Re: [PATCH v3 4/6] arm64: dts: imx93: Add LCDIF & LDB nodes

[Frank Li <Frank.li@nxp.com>]

On Tue, Mar 04, 2025 at 04:49:23PM +0100, Alexander Stein wrote:
> LCDIF port 1 is directly attached to the LVDS Display Bridge (LDB).
> Both need the same clock source (VIDEO_PLL1).
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  arch/arm64/boot/dts/freescale/imx93.dtsi | 77 ++++++++++++++++++++++++
>  1 file changed, 77 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
> index 56766fdb0b1e5..69a639a8c833f 100644
> --- a/arch/arm64/boot/dts/freescale/imx93.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
> @@ -1273,6 +1273,9 @@ s4muap: mailbox@47520000 {
>  		media_blk_ctrl: system-controller@4ac10000 {
>  			compatible = "fsl,imx93-media-blk-ctrl", "syscon";
>  			reg = <0x4ac10000 0x10000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0x4ac10000 0x10000>;

I remember ranges should be after reg.

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  			power-domains = <&mediamix>;
>  			clocks = <&clk IMX93_CLK_MEDIA_APB>,
>  				 <&clk IMX93_CLK_MEDIA_AXI>,
> @@ -1286,8 +1289,82 @@ media_blk_ctrl: system-controller@4ac10000 {
>  				 <&clk IMX93_CLK_MIPI_DSI_GATE>;
>  			clock-names = "apb", "axi", "nic", "disp", "cam",
>  				      "pxp", "lcdif", "isi", "csi", "dsi";
> +			assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>,
> +					  <&clk IMX93_CLK_MEDIA_APB>,
> +					  <&clk IMX93_CLK_VIDEO_PLL>,
> +					  <&clk IMX93_CLK_MEDIA_DISP_PIX>;
> +			assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD0>,
> +						 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
> +						 <&clk IMX93_CLK_24M>,
> +						 <&clk IMX93_CLK_VIDEO_PLL>;
> +			assigned-clock-rates = <333333333>, <133333333>, <0>, <200000000>;
>  			#power-domain-cells = <1>;
>  			status = "disabled";
> +
> +			lvds_bridge: bridge@20 {
> +				compatible = "fsl,imx93-ldb";
> +				reg = <0x20 0x4>, <0x24 0x4>;
> +				reg-names = "ldb", "lvds";
> +				clocks = <&clk IMX93_CLK_LVDS_GATE>;
> +				clock-names = "ldb";
> +				assigned-clocks = <&clk IMX93_CLK_MEDIA_LDB>;
> +				assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>;
> +				status = "disabled";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +
> +						ldb_from_lcdif: endpoint {
> +							remote-endpoint = <&lcdif_to_ldb>;
> +						};
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +
> +						ldb_lvds: endpoint {
> +						};
> +					};
> +				};
> +			};
> +		};
> +
> +		lcdif: display-controller@4ae30000 {
> +			compatible = "fsl,imx93-lcdif";
> +			reg = <0x4ae30000 0x23c>;
> +			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clk IMX93_CLK_MEDIA_DISP_PIX>,
> +				 <&clk IMX93_CLK_LCDIF_GATE>,
> +				 <&clk IMX93_CLK_MEDIA_AXI>;
> +			clock-names = "pix", "axi", "disp_axi";
> +			assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>,
> +					  <&clk IMX93_CLK_MEDIA_DISP_PIX>;
> +			assigned-clock-parents = <&clk IMX93_CLK_24M>,
> +						 <&clk IMX93_CLK_VIDEO_PLL>;
> +			power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_LCDIF>;
> +			status = "disabled";
> +
> +			port {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				lcdif_to_dsi: endpoint@0 {
> +					reg = <0>;
> +				};
> +
> +				lcdif_to_ldb: endpoint@1 {
> +					reg = <1>;
> +					remote-endpoint = <&ldb_from_lcdif>;
> +				};
> +
> +				lcdif_to_dpi: endpoint@2 {
> +					reg = <2>;
> +				};
> +			};
>  		};
>
>  		usbotg1: usb@4c100000 {
> --
> 2.43.0
>