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[79.144.194.54]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd426c33asm9222345e9.3.2025.03.04.23.36.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 23:36:28 -0800 (PST) From: Jorge Ramirez X-Google-Original-From: Jorge Ramirez Date: Wed, 5 Mar 2025 08:36:26 +0100 To: Bjorn Andersson Cc: Krzysztof Kozlowski , Krishna Chaitanya Chundru , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , chaitanya chundru , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski , quic_vbadigan@quicnic.com, amitk@kernel.org, dmitry.baryshkov@linaro.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com Subject: Re: [PATCH v4 09/10] dt-bindings: PCI: qcom,pcie-sc7280: Add 'global' interrupt Message-ID: References: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> <20250225-qps615_v4_1-v4-9-e08633a7bdf8@oss.qualcomm.com> <20250226-enlightened-chachalaca-of-artistry-2de5ea@krzk-bin> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-GUID: AxFXfJoIWllouIis-EMRMf4bHnh0WnH2 X-Authority-Analysis: v=2.4 cv=KfMosRYD c=1 sm=1 tr=0 ts=67c7fefe cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=cl0az7d0LwC7qAhl51RXhA==:17 a=kj9zAlcOel0A:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=9WSsZrPlu9oLnKen9MIA:9 a=CjuIK1q_8ugA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-ORIG-GUID: AxFXfJoIWllouIis-EMRMf4bHnh0WnH2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-05_03,2025-03-05_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 phishscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 impostorscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503050059 On 26/02/25 10:29:43, Bjorn Andersson wrote: > On Wed, Feb 26, 2025 at 08:32:42AM +0100, Krzysztof Kozlowski wrote: > > On Tue, Feb 25, 2025 at 03:04:06PM +0530, Krishna Chaitanya Chundru wrote: > > > Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt > > > to the host CPU. This interrupt can be used by the device driver to handle > > > PCIe link specific events such as Link up and Link down, which give the > > > driver a chance to start bus enumeration on its own when link is up and > > > initiate link training if link goes to a bad state. The PCIe driver can > > > still work without this interrupt but it will provide a nice user > > > experience when device gets plugged and removed. > > > > > > Hence, document it in the binding along with the existing MSI interrupts. > > > Global interrupt is parsed as optional in driver, so adding it in bindings > > > will not break the ABI. > > > > > > Signed-off-by: Krishna Chaitanya Chundru > > > --- > > > Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 8 +++++--- > > > 1 file changed, 5 insertions(+), 3 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml > > > index 76cb9fbfd476..7ae09ba8da60 100644 > > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml > > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml > > > @@ -54,7 +54,7 @@ properties: > > > > > > interrupts: > > > minItems: 8 > > > - maxItems: 8 > > > + maxItems: 9 > > > > > > interrupt-names: > > > items: > > > @@ -66,6 +66,7 @@ properties: > > > - const: msi5 > > > - const: msi6 > > > - const: msi7 > > > + - const: global > > > > Either context is missing or these are not synced with interrupts. > > > > I think the patch context ("properties") is confusing here, but it looks > to me that these are in sync: interrupts is defined to have 8 items, and > interrupt-names is a list of msi0 through msi7. > > @Krishna, these two last patches (adding the global interrupt) doesn't > seem strongly connected to the switch patches. So, if Krzysztof agrees > with above assessment, please submit them separately (i.e. a new series, > 2 patches, v5). um, but without these two patches, the functionality is broken requiring users to manually rescan the pci bus (ie, via sysfs) to see what is behind the bridge. shouldnt the set include all the necessary patches? > > Regards, > Bjorn > > > Best regards, > > Krzysztof > >