[PATCH 0/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[PATCH 0/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[Chukun Pan]

Same as RK3568, RK3528 uses SCMI clk instead of standard ARMCLK.
Add SCMI clk for CPU, GPU and RNG will also use it.

dmesg:
[    0.061333] scmi_core: SCMI protocol bus registered
[    0.125780] scmi_protocol scmi_dev.1: Enabled polling mode TX channel - prot_id:16
[    0.126628] arm-scmi firmware:scmi: SCMI Notifications - Core Enabled.
[    0.127233] arm-scmi firmware:scmi: SCMI Protocol v2.0 'rockchip:' Firmware version 0x0

CPU frequency: ~# mhz
count=611657 us50=19994 us250=99945 diff=79951 cpu_MHz=1530.080

Chukun Pan (1):
  arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

 arch/arm64/boot/dts/rockchip/rk3528.dtsi | 32 ++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

-- 
2.25.1

[PATCH 1/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[Chukun Pan]

Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK.
Add SCMI clk for CPU, GPU and RNG will also use it.

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
 arch/arm64/boot/dts/rockchip/rk3528.dtsi | 32 ++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index 0c0e7f151462..aa68c2fef2f3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -59,6 +59,7 @@ cpu0: cpu@0 {
 			reg = <0x0>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&scmi_clk SCMI_CLK_CPU>;
 		};
 
 		cpu1: cpu@1 {
@@ -66,6 +67,7 @@ cpu1: cpu@1 {
 			reg = <0x1>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&scmi_clk SCMI_CLK_CPU>;
 		};
 
 		cpu2: cpu@2 {
@@ -73,6 +75,7 @@ cpu2: cpu@2 {
 			reg = <0x2>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&scmi_clk SCMI_CLK_CPU>;
 		};
 
 		cpu3: cpu@3 {
@@ -80,6 +83,22 @@ cpu3: cpu@3 {
 			reg = <0x3>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&scmi_clk SCMI_CLK_CPU>;
+		};
+	};
+
+	firmware {
+		scmi: scmi {
+			compatible = "arm,scmi-smc";
+			arm,smc-id = <0x82000010>;
+			shmem = <&scmi_shmem>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
 		};
 	};
 
@@ -110,6 +129,19 @@ gmac0_clk: clock-gmac50m {
 		#clock-cells = <0>;
 	};
 
+	sram@10f000 {
+		compatible = "mmio-sram";
+		reg = <0x0 0x0010f000 0x0 0x100>;
+		ranges = <0 0x0 0x0010f000 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		scmi_shmem: sram@0 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x0 0x100>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
-- 
2.25.1

Re: [PATCH 1/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[Heiko Stübner]

Hi,

Am Donnerstag, 6. März 2025, 14:10:16 MEZ schrieb Chukun Pan:
> Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK.
> Add SCMI clk for CPU, GPU and RNG will also use it.
> 
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> ---

> @@ -110,6 +129,19 @@ gmac0_clk: clock-gmac50m {
>  		#clock-cells = <0>;
>  	};
>  
> +	sram@10f000 {

That sram is part of the soc (and has an mmio-address), so I'd think
it should live inside the soc node?


Heiko

Re: [PATCH 1/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[Chukun Pan]

Hi,

> That sram is part of the soc (and has an mmio-address), so I'd think
> it should live inside the soc node?

But soc ranges starts from 0xfe000000, I don't know whether to change it.
And all other nodes are 0xf..., except this sram.
Any suggestions would be greatly appreciated.

Thanks,
Chukun

-- 
2.25.1

Re: [PATCH 1/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[Krzysztof Kozlowski]

On 06/03/2025 14:40, Chukun Pan wrote:
> Hi,
> 
>> That sram is part of the soc (and has an mmio-address), so I'd think
>> it should live inside the soc node?
> 
> But soc ranges starts from 0xfe000000, I don't know whether to change it.
> And all other nodes are 0xf..., except this sram.

Maybe they are wrong?

> Any suggestions would be greatly appreciated.
Where is the SRAM located? Inside the SoC or is it carved out external
ROM/RAM?

Best regards,
Krzysztof

Re: [PATCH 1/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[Heiko Stübner]

Am Donnerstag, 6. März 2025, 14:40:02 MEZ schrieb Chukun Pan:
> Hi,
> 
> > That sram is part of the soc (and has an mmio-address), so I'd think
> > it should live inside the soc node?
> 
> But soc ranges starts from 0xfe000000, I don't know whether to change it.
> And all other nodes are 0xf..., except this sram.
> Any suggestions would be greatly appreciated.

darn ... I didn't realize that this is not sram, but main memory :-)

in freescale/s32g3.dtsi and blaize/blaize-blzp1600.dtsi I see structures like:

        reserved-memory  {
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
                
                scmi_shmem: shm@d0000000 {
                        compatible = "arm,scmi-shmem";
                        reg = <0x0 0xd0000000 0x0 0x80>;
                        no-map;
                };
        };

does something like this work on the rk3528?

Heiko

Re: [PATCH 1/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[Krzysztof Kozlowski]

On 06/03/2025 14:51, Heiko Stübner wrote:
> Am Donnerstag, 6. März 2025, 14:40:02 MEZ schrieb Chukun Pan:
>> Hi,
>>
>>> That sram is part of the soc (and has an mmio-address), so I'd think
>>> it should live inside the soc node?
>>
>> But soc ranges starts from 0xfe000000, I don't know whether to change it.
>> And all other nodes are 0xf..., except this sram.
>> Any suggestions would be greatly appreciated.
> 
> darn ... I didn't realize that this is not sram, but main memory :-)


Heh, I think carving out reserved blocks from the main RAM and calling
it a SRAM is a stretch.

Best regards,
Krzysztof

Re: [PATCH 1/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[Heiko Stübner]

Am Donnerstag, 6. März 2025, 14:54:04 MEZ schrieb Krzysztof Kozlowski:
> On 06/03/2025 14:51, Heiko Stübner wrote:
> > Am Donnerstag, 6. März 2025, 14:40:02 MEZ schrieb Chukun Pan:
> >> Hi,
> >>
> >>> That sram is part of the soc (and has an mmio-address), so I'd think
> >>> it should live inside the soc node?
> >>
> >> But soc ranges starts from 0xfe000000, I don't know whether to change it.
> >> And all other nodes are 0xf..., except this sram.
> >> Any suggestions would be greatly appreciated.
> > 
> > darn ... I didn't realize that this is not sram, but main memory :-)
> 
> 
> Heh, I think carving out reserved blocks from the main RAM and calling
> it a SRAM is a stretch.

yep, hence going with the reserved memory instead
and not trying to call it sram :-)

And I just saw rk3576 has the same issue, only that there
the mmio area is sitting before the main memory address space

Re: [PATCH 1/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[Chukun Pan]

Hi,

>> Any suggestions would be greatly appreciated.
> Where is the SRAM located? Inside the SoC or is it carved out external
> ROM/RAM?

It is located in the SoC.
"Embedded Memory" Area:
BootROM | PMU_SRAM (8KB) | SYSTEM_SRAM (64KB) | OTP

Thanks,
Chukun

-- 
2.25.1

Re: [PATCH 1/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[Heiko Stübner]

Am Donnerstag, 6. März 2025, 15:20:08 MEZ schrieb Chukun Pan:
> Hi,
> 
> >> Any suggestions would be greatly appreciated.
> > Where is the SRAM located? Inside the SoC or is it carved out external
> > ROM/RAM?
> 
> It is located in the SoC.
> "Embedded Memory" Area:
> BootROM | PMU_SRAM (8KB) | SYSTEM_SRAM (64KB) | OTP

are you really sure about that?

Looking at Jonas' recent rk3528 u-boot series [0]
0x0 _to_ 0xfc000000 is the SDRAM memory area
so 0x10f000 is a carveout of the main sdram.


Heiko


[0] https://lists.denx.de/pipermail/u-boot/2025-January/578393.html

Re: [PATCH 1/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[Chukun Pan]

Hi,

> are you really sure about that?
>
> Looking at Jonas' recent rk3528 u-boot series [0]
> 0x0 _to_ 0xfc000000 is the SDRAM memory area
> so 0x10f000 is a carveout of the main sdram.

Sorry, I was misled by the dtsi of rk3568.
Put it in reserved-memory works on rk3528:

~# dmesg | grep scmi
[    0.061452] scmi_core: SCMI protocol bus registered
[    0.125903] scmi_protocol scmi_dev.1: Enabled polling mode TX channel - prot_id:16
[    0.126763] arm-scmi firmware:scmi: SCMI Notifications - Core Enabled.
[    0.127368] arm-scmi firmware:scmi: SCMI Protocol v2.0 'rockchip:' Firmware version 0x0

Should we change this for rk3568 as well?

Thanks,
Chukun

-- 
2.25.1

Re: [PATCH 1/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[Jonas Karlman]

Hi Chukun,

On 2025-03-06 14:10, Chukun Pan wrote:
> Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK.
> Add SCMI clk for CPU, GPU and RNG will also use it.
> 
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> ---
>  arch/arm64/boot/dts/rockchip/rk3528.dtsi | 32 ++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> index 0c0e7f151462..aa68c2fef2f3 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> @@ -59,6 +59,7 @@ cpu0: cpu@0 {
>  			reg = <0x0>;
>  			device_type = "cpu";
>  			enable-method = "psci";
> +			clocks = <&scmi_clk SCMI_CLK_CPU>;
>  		};
>  
>  		cpu1: cpu@1 {
> @@ -66,6 +67,7 @@ cpu1: cpu@1 {
>  			reg = <0x1>;
>  			device_type = "cpu";
>  			enable-method = "psci";
> +			clocks = <&scmi_clk SCMI_CLK_CPU>;
>  		};
>  
>  		cpu2: cpu@2 {
> @@ -73,6 +75,7 @@ cpu2: cpu@2 {
>  			reg = <0x2>;
>  			device_type = "cpu";
>  			enable-method = "psci";
> +			clocks = <&scmi_clk SCMI_CLK_CPU>;
>  		};
>  
>  		cpu3: cpu@3 {
> @@ -80,6 +83,22 @@ cpu3: cpu@3 {
>  			reg = <0x3>;
>  			device_type = "cpu";
>  			enable-method = "psci";
> +			clocks = <&scmi_clk SCMI_CLK_CPU>;
> +		};
> +	};
> +
> +	firmware {
> +		scmi: scmi {
> +			compatible = "arm,scmi-smc";
> +			arm,smc-id = <0x82000010>;
> +			shmem = <&scmi_shmem>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			scmi_clk: protocol@14 {
> +				reg = <0x14>;
> +				#clock-cells = <1>;
> +			};
>  		};
>  	};
>  
> @@ -110,6 +129,19 @@ gmac0_clk: clock-gmac50m {
>  		#clock-cells = <0>;
>  	};
>  
> +	sram@10f000 {
> +		compatible = "mmio-sram";
> +		reg = <0x0 0x0010f000 0x0 0x100>;
> +		ranges = <0 0x0 0x0010f000 0x100>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		scmi_shmem: sram@0 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0x0 0x100>;
> +		};
> +	};

This does not look correct, the shared memory is located in DRAM not in
SRAM. I used reserved-memory in my work-in-progress commit for adding
the GPU [1], something like, not sure if this is more correct:

	reserved-memory  {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		scmi_shmem: scmi-shmem@10f000 {
			compatible = "arm,scmi-shmem";
			reg = <0x0 0x0010f000 0x0 0x100>;
			no-map;
		};
	};

[1] https://github.com/Kwiboo/linux-rockchip/commit/f1cd58b2431a01e8cf6a430922204a71fee484f3

Regards,
Jonas

> +
>  	soc {
>  		compatible = "simple-bus";
>  		ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;

Re: [PATCH 1/1] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC

[Sudeep Holla]

On Thu, Mar 06, 2025 at 09:10:16PM +0800, Chukun Pan wrote:
> Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK.
> Add SCMI clk for CPU, GPU and RNG will also use it.
> 

It is highly recommended not to use clock protocol for CPUs and GPUs
especially if the plan is to drive regulators separately. Please use
the performance protocol instead which can abstract the clock and the
regulator details for the OS.

-- 
Regards,
Sudeep