* [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF
@ 2025-03-18 23:58 Christian Marangi
2025-03-18 23:58 ` [net-next PATCH 1/6] net: phylink: reset PCS-Phylink double reference on phylink_stop Christian Marangi
` (7 more replies)
0 siblings, 8 replies; 34+ messages in thread
From: Christian Marangi @ 2025-03-18 23:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Russell King, Philipp Zabel, Christian Marangi,
Daniel Golle, netdev, devicetree, linux-kernel, upstream
This series introduce a most awaited feature that is correctly
provide PCS with OF without having to use specific export symbol.
The concept is to implement a producer-consumer API similar to other
subsystem like clock or PHY.
That seems to be the best solution to the problem as PCS driver needs
to be detached from phylink and implement a simple way to provide a
PCS while maintaining support for probe defer or driver removal.
To keep the implementation simple, the PCS driver devs needs some
collaboration to correctly implement this. This is O.K. as helper
to correctly implement this are provided hence it's really a matter
of following a pattern to correct follow removal of a PCS driver.
A PCS provider have to implement and call of_pcs_add_provider() in
probe function and define an xlate function to define how the PCS
should be provided based on the requested interface and phandle spec
defined in DT (based on the #pcs-cells)
of_pcs_get() is provided to provide a specific PCS declared in DT
an index.
A simple xlate function is provided for simple single PCS
implementation, of_pcs_simple_get.
A PCS provider on driver removal should first call
phylink_pcs_release() to release the PCS from phylink and then
delete itself as a provider with of_pcs_del_provider() helper.
A PCS declared with a PCS provider implementation can be used
by declaring in the MAC OPs the .mac_select_pcs with the helper
of_phylink_mac_select_pcs().
This helper will just try every phandle declared in "pcs-handle"
until one supported for the requested interface is found.
A user for this new implementation is provided as an Airoha PCS
driver. This was also tested downstream with the IPQ95xx QCOM SoC
and with the help of Daniel also on the various Mediatek MT7988
SoC with both SFP cage implementation and DSA attached.
Lots of tests were done with driver unbind/bind and with interface
up/down. It was initially used phylink_stop to handle PCS driver
removal, but it was then decided to use dev_close with
phylink_pcs_release() as it does better handle interface drop
and communicate more info to the user than leaving the interface
in a dangling state.
Christian Marangi (6):
net: phylink: reset PCS-Phylink double reference on phylink_stop
net: pcs: Implement OF support for PCS driver
net: phylink: Correctly handle PCS probe defer from PCS provider
dt-bindings: net: ethernet-controller: permit to define multiple PCS
net: pcs: airoha: add PCS driver for Airoha SoC
dt-bindings: net: pcs: Document support for Airoha Ethernet PCS
.../bindings/net/ethernet-controller.yaml | 2 -
.../bindings/net/pcs/airoha,pcs.yaml | 112 +
drivers/net/pcs/Kconfig | 13 +
drivers/net/pcs/Makefile | 2 +
drivers/net/pcs/pcs-airoha.c | 2858 +++++++++++++++++
drivers/net/pcs/pcs.c | 185 ++
drivers/net/phy/phylink.c | 46 +-
include/linux/pcs/pcs-airoha.h | 11 +
include/linux/pcs/pcs-provider.h | 46 +
include/linux/pcs/pcs.h | 62 +
include/linux/phylink.h | 2 +
11 files changed, 3336 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
create mode 100644 drivers/net/pcs/pcs-airoha.c
create mode 100644 drivers/net/pcs/pcs.c
create mode 100644 include/linux/pcs/pcs-airoha.h
create mode 100644 include/linux/pcs/pcs-provider.h
create mode 100644 include/linux/pcs/pcs.h
--
2.48.1
^ permalink raw reply [flat|nested] 34+ messages in thread
* [net-next PATCH 1/6] net: phylink: reset PCS-Phylink double reference on phylink_stop
2025-03-18 23:58 [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF Christian Marangi
@ 2025-03-18 23:58 ` Christian Marangi
2025-03-18 23:58 ` [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver Christian Marangi
` (6 subsequent siblings)
7 siblings, 0 replies; 34+ messages in thread
From: Christian Marangi @ 2025-03-18 23:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Russell King, Philipp Zabel, Christian Marangi,
Daniel Golle, netdev, devicetree, linux-kernel, upstream
On calling phylink_stop, the double reference between PCS and Phylink is
never reset. This is OK in the current rudimental implementation of PCS
as current PCS driver doesn't autonomously handle link termination (or
actually doesn't handle removal of the PCS driver at all)
But this immediately became problematic if the PCS driver makes use of
this double reference to track if the PCS have an actual user attached.
If a driver makes use of this and the double reference is not reset, the
driver might erroneously detect the PCS have a user and execute stop
operation even if not actually used. (causing unwanted link termination)
To permit PCS driver to detect this correctly, and to better handle this
similar to how it done with phylink_major_config, set to NULL the double
reference between PCS and Phylink on phylink_stop.
On phylink_major_config, PCS is always refreshed by calling
mac_select_pcs hence it's save to always reset it in phylink_stop.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/phy/phylink.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 76b1a329607b..eef1712ec22c 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -2589,6 +2589,9 @@ void phylink_stop(struct phylink *pl)
pl->pcs_state = PCS_STATE_DOWN;
phylink_pcs_disable(pl->pcs);
+ if (pl->pcs)
+ pl->pcs->phylink = NULL;
+ pl->pcs = NULL;
}
EXPORT_SYMBOL_GPL(phylink_stop);
--
2.48.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver
2025-03-18 23:58 [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF Christian Marangi
2025-03-18 23:58 ` [net-next PATCH 1/6] net: phylink: reset PCS-Phylink double reference on phylink_stop Christian Marangi
@ 2025-03-18 23:58 ` Christian Marangi
2025-03-19 9:11 ` Christian Marangi
` (4 more replies)
2025-03-18 23:58 ` [net-next PATCH 3/6] net: phylink: Correctly handle PCS probe defer from PCS provider Christian Marangi
` (5 subsequent siblings)
7 siblings, 5 replies; 34+ messages in thread
From: Christian Marangi @ 2025-03-18 23:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Russell King, Philipp Zabel, Christian Marangi,
Daniel Golle, netdev, devicetree, linux-kernel, upstream
Implement the foundation of OF support for PCS driver.
To support this, implement a simple Provider API where a PCS driver can
expose multiple PCS with an xlate .get function.
PCS driver will have to call of_pcs_add_provider() and pass the device
node pointer and a xlate function to return the correct PCS for the
requested interface and the passed #pcs-cells.
This will register the PCS in a global list of providers so that
consumer can access it.
Consumer will then use of_pcs_get() to get the actual PCS by passing the
device_node pointer, the index for #pcs-cells and the requested
interface.
For simple implementation where #pcs-cells is 0 and the PCS driver
expose a single PCS, the xlate function of_pcs_simple_get() is
provided. In such case the passed interface is ignored and is expected
that the PCS supports any interface mode supported by the MAC.
For advanced implementation a custom xlate function is required. Such
function should return an error if the PCS is not supported for the
requested interface type.
This is needed for the correct function of of_phylink_mac_select_pcs()
later described.
PCS driver on removal should first call phylink_pcs_release() on every
PCS the driver provides and then correctly delete as a provider with
the usage of of_pcs_del_provider().
A generic function for .mac_select_pcs is provided for any MAC driver
that will declare PCS in DT, of_phylink_mac_select_pcs().
This function will parse "pcs-handle" property and will try every PCS
declared in DT until one that supports the requested interface type is
found. This works by leveraging the return value of the xlate function
returned by of_pcs_get() and checking if it's an ERROR or NULL, in such
case the next PCS in the phandle array is tested.
Some additional helper are provided for xlate functions,
pcs_supports_interface() as a simple function to check if the requested
interface is supported by the PCS and phylink_pcs_release() to release a
PCS from a phylink instance.
Co-developed-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/pcs/Kconfig | 7 ++
drivers/net/pcs/Makefile | 1 +
drivers/net/pcs/pcs.c | 185 +++++++++++++++++++++++++++++++
drivers/net/phy/phylink.c | 21 ++++
include/linux/pcs/pcs-provider.h | 46 ++++++++
include/linux/pcs/pcs.h | 62 +++++++++++
include/linux/phylink.h | 2 +
7 files changed, 324 insertions(+)
create mode 100644 drivers/net/pcs/pcs.c
create mode 100644 include/linux/pcs/pcs-provider.h
create mode 100644 include/linux/pcs/pcs.h
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index f6aa437473de..8c3b720de6fd 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -5,6 +5,13 @@
menu "PCS device drivers"
+config OF_PCS
+ tristate
+ depends on OF
+ depends on PHYLINK
+ help
+ OpenFirmware PCS accessors
+
config PCS_XPCS
tristate "Synopsys DesignWare Ethernet XPCS"
select PHYLINK
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index 4f7920618b90..29881f0f981f 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Makefile for Linux PCS drivers
+obj-$(CONFIG_OF_PCS) += pcs.o
pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
pcs-xpcs-nxp.o pcs-xpcs-wx.o
diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
new file mode 100644
index 000000000000..af04a76ef825
--- /dev/null
+++ b/drivers/net/pcs/pcs.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/phylink.h>
+#include <linux/pcs/pcs.h>
+#include <linux/pcs/pcs-provider.h>
+
+struct of_pcs_provider {
+ struct list_head link;
+
+ struct device_node *node;
+ struct phylink_pcs *(*get)(struct of_phandle_args *pcsspec,
+ void *data,
+ phy_interface_t interface);
+
+ void *data;
+};
+
+static LIST_HEAD(of_pcs_providers);
+static DEFINE_MUTEX(of_pcs_mutex);
+
+struct phylink_pcs *of_pcs_simple_get(struct of_phandle_args *pcsspec, void *data,
+ phy_interface_t interface)
+{
+ struct phylink_pcs *pcs = data;
+
+ if (!pcs_supports_interface(pcs, interface))
+ return ERR_PTR(-EOPNOTSUPP);
+
+ return data;
+}
+EXPORT_SYMBOL_GPL(of_pcs_simple_get);
+
+int of_pcs_add_provider(struct device_node *np,
+ struct phylink_pcs *(*get)(struct of_phandle_args *pcsspec,
+ void *data,
+ phy_interface_t interface),
+ void *data)
+{
+ struct of_pcs_provider *pp;
+
+ if (!np)
+ return 0;
+
+ pp = kzalloc(sizeof(*pp), GFP_KERNEL);
+ if (!pp)
+ return -ENOMEM;
+
+ pp->node = of_node_get(np);
+ pp->data = data;
+ pp->get = get;
+
+ mutex_lock(&of_pcs_mutex);
+ list_add(&pp->link, &of_pcs_providers);
+ mutex_unlock(&of_pcs_mutex);
+ pr_debug("Added pcs provider from %pOF\n", np);
+
+ fwnode_dev_initialized(&np->fwnode, true);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(of_pcs_add_provider);
+
+void of_pcs_del_provider(struct device_node *np)
+{
+ struct of_pcs_provider *pp;
+
+ if (!np)
+ return;
+
+ mutex_lock(&of_pcs_mutex);
+ list_for_each_entry(pp, &of_pcs_providers, link) {
+ if (pp->node == np) {
+ list_del(&pp->link);
+ fwnode_dev_initialized(&np->fwnode, false);
+ of_node_put(pp->node);
+ kfree(pp);
+ break;
+ }
+ }
+ mutex_unlock(&of_pcs_mutex);
+}
+EXPORT_SYMBOL_GPL(of_pcs_del_provider);
+
+static int of_parse_pcsspec(const struct device_node *np, int index,
+ const char *name, struct of_phandle_args *out_args)
+{
+ int ret = -ENOENT;
+
+ if (!np)
+ return -ENOENT;
+
+ if (name)
+ index = of_property_match_string(np, "pcs-names", name);
+
+ ret = of_parse_phandle_with_args(np, "pcs-handle", "#pcs-cells",
+ index, out_args);
+ if (ret || (name && index < 0))
+ return ret;
+
+ return 0;
+}
+
+static struct phylink_pcs *
+of_pcs_get_from_pcsspec(struct of_phandle_args *pcsspec,
+ phy_interface_t interface)
+{
+ struct of_pcs_provider *provider;
+ struct phylink_pcs *pcs = ERR_PTR(-EPROBE_DEFER);
+
+ if (!pcsspec)
+ return ERR_PTR(-EINVAL);
+
+ mutex_lock(&of_pcs_mutex);
+ list_for_each_entry(provider, &of_pcs_providers, link) {
+ if (provider->node == pcsspec->np) {
+ pcs = provider->get(pcsspec, provider->data,
+ interface);
+ if (!IS_ERR(pcs))
+ break;
+ }
+ }
+ mutex_unlock(&of_pcs_mutex);
+
+ return pcs;
+}
+
+static struct phylink_pcs *__of_pcs_get(struct device_node *np, int index,
+ const char *con_id,
+ phy_interface_t interface)
+{
+ struct of_phandle_args pcsspec;
+ struct phylink_pcs *pcs;
+ int ret;
+
+ ret = of_parse_pcsspec(np, index, con_id, &pcsspec);
+ if (ret)
+ return ERR_PTR(ret);
+
+ pcs = of_pcs_get_from_pcsspec(&pcsspec, interface);
+ of_node_put(pcsspec.np);
+
+ return pcs;
+}
+
+struct phylink_pcs *of_pcs_get(struct device_node *np, int index,
+ phy_interface_t interface)
+{
+ return __of_pcs_get(np, index, NULL, interface);
+}
+EXPORT_SYMBOL_GPL(of_pcs_get);
+
+struct phylink_pcs *of_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+{
+ int i, count;
+ struct device *dev = config->dev;
+ struct device_node *np = dev->of_node;
+ struct phylink_pcs *pcs = ERR_PTR(-ENODEV);
+
+ /* To enable using_mac_select_pcs on phylink_create */
+ if (interface == PHY_INTERFACE_MODE_NA)
+ return NULL;
+
+ /* Reject configuring PCS with Internal mode */
+ if (interface == PHY_INTERFACE_MODE_INTERNAL)
+ return ERR_PTR(-EINVAL);
+
+ if (!of_property_present(np, "pcs-handle"))
+ return pcs;
+
+ count = of_count_phandle_with_args(np, "pcs-handle", "#pcs-cells");
+ if (count < 0)
+ return ERR_PTR(count);
+
+ for (i = 0; i < count; i++) {
+ pcs = of_pcs_get(np, i, interface);
+ if (!IS_ERR_OR_NULL(pcs))
+ return pcs;
+ }
+
+ return pcs;
+}
+EXPORT_SYMBOL_GPL(of_phylink_mac_select_pcs);
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index eef1712ec22c..7f71547e89fe 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -1130,6 +1130,27 @@ int phylink_pcs_pre_init(struct phylink *pl, struct phylink_pcs *pcs)
}
EXPORT_SYMBOL_GPL(phylink_pcs_pre_init);
+/**
+ * phylink_pcs_release() - release a PCS
+ * @pl: a pointer to &struct phylink_pcs
+ *
+ * PCS provider can use this to release a PCS from a phylink
+ * instance by stopping the attached netdev. This is only done
+ * if the PCS is actually attached to a phylink, otherwise is
+ * ignored.
+ */
+void phylink_pcs_release(struct phylink_pcs *pcs)
+{
+ struct phylink *pl = pcs->phylink;
+
+ if (pl) {
+ rtnl_lock();
+ dev_close(pl->netdev);
+ rtnl_unlock();
+ }
+}
+EXPORT_SYMBOL_GPL(phylink_pcs_release);
+
static void phylink_mac_config(struct phylink *pl,
const struct phylink_link_state *state)
{
diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
new file mode 100644
index 000000000000..0172d0286f07
--- /dev/null
+++ b/include/linux/pcs/pcs-provider.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_PROVIDER_H
+#define __LINUX_PCS_PROVIDER_H
+
+#include <linux/phy.h>
+
+/**
+ * of_pcs_simple_get - Simple xlate function to retrieve PCS
+ * @pcsspec: Phandle arguments
+ * @data: Context data (assumed assigned to the single PCS)
+ * @interface: requested PHY interface type for PCS
+ *
+ * Returns the PCS (pointed by data) or an -EOPNOTSUPP pointer
+ * if the PCS doesn't support the requested interface.
+ */
+struct phylink_pcs *of_pcs_simple_get(struct of_phandle_args *pcsspec, void *data,
+ phy_interface_t interface);
+
+/**
+ * of_pcs_add_provider - Registers a new PCS provider
+ * @np: Device node
+ * @get: xlate function to retrieve the PCS
+ * @data: Context data
+ *
+ * Register and add a new PCS to the global providers list
+ * for the device node. A function to get the PCS from
+ * device node with the use of phandle args.
+ * To the get function is also passed the interface type
+ * requested for the PHY. PCS driver will use the passed
+ * interface to understand if the PCS can support it or not.
+ *
+ * Returns 0 on success or -ENOMEM on allocation failure.
+ */
+int of_pcs_add_provider(struct device_node *np,
+ struct phylink_pcs *(*get)(struct of_phandle_args *pcsspec,
+ void *data,
+ phy_interface_t interface),
+ void *data);
+
+/**
+ * of_pcs_del_provider - Removes a PCS provider
+ * @np: Device node
+ */
+void of_pcs_del_provider(struct device_node *np);
+
+#endif /* __LINUX_PCS_PROVIDER_H */
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
new file mode 100644
index 000000000000..b681bf05ac08
--- /dev/null
+++ b/include/linux/pcs/pcs.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_H
+#define __LINUX_PCS_H
+
+#include <linux/phy.h>
+#include <linux/phylink.h>
+
+static inline bool pcs_supports_interface(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ return test_bit(interface, pcs->supported_interfaces);
+}
+
+#ifdef CONFIG_OF_PCS
+/**
+ * of_pcs_get - Retrieves a PCS from a device node
+ * @np: Device node
+ * @index: Index of PCS handle in Device Node
+ * @interface: requested PHY interface type for PCS
+ *
+ * Get a PCS for the requested PHY interface type from the
+ * device node at index.
+ *
+ * Returns a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -EPROBE_DEFER if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed)
+ */
+struct phylink_pcs *of_pcs_get(struct device_node *np, int index,
+ phy_interface_t interface);
+
+/**
+ * of_phylink_mac_select_pcs - Generic MAC select pcs for OF PCS provider
+ * @config: phylink config pointer
+ * @interface: requested PHY interface type for PCS
+ *
+ * Generic helper function to get a PCS from a "pcs-handle" OF property
+ * defined in device tree. Each phandle defined in "pcs-handle" will be
+ * tested until a PCS that supports the requested PHY interface is found.
+ *
+ * Returns a pointer to the selected PCS or an error pointer.
+ * Return NULL for PHY_INTERFACE_MODE_NA and a -EINVAL error pointer
+ * for PHY_INTERFACE_MODE_INTERNAL. It can also return -EPROBE_DEFER,
+ * refer to of_pcs_get for details about it.
+ */
+struct phylink_pcs *of_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface);
+#else
+static inline struct phylink_pcs *of_pcs_get(struct device_node *np, int index,
+ phy_interface_t interface)
+{
+ return PTR_ERR(-ENOENT);
+}
+
+static inline struct phylink_pcs *of_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+{
+ return PTR_ERR(-EOPNOTSUPP);
+}
+#endif
+
+#endif /* __LINUX_PCS_H */
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index c187267a15b6..80367d4fbad9 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -695,6 +695,8 @@ void phylink_pcs_change(struct phylink_pcs *, bool up);
int phylink_pcs_pre_init(struct phylink *pl, struct phylink_pcs *pcs);
+void phylink_pcs_release(struct phylink_pcs *pcs);
+
void phylink_start(struct phylink *);
void phylink_stop(struct phylink *);
--
2.48.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [net-next PATCH 3/6] net: phylink: Correctly handle PCS probe defer from PCS provider
2025-03-18 23:58 [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF Christian Marangi
2025-03-18 23:58 ` [net-next PATCH 1/6] net: phylink: reset PCS-Phylink double reference on phylink_stop Christian Marangi
2025-03-18 23:58 ` [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver Christian Marangi
@ 2025-03-18 23:58 ` Christian Marangi
2025-03-19 15:58 ` Russell King (Oracle)
2025-03-18 23:58 ` [net-next PATCH 4/6] dt-bindings: net: ethernet-controller: permit to define multiple PCS Christian Marangi
` (4 subsequent siblings)
7 siblings, 1 reply; 34+ messages in thread
From: Christian Marangi @ 2025-03-18 23:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Russell King, Philipp Zabel, Christian Marangi,
Daniel Golle, netdev, devicetree, linux-kernel, upstream
On using OF PCS implementation, it can happen that the PCS driver still
needs to be probed at the time the MAC driver calls .mac_select_pcs.
In such case, PCS provider will return probe defer as the PCS can't be
found in the global provider list. It's expected the MAC driver to
retry probing at a later time when the PCS driver is actually probed.
To handle this, check the return value of phylink_validate (that will
call mac_select_pcs to validate the interface) in phylink_create and
make phylink_create return -EPROBE_DEFER. The MAC driver will check this
return value and retry probing.
PCS can be removed unexpectedly at later time (driver gets removed) and
not available anymore. In such case, PCS provider will also return probe
defer as the PCS can't be found in the global provider list. (as the PCS
driver on removal will delete itself as PCS provider)
To communicate correct error message, in phylink_major_config() detect
this condition and treat -EPROBE_DEFER error from .mac_select_pcs as
-ENOENT as probe defer is only allowed at probe stage.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/phy/phylink.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 7f71547e89fe..c6d9e4efed13 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -1395,6 +1395,15 @@ static void phylink_major_config(struct phylink *pl, bool restart,
if (pl->mac_ops->mac_select_pcs) {
pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
if (IS_ERR(pcs)) {
+ /* PCS can be removed unexpectedly and not available
+ * anymore.
+ * PCS provider will return probe defer as the PCS
+ * can't be found in the global provider list.
+ * In such case, return -ENOENT as a more symbolic name
+ * for the error message.
+ */
+ if (PTR_ERR(pcs) == -EPROBE_DEFER)
+ pcs = ERR_PTR(-ENOENT);
phylink_err(pl,
"mac_select_pcs unexpectedly failed: %pe\n",
pcs);
@@ -2004,7 +2013,18 @@ struct phylink *phylink_create(struct phylink_config *config,
linkmode_fill(pl->supported);
linkmode_copy(pl->link_config.advertising, pl->supported);
- phylink_validate(pl, pl->supported, &pl->link_config);
+ ret = phylink_validate(pl, pl->supported, &pl->link_config);
+ /* The PCS might not available at the time phylink_create
+ * is called. Check this and communicate to the MAC driver
+ * that probe should be retried later.
+ *
+ * Notice that this can only happen in probe stage and PCS
+ * is expected to be avaialble in phylink_major_config.
+ */
+ if (ret == -EPROBE_DEFER) {
+ kfree(pl);
+ return ERR_PTR(ret);
+ }
ret = phylink_parse_mode(pl, fwnode);
if (ret < 0) {
--
2.48.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [net-next PATCH 4/6] dt-bindings: net: ethernet-controller: permit to define multiple PCS
2025-03-18 23:58 [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF Christian Marangi
` (2 preceding siblings ...)
2025-03-18 23:58 ` [net-next PATCH 3/6] net: phylink: Correctly handle PCS probe defer from PCS provider Christian Marangi
@ 2025-03-18 23:58 ` Christian Marangi
2025-03-21 16:18 ` Rob Herring
2025-03-18 23:58 ` [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC Christian Marangi
` (3 subsequent siblings)
7 siblings, 1 reply; 34+ messages in thread
From: Christian Marangi @ 2025-03-18 23:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Russell King, Philipp Zabel, Christian Marangi,
Daniel Golle, netdev, devicetree, linux-kernel, upstream
Drop the limitation of a single PCS in pcs-handle property. Multiple PCS
can be defined for an ethrnet-controller node to support various PHY
interface mode type.
It's very common for SoCs to have a dedicated PCS for SGMII mode and one
for USXGMII mode.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
Documentation/devicetree/bindings/net/ethernet-controller.yaml | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
index 45819b235800..a260ab8e056e 100644
--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
@@ -110,8 +110,6 @@ properties:
pcs-handle:
$ref: /schemas/types.yaml#/definitions/phandle-array
- items:
- maxItems: 1
description:
Specifies a reference to a node representing a PCS PHY device on a MDIO
bus to link with an external PHY (phy-handle) if exists.
--
2.48.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC
2025-03-18 23:58 [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF Christian Marangi
` (3 preceding siblings ...)
2025-03-18 23:58 ` [net-next PATCH 4/6] dt-bindings: net: ethernet-controller: permit to define multiple PCS Christian Marangi
@ 2025-03-18 23:58 ` Christian Marangi
2025-03-19 9:13 ` Christian Marangi
` (3 more replies)
2025-03-18 23:58 ` [net-next PATCH 6/6] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS Christian Marangi
` (2 subsequent siblings)
7 siblings, 4 replies; 34+ messages in thread
From: Christian Marangi @ 2025-03-18 23:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Russell King, Philipp Zabel, Christian Marangi,
Daniel Golle, netdev, devicetree, linux-kernel, upstream
Add PCS driver for Airoha SoC for Ethernet Serdes and PCS and permit
usage of external PHY or connected SFP cage. Supported modes are
USXGMII, 10-BASER, 2500BASE-X, 1000BASE-X and SGMII.
The driver register as a PCS provider and supports poll mode to detect
PCS port state. While interrupt is supported by the HW, there are some
defect with the interrupt not fired on cable detach.
The PCS require complex calibration to correctly work and might require
multiple try until the signal detection module "lock" on the signal
level to correct work with the attached PHY.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/pcs/Kconfig | 6 +
drivers/net/pcs/Makefile | 1 +
drivers/net/pcs/pcs-airoha.c | 2858 ++++++++++++++++++++++++++++++++
include/linux/pcs/pcs-airoha.h | 11 +
4 files changed, 2876 insertions(+)
create mode 100644 drivers/net/pcs/pcs-airoha.c
create mode 100644 include/linux/pcs/pcs-airoha.h
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index 8c3b720de6fd..f0ad087286be 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -12,6 +12,12 @@ config OF_PCS
help
OpenFirmware PCS accessors
+config PCS_AIROHA
+ tristate "Airoha PCS driver"
+ help
+ This module provides helper to phylink for managing the Airoha
+ PCS for SoC Ethernet Serdes and PCS.
+
config PCS_XPCS
tristate "Synopsys DesignWare Ethernet XPCS"
select PHYLINK
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index 29881f0f981f..4ce759cd6ad9 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -2,6 +2,7 @@
# Makefile for Linux PCS drivers
obj-$(CONFIG_OF_PCS) += pcs.o
+obj-$(CONFIG_PCS_AIROHA) += pcs-airoha.o
pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
pcs-xpcs-nxp.o pcs-xpcs-wx.o
diff --git a/drivers/net/pcs/pcs-airoha.c b/drivers/net/pcs/pcs-airoha.c
new file mode 100644
index 000000000000..7f33d5c0799e
--- /dev/null
+++ b/drivers/net/pcs/pcs-airoha.c
@@ -0,0 +1,2858 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pcs/pcs-airoha.h>
+#include <linux/pcs/pcs-provider.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+/* SCU*/
+#define AIROHA_SCU_WAN_CONF 0x70
+#define AIROHA_SCU_WAN_SEL GENMASK(7, 0)
+#define AIROHA_SCU_WAN_SEL_SGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)
+#define AIROHA_SCU_WAN_SEL_HSGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)
+#define AIROHA_SCU_WAN_SEL_USXGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12)
+#define AIROHA_SCU_SSR3 0x94
+#define AIROHA_SCU_ETH_XSI_SEL GENMASK(14, 13)
+#define AIROHA_SCU_ETH_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1)
+#define AIROHA_SCU_ETH_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2)
+#define AIROHA_SCU_SSTR 0x9c
+#define AIROHA_SCU_PON_XSI_SEL GENMASK(10, 9)
+#define AIROHA_SCU_PON_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1)
+#define AIROHA_SCU_PON_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2)
+
+/* HSGMII_AN */
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0 0x0
+#define AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE BIT(12)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART BIT(9)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1 0x4 /* BMSR */
+#define AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3)
+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4 0x10
+#define AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5 0x14 /* LPA */
+#define AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11 0x2c
+#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13 0x34
+#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8)
+#define AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5)
+#define AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_AN_SIDEBAND_EN BIT(1)
+#define AIROHA_PCS_HSGMII_AN_SGMII_EN BIT(0)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60
+#define AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE BIT(0)
+
+/* HSGMII_PCS */
+#define AIROHA_PCS_HSGMII_PCS_CTROL_1 0x0
+#define AIROHA_PCS_TBI_10B_MODE BIT(30)
+#define AIROHA_PCS_SGMII_SEND_AN_ERR_EN BIT(24)
+#define AIROHA_PCS_REMOTE_FAULT_DIS BIT(12)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_3 0x8
+#define AIROHA_PCS_HSGMII_PCS_LINK_STSTIME GENMASK(19, 0)
+#define AIROHA_PCS_HSGMII_PCS_CTROL_6 0x14
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14)
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13)
+#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12)
+#define AIROHA_PCS_HSGMII_PCS_MAC_MODE BIT(8)
+#define AIROHA_PCS_HSGMII_PCS_TX_ENABLE BIT(4)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT BIT(1)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_EN BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20
+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11)
+#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10)
+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9)
+#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8)
+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5)
+#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT BIT(4)
+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3)
+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2)
+#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1)
+#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0)
+#define ARIOHA_PCS_HSGMII_PCS_STATE_2 0x104
+#define AIROHA_PCS_HSGMII_PCS_RX_SYNC BIT(5)
+#define AIROHA_PCS_HSGMII_PCS_AN_DONE BIT(0)
+#define AIROHA_PCS_HSGMII_PCS_INT_STATE 0x15c
+#define AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS BIT(3)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC BIT(1)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE BIT(0)
+
+/* MULTI_SGMII */
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0 0x14
+#define AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0 BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18
+#define AIROHA_PCS_LINK_MODE_P0 GENMASK(5, 4)
+#define AIROHA_PCS_LINK_MODE_P0_2_5G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3)
+#define AIROHA_PCS_LINK_MODE_P0_1G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2)
+#define AIROHA_PCS_LINK_MODE_P0_100M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1)
+#define AIROHA_PCS_LINK_MODE_P0_10M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0)
+#define AIROHA_PCS_FORCE_SPD_MODE_P0 BIT(2)
+#define AIROHA_PCS_FORCE_LINKDOWN_P0 BIT(1)
+#define AIROHA_PCS_FORCE_LINKUP_P0 BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0 0x100
+#define AIROHA_PCS_HSGMII_XFI_SEL BIT(28)
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL 0x14c
+#define AIROHA_PCS_HSGMII_PCS_INT BIT(0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15 0x43c
+#define AIROHA_PCS_LINK_STS_P0 BIT(3)
+#define AIROHA_PCS_SPEED_STS_P0 GENMASK(2, 0)
+#define AIROHA_PCS_SPEED_STS_P0_1G FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2)
+#define AIROHA_PCS_SPEED_STS_P0_100M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1)
+#define AIROHA_PCS_SPEED_STS_P0_10M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0)
+#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18 0x448
+#define AIROHA_PCS_P0_SGMII_IS_10 BIT(2)
+#define AIROHA_PCS_P0_SGMII_IS_100 BIT(1)
+#define AIROHA_PCS_P0_SGMII_IS_1000 BIT(0)
+
+/* HSGMII_RATE_ADP */
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0 0x0
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN BIT(4)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN BIT(0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1 0x4
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6 0x18
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8 0x20
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0)
+#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11 0x2c
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4)
+#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \
+ FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6)
+#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0 0x100
+#define AIROHA_PCS_HSGMII_P0_DIS_MII_MODE BIT(31)
+
+/* USXGMII */
+#define AIROHA_PCS_USXGMII_PCS_CTROL_1 0x0
+#define AIROHA_PCS_USXGMII_SPEED_SEL_H BIT(13)
+#define AIROHA_PCS_USXGMII_PCS_STUS_1 0x30
+#define AIROHA_PCS_USXGMII_RX_LINK_STUS BIT(12)
+#define AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3)
+#define AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2)
+#define AIROHA_PCS_USXGMII_PCS_BLK_LK BIT(0)
+#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116 0x22c
+#define AIROHA_PCS_USXGMII_PCS_CTRL_0 0x2c0
+#define AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_1 0x2c4
+#define AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_2 0x2c8
+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_3 0x2cc
+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24)
+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16)
+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN BIT(8)
+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_2 0x2d8
+#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24)
+#define AIROHA_PCS_USXGMII_R_TYPE_E_INT BIT(16)
+#define AIROHA_PCS_USXGMII_R_TYPE_T_INT BIT(8)
+#define AIROHA_PCS_USXGMII_R_TYPE_D_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_3 0x2dc
+#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24)
+#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16)
+#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT BIT(8)
+#define AIROHA_PCS_USXGMII_HI_BER_ST_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_CTRL_4 0x2e0
+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_INT_STA_4 0x2e4
+#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0 0x2f8
+#define AIROHA_PCS_USXGMII_AN_RESTART BIT(8)
+#define AIROHA_PCS_USXGMII_AN_ENABLE BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0 0x310
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE GENMASK(30, 28)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3)
+#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4)
+#define AIROHA_PCS_USXGMII_PARTNER_ABILITY GENMASK(15, 0)
+#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2 0x318
+#define AIROHA_PCS_USXGMII_PCS_AN_COMPLETE BIT(24)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6 0x31c
+#define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)
+#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7 0x320
+#define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE BIT(12)
+#define AIROHA_PCS_USXGMII_MODE GENMASK(10, 8)
+#define AIROHA_PCS_USXGMII_MODE_10000 FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x0)
+#define AIROHA_PCS_USXGMII_MODE_5000 FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x1)
+#define AIROHA_PCS_USXGMII_MODE_2500 FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x2)
+#define AIROHA_PCS_USXGMII_MODE_1000 FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x3)
+#define AIROHA_PCS_USXGMII_MODE_100 FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x4)
+
+/* PMA_PHYA */
+#define AIROHA_PCS_ANA_PXP_CMN_EN 0x0
+#define AIROHA_PCS_ANA_CMN_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN 0x4
+#define AIROHA_PCS_ANA_JCPLL_CHP_IOFST GENMASK(29, 24)
+#define AIROHA_PCS_ANA_JCPLL_CHP_IBIAS GENMASK(21, 16)
+#define AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN BIT(8)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR 0x8
+#define AIROHA_PCS_ANA_JCPLL_LPF_BWR GENMASK(28, 24)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BP GENMASK(20, 16)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BC GENMASK(12, 8)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BR GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC 0xc
+#define AIROHA_PCS_ANA_JCPLL_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_CODE GENMASK(23, 16)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_OPTION BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_LPF_BWC GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC 0x10
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KS GENMASK(17, 16)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KF GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_KBAND_KFC GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14
+#define AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 BIT(24)
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x0)
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x1)
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x2)
+#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x3)
+#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY 0x1c
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS GENMASK(25, 24)
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x0)
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x1)
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x2)
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x3)
+#define AIROHA_PCS_ANA_JCPLL_SDM_DI_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_PLL_RSTB BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY GENMASK(2, 0)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x1)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x2)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x3)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x4)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x5)
+#define AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x6)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM 0x20
+#define AIROHA_PCS_ANA_JCPLL_SDM_OUT BIT(24)
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD GENMASK(17, 16)
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0)
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x1)
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x2)
+#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x3)
+#define AIROHA_PCS_ANA_JCPLL_SDM_MODE GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_SDM_IFM BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN 0x24
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF GENMASK(28, 24)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN GENMASK(18, 16)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x0)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x1)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x2)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x3)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x4)
+#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN BIT(8)
+#define AIROHA_PCS_ANA_JCPLL_SDM_HREN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN 0x28
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x0)
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x1)
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x2)
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x3)
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x4)
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x6)
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24)
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV 0x2c
+#define AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR GENMASK(26, 24)
+#define AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_VCO_CFIX GENMASK(9, 8)
+#define AIROHA_PCS_ANA_JCPLL_VCODIV GENMASK(1, 0)
+#define AIROHA_PCS_ANA_JCPLL_VCODIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x0)
+#define AIROHA_PCS_ANA_JCPLL_VCODIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x1)
+#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR 0x30
+#define AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI BIT(17)
+#define AIROHA_PCS_ANA_JCPLL_SSC_EN BIT(16)
+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8)
+#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3)
+#define AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN 0x34
+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 GENMASK(23, 8)
+#define AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA 0x38
+#define AIROHA_PCS_ANA_JCPLL_SSC_PERIOD GENMASK(31, 16)
+#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H 0x48
+#define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF GENMASK(20, 16)
+#define AIROHA_PCS_ANA_JCPLL_SPARE_L GENMASK(15, 8)
+#define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5))
+#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS 0x50
+#define AIROHA_PCS_ANA_TXPLL_LPF_BC GENMASK(28, 24)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BR GENMASK(20, 16)
+#define AIROHA_PCS_ANA_TXPLL_CHP_IOFST GENMASK(13, 8)
+#define AIROHA_PCS_ANA_TXPLL_CHP_IBIAS GENMASK(5, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP 0x54
+#define AIROHA_PCS_ANA_TXPLL_KBAND_OPTION BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BWC GENMASK(20, 16)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BWR GENMASK(12, 8)
+#define AIROHA_PCS_ANA_TXPLL_LPF_BP GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE 0x58
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KF GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KFC GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_DIV GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_CODE GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS 0x5c
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x0)
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x1)
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x2)
+#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x3)
+#define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_KBAND_KS GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL 0x64
+#define AIROHA_PCS_ANA_TXPLL_PLL_RSTB BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_RST_DLY GENMASK(18, 16)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV GENMASK(9, 8)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x0)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x1)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x2)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x3)
+#define AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN 0x68
+#define AIROHA_PCS_ANA_TXPLL_SDM_MODE GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_SDM_IFM BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS GENMASK(9, 8)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x0)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x1)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x2)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x3)
+#define AIROHA_PCS_ANA_TXPLL_SDM_DI_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD 0x6c
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN BIT(24)
+#define AIROHA_PCS_ANA_TXPLL_SDM_HREN BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SDM_OUT BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD GENMASK(1, 0)
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x0)
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x1)
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x2)
+#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x3)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN 0x70
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF GENMASK(12, 8)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN GENMASK(2, 0)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x0)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x1)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x2)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x3)
+#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x4)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN 0x74
+#define AIROHA_PCS_ANA_TXPLL_VCO_CFIX GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_VCODIV GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_VCODIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x0)
+#define AIROHA_PCS_ANA_TXPLL_VCODIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1)
+#define AIROHA_PCS_ANA_TXPLL_VCODIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1)
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x0)
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x1)
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x2)
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x3)
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x4)
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x6)
+#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN 0x78
+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27)
+#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24)
+#define AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR GENMASK(18, 16)
+#define AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR GENMASK(10, 8)
+#define AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN 0x7c
+#define AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN BIT(16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI BIT(8)
+#define AIROHA_PCS_ANA_TXPLL_SSC_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1 0x80
+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA GENMASK(31, 16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA1 GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD 0x84
+#define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT GENMASK(25, 24)
+#define AIROHA_PCS_ANA_TXPLL_LDO_OUT GENMASK(17, 16)
+#define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD GENMASK(15, 0)
+#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF 0x94
+#define AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)
+#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN 0xc4
+#define AIROHA_PCS_ANA_TX_DMEDGEGEN_EN BIT(24)
+#define AIROHA_PCS_ANA_TX_CKLDO_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL 0xcc
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE BIT(24)
+#define AIROHA_PCS_ANA_RX_PHY_CK_SEL BIT(16) /* 0: from PR 1: from DES */
+#define AIROHA_PCS_ANA_PXP_RX_REV_0 0xd4
+#define AIROHA_PCS_ANA_RX_REV_1 GENMASK(31, 16)
+#define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
+#define AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
+#define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
+#define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK GENMASK(19, 18)
+#define AIROHA_PCS_ANA_REV_1_FECUR_PWDB BIT(16)
+#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV 0xd8
+#define AIROHA_PCS_ANA_RX_TDC_CK_SEL BIT(24)
+#define AIROHA_PCS_ANA_RX_PHYCK_RSTB BIT(16)
+#define AIROHA_PCS_ANA_RX_PHYCK_SEL GENMASK(9, 8)
+#define AIROHA_PCS_ANA_RX_PHYCK_DIV GENMASK(7, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc
+#define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS BIT(8)
+#define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV BIT(0)
+#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO 0xe8
+#define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM GENMASK(26, 8)
+#define AIROHA_PCS_ANA_CDR_LPF_RATIO GENMASK(1, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE 0xf4
+#define AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF BIT(24)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC 0xf8
+#define AIROHA_PCS_ANA_CDR_PR_KBAND_DIV GENMASK(26, 24)
+#define AIROHA_PCS_ANA_CDR_PR_BETA_SEL GENMASK(19, 16)
+#define AIROHA_PCS_ANA_CDR_PR_VCOADC_OS GENMASK(11, 8)
+#define AIROHA_PCS_ANA_CDR_PR_BETA_DAC GENMASK(6, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc
+#define AIROHA_PCS_ANA_CDR_PR_FBKSEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND GENMASK(20, 16)
+#define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL GENMASK(10, 8)
+#define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL GENMASK(2, 0)
+#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN 0x10c
+#define AIROHA_PCS_ANA_RX_DAC_MON GENMASK(28, 24)
+#define AIROHA_PCS_ANA_CDR_PR_CAP_EN BIT(19)
+#define AIROHA_PCS_ANA_CDR_BUF_IN_SR GENMASK(18, 16)
+#define AIROHA_PCS_ANA_CDR_PR_XFICK_EN BIT(2)
+#define AIROHA_PCS_ANA_CDR_PR_MONDPI_EN BIT(1)
+#define AIROHA_PCS_ANA_CDR_PR_MONDPR_EN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE 0x110
+#define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH 0x114
+#define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL GENMASK(25, 24)
+#define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL GENMASK(20, 16)
+#define AIROHA_PCS_ANA_RX_SIGDET_PEAK GENMASK(9, 8)
+#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN 0x118
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN BIT(24)
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN BIT(16)
+#define AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN BIT(8)
+#define AIROHA_PCS_ANA_RX_FE_EQ_HZEN BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB 0x11c
+#define AIROHA_PCS_ANA_FE_VCM_GEN_PWDB BIT(0)
+#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW 0x120
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE GENMASK(17, 8)
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(0))
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(1))
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(2))
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(3))
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(4))
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(5))
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(6))
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(7))
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(8))
+#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(9))
+#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE 0x13c
+#define AIROHA_PCS_ANA_AEQ_OFORCE GENMASK(19, 8)
+#define AIROHA_PCS_ANA_AEQ_OFORCE_SAOS FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(0))
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(1))
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(2))
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(3))
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(4))
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(5))
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(6))
+#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(7))
+#define AIROHA_PCS_ANA_AEQ_OFORCE_VGA FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(8))
+#define AIROHA_PCS_ANA_AEQ_OFORCE_CTLE FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(9))
+#define AIROHA_PCS_ANA_AEQ_OFORCE_ATT FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(10))
+#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144
+#define AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ 0x148
+#define AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ BIT(24)
+#define AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ BIT(16)
+#define AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ BIT(8)
+#define AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ BIT(0)
+
+/* PMA_PHYD */
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0 0x0
+#define AIROHA_PCS_PMA_SW_LCPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1 0x4
+#define AIROHA_PCS_PMA_LCPLL_MAN_PWDB BIT(0)
+#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2 0x88
+#define AIROHA_PCS_PMA_DATA_SHIFT BIT(8)
+#define AIROHA_PCS_PMA_EYECNT_FAST BIT(0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0 0x8c
+#define AIROHA_PCS_PMA_RX_OS_START GENMASK(23, 8)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT GENMASK(2, 0)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6)
+#define AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1 0x90
+#define AIROHA_PCS_PMA_RX_PICAL_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_PICAL_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2 0x94
+#define AIROHA_PCS_PMA_RX_PDOS_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_PDOS_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3 0x98
+#define AIROHA_PCS_PMA_RX_FEOS_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_FEOS_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4 0x9c
+#define AIROHA_PCS_PMA_RX_SDCAL_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_SDCAL_START GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5 0x100
+#define AIROHA_PCS_PMA_RX_RDY GENMASK(31, 16)
+#define AIROHA_PCS_PMA_RX_BLWC_RDY_EN GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6 0x104
+#define AIROHA_PCS_PMA_RX_OS_END GENMASK(15, 0)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c
+#define AIROHA_PCS_PMA_DISB_RX_RDY BIT(24)
+#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114
+#define AIROHA_PCS_PMA_FORCE_RX_RDY BIT(24)
+#define AIROHA_PCS_PMA_PHY_EQ_CTRL_3 0x120
+#define AIROHA_PCS_PMA_EQ_DEBUG_SEL GENMASK(17, 16)
+#define AIROHA_PCS_PMA_FOM_NUM_ORDER GENMASK(12, 8)
+#define AIROHA_PCS_PMA_A_SEL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1 0x14c
+#define AIROHA_PCS_PMA_UNLOCK_CYCLECNT GENMASK(31, 16)
+#define AIROHA_PCS_PMA_LOCK_CYCLECNT GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2 0x150
+#define AIROHA_PCS_PMA_LOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_LOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3 0x154
+#define AIROHA_PCS_PMA_UNLOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_UNLOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4 0x158
+#define AIROHA_PCS_PMA_LOCK_UNLOCKTH GENMASK(15, 12)
+#define AIROHA_PCS_PMA_LOCK_LOCKTH GENMASK(11, 8)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN GENMASK(2, 0)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)
+#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)
+#define AIROHA_PCS_PMA_SS_RX_SIGDET_1 0x16c
+#define AIROHA_PCS_PMA_SIGDET_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_FLL_1 0x174
+#define AIROHA_PCS_PMA_LPATH_IDAC GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_2 0x178
+#define AIROHA_PCS_PMA_CK_RATE GENMASK(18, 16)
+#define AIROHA_PCS_PMA_CK_RATE_20 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0)
+#define AIROHA_PCS_PMA_CK_RATE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1)
+#define AIROHA_PCS_PMA_CK_RATE_5 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2)
+#define AIROHA_PCS_PMA_RX_FLL_5 0x184
+#define AIROHA_PCS_PMA_FLL_IDAC_MIN GENMASK(26, 16)
+#define AIROHA_PCS_PMA_FLL_IDAC_MAX GENMASK(10, 0)
+#define AIROHA_PCS_PMA_RX_FLL_B 0x19c
+#define AIROHA_PCS_PMA_LOAD_EN BIT(0)
+#define AIROHA_PCS_PMA_RX_RESET_1 0x208
+#define AIROHA_PCS_PMA_SIGDET_RST_B BIT(8)
+#define AIROHA_PCS_PMA_TX_RST_B 0x260
+#define AIROHA_PCS_PMA_TXCALIB_RST_B BIT(8)
+#define AIROHA_PCS_PMA_TX_TOP_RST_B BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_4 0x320
+#define AIROHA_PCS_PMA_DISB_BLWC_OFFSET BIT(24)
+#define AIROHA_PCS_PMA_RX_FORCE_MODE_9 0x330
+#define AIROHA_PCS_PMA_FORCE_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_RX_DISB_MODE_8 0x33c
+#define AIROHA_PCS_PMA_DISB_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0 0x38c
+#define AIROHA_PCS_PMA_RX_SYS_EN_SEL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0 0x390
+#define AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1 0x394
+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_END GENMASK(31, 16)
+#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG GENMASK(15, 0)
+#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3 0x39c
+#define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH GENMASK(11, 8)
+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL 0x48c
+#define AIROHA_PCS_PMA_DISB_LEQ BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0 0x34c
+#define AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB BIT(24)
+#define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB BIT(16)
+#define AIROHA_PCS_PMA_XPON_CDR_PW_PWDB BIT(8)
+#define AIROHA_PCS_PMA_XPON_RX_FE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1 0x350
+#define AIROHA_PCS_PMA_RX_SIDGET_PWDB BIT(0)
+#define AIROHA_PCS_PMA_DIG_RESERVE_0 0x360
+#define AIROHA_PCS_PMA_DIG_RO_RESERVE_2 0x380
+#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1 0x374
+#define AIROHA_PCS_PMA_XPON_RX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_SW_RST_SET 0x460
+#define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N BIT(11)
+#define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N BIT(10)
+#define AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N BIT(9)
+#define AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N BIT(8)
+#define AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N BIT(7)
+#define AIROHA_PCS_PMA_SW_TX_FIFO_RST_N BIT(6)
+#define AIROHA_PCS_PMA_SW_REF_RST_N BIT(5)
+#define AIROHA_PCS_PMA_SW_ALLPCS_RST_N BIT(4)
+#define AIROHA_PCS_PMA_SW_PMA_RST_N BIT(3)
+#define AIROHA_PCS_PMA_SW_TX_RST_N BIT(2)
+#define AIROHA_PCS_PMA_SW_RX_RST_N BIT(1)
+#define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N BIT(0)
+#define AIROHA_PCS_PMA_XPON_INT_EN_3 0x474
+#define AIROHA_PCS_PMA_RX_SIGDET_INT_EN BIT(16)
+#define AIROHA_PCS_PMA_XPON_INT_STA_3 0x47c
+#define AIROHA_PCS_PMA_RX_SIGDET_INT BIT(16)
+#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL 0x48c
+#define AIROHA_PCS_PMA_DISB_LEQ BIT(0)
+#define AIROHA_PCS_PMA_RX_FREQDET 0x530
+#define AIROHA_PCS_PMA_FL_OUT GENMASK(31, 16)
+#define AIROHA_PCS_PMA_FBCK_LOCK BIT(0)
+#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL 0x580
+#define AIROHA_PCS_PMA_PON_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN 0x768
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PEAKING_CTRL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL GENMASK(19, 16)
+#define AIROHA_PCS_PMA_PXP_AEQ_SPEED 0x76c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_OSR_SEL GENMASK(17, 16)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B 0x778
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 GENMASK(20, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL 0x77c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL GENMASK(2, 0)
+#define AIROHA_PCS_PMA_PXP_TX_FIR_C1 0x780
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 GENMASK(20, 16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1 GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL 0x784
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC 0x794
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)
+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC GENMASK(10, 0)
+#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8)
+#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW 0x798
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_VOS 0x79c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_FE_VOS GENMASK(5, 0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW 0x800
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW GENMASK(30, 0)
+#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS 0x80c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON BIT(16)
+#define AIROHA_PCS_PMA_PXP_AEQ_RSTB 0x814
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL BIT(16)
+#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA 0x818
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB 0x81c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN 0x820
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB 0x824
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0)
+#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN 0x828
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B 0x84c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B BIT(0)
+#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN 0x854
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)
+#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN 0x874
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL BIT(16)
+#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL 0x88c
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0)
+#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB 0x894
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN BIT(16)
+#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)
+#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB BIT(0)
+
+#define AIROHA_PCS_MAX_CALIBRATION_TRY 50
+#define AIROHA_PCS_MAX_NUM_RSTS 2
+
+enum xfi_port_type {
+ AIROHA_PCS_ETH,
+ AIROHA_PCS_PON,
+};
+
+struct airoha_pcs_match_data {
+ enum xfi_port_type port_type;
+};
+
+struct airoha_pcs_priv {
+ struct device *dev;
+ const struct airoha_pcs_match_data *data;
+ phy_interface_t interface;
+
+ struct regmap *scu;
+
+ struct regmap *xfi_mac;
+ struct regmap *hsgmii_an;
+ struct regmap *hsgmii_pcs;
+ struct regmap *hsgmii_rate_adp;
+ struct regmap *multi_sgmii;
+ struct regmap *usxgmii_pcs;
+
+ struct regmap *xfi_pma;
+ struct regmap *xfi_ana;
+
+ struct reset_control_bulk_data rsts[AIROHA_PCS_MAX_NUM_RSTS];
+
+ struct phylink_pcs pcs;
+};
+
+static struct airoha_pcs_priv *phylink_pcs_to_airoha_pcs_port(struct phylink_pcs *pcs)
+{
+ return container_of(pcs, struct airoha_pcs_priv, pcs);
+}
+
+static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 xsi_sel;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ xsi_sel = AIROHA_SCU_ETH_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ xsi_sel = AIROHA_SCU_ETH_XSI_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSR3,
+ AIROHA_SCU_ETH_XSI_SEL,
+ xsi_sel);
+}
+
+static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 xsi_sel, wan_sel;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ wan_sel = AIROHA_SCU_WAN_SEL_SGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ wan_sel = AIROHA_SCU_WAN_SEL_HSGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ default:
+ wan_sel = AIROHA_SCU_WAN_SEL_USXGMII;
+ xsi_sel = AIROHA_SCU_PON_XSI_USXGMII;
+ }
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
+ AIROHA_SCU_PON_XSI_SEL,
+ xsi_sel);
+
+ regmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF,
+ AIROHA_SCU_WAN_SEL,
+ wan_sel);
+}
+
+static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ int ret;
+
+ switch (priv->data->port_type) {
+ case AIROHA_PCS_ETH:
+ airoha_pcs_setup_scu_eth(priv, interface);
+ break;
+ case AIROHA_PCS_PON:
+ airoha_pcs_setup_scu_pon(priv, interface);
+ break;
+ }
+
+ ret = reset_control_bulk_assert(ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return ret;
+
+ ret = reset_control_bulk_deassert(ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv)
+{
+ regmap_set_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ /* Disable Hibernation */
+ regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,
+ AIROHA_PCS_USXGMII_SPEED_SEL_H);
+
+ /* FIXME: wait Airoha */
+ /* Avoid PCS sending garbage to MAC in some HW revision (E0) */
+ regmap_write(priv->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);
+}
+
+static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv)
+{
+ regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_TBI_10B_MODE);
+}
+
+static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv)
+{
+ regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_TBI_10B_MODE);
+
+ regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707));
+
+ regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff));
+}
+
+static void airoha_pcs_init(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ airoha_pcs_init_sgmii(priv);
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ airoha_pcs_init_hsgmii(priv);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ airoha_pcs_init_usxgmii(priv);
+ break;
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv)
+{
+ /* Disable every interrupt */
+ regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT);
+
+ /* Clear interrupt */
+ regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+
+ regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+}
+
+static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv)
+{
+ /* Disable every Interrupt */
+ regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0,
+ AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN);
+
+ regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1,
+ AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN |
+ AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN |
+ AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN);
+
+ regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2,
+ AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN |
+ AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN);
+
+ regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3,
+ AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN |
+ AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN |
+ AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN |
+ AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN);
+
+ regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4,
+ AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN);
+
+ /* Clear any pending interrupt */
+ regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2,
+ AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_E_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_T_INT |
+ AIROHA_PCS_USXGMII_R_TYPE_D_INT);
+
+ regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3,
+ AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT |
+ AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT |
+ AIROHA_PCS_USXGMII_LINK_UP_ST_INT |
+ AIROHA_PCS_USXGMII_HI_BER_ST_INT);
+
+ regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4,
+ AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT);
+
+ /* Interrupt saddly seems to be not weel supported for Link Down.
+ * PCS Poll is a must to correctly read and react on Cable Deatch
+ * as only cable attach interrupt are fired and Link Down interrupt
+ * are fired only in special case like AN restart.
+ */
+}
+
+static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ return airoha_pcs_interrupt_init_sgmii(priv);
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ return airoha_pcs_interrupt_init_usxgmii(priv);
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_jcpll_bringup(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 kband_vref;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ kband_vref = 0x10;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ kband_vref = 0xf;
+ break;
+ default:
+ return;
+ }
+
+ /* Setup LDO */
+ usleep_range(200, 300);
+
+ regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H,
+ AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO);
+
+ /* Setup RSTB */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
+ AIROHA_PCS_ANA_JCPLL_RST_DLY,
+ AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200);
+
+ regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
+ AIROHA_PCS_ANA_JCPLL_PLL_RSTB);
+
+ /* Enable PLL force selection and Force Disable */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN);
+
+ /* Setup SDM */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
+ AIROHA_PCS_ANA_JCPLL_SDM_DI_LS |
+ AIROHA_PCS_ANA_JCPLL_SDM_DI_EN,
+ AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23);
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM,
+ AIROHA_PCS_ANA_JCPLL_SDM_OUT |
+ AIROHA_PCS_ANA_JCPLL_SDM_ORD |
+ AIROHA_PCS_ANA_JCPLL_SDM_MODE |
+ AIROHA_PCS_ANA_JCPLL_SDM_IFM,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0) |
+ AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM |
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_MODE, 0x0));
+
+ regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN,
+ AIROHA_PCS_ANA_JCPLL_SDM_HREN);
+
+ /* Setup SSC */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA,
+ AIROHA_PCS_ANA_JCPLL_SSC_PERIOD |
+ AIROHA_PCS_ANA_JCPLL_SSC_DELTA,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_PERIOD, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA, 0x0));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN,
+ AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 |
+ AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA1, 0x0));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR,
+ AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI |
+ AIROHA_PCS_ANA_JCPLL_SSC_EN |
+ AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L |
+ AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x0));
+
+ /* Setup LPF */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN,
+ AIROHA_PCS_ANA_JCPLL_CHP_IOFST |
+ AIROHA_PCS_ANA_JCPLL_CHP_IBIAS |
+ AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IOFST, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IBIAS, 0x18));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR,
+ AIROHA_PCS_ANA_JCPLL_LPF_BWR |
+ AIROHA_PCS_ANA_JCPLL_LPF_BP |
+ AIROHA_PCS_ANA_JCPLL_LPF_BC |
+ AIROHA_PCS_ANA_JCPLL_LPF_BR,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWR, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BP, 0x10) |
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BC, 0x1f) |
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BR, BIT(3) | BIT(1)));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC,
+ AIROHA_PCS_ANA_JCPLL_LPF_BWC,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWC, 0x0));
+
+ /* Setup VCO */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV,
+ AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR |
+ AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN |
+ AIROHA_PCS_ANA_JCPLL_VCO_CFIX,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR, 0x4) |
+ AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN |
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_CFIX, 0x1));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR,
+ AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L |
+ AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H |
+ AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H, 0x3) |
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x3));
+
+ /* Setup PCW */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW,
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000));
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW);
+
+ /* Setup DIV */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE,
+ AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 |
+ AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE,
+ AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2);
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV,
+ AIROHA_PCS_ANA_JCPLL_VCODIV,
+ AIROHA_PCS_ANA_JCPLL_VCODIV_1);
+
+ /* Setup KBand */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC,
+ AIROHA_PCS_ANA_JCPLL_KBAND_KS |
+ AIROHA_PCS_ANA_JCPLL_KBAND_KF |
+ AIROHA_PCS_ANA_JCPLL_KBAND_KFC,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KS, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KF, 0x3) |
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KFC, 0x0));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC,
+ AIROHA_PCS_ANA_JCPLL_KBAND_DIV |
+ AIROHA_PCS_ANA_JCPLL_KBAND_CODE |
+ AIROHA_PCS_ANA_JCPLL_KBAND_OPTION,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_DIV, 0x2) |
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_CODE, 0xe4));
+
+ /* Setup TCL */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H,
+ AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF, kband_vref));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN,
+ AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF |
+ AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN |
+ AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN,
+ FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF, 0x5) |
+ AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 |
+ AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN);
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN,
+ AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW |
+ AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN,
+ AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 |
+ AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN);
+
+ /* Enable PLL */
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN);
+
+ /* Enale PLL Output */
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN |
+ AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN);
+}
+
+static void airoha_pcs_txpll_bringup(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc;
+ u32 vco_cfix;
+ u32 pcw;
+ u32 tcl_amp_vref;
+ bool sdm_hren;
+ bool vcodiv;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ lpf_chp_ibias = 0xf;
+ lpf_bp = BIT(1);
+ lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+ lpf_bwc = BIT(4) | BIT(3);
+ vco_cfix = BIT(1) | BIT(0);
+ pcw = BIT(27);
+ tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+ vcodiv = false;
+ sdm_hren = false;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ lpf_chp_ibias = 0xa;
+ lpf_bp = BIT(2) | BIT(0);
+ lpf_bwr = 0;
+ lpf_bwc = 0;
+ vco_cfix = 0;
+ pcw = BIT(27) | BIT(25);
+ tcl_amp_vref = BIT(3) | BIT(2) | BIT(0);
+ vcodiv = true;
+ sdm_hren = false;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ lpf_chp_ibias = 0xf;
+ lpf_bp = BIT(1);
+ lpf_bwr = BIT(3) | BIT(1) | BIT(0);
+ lpf_bwc = BIT(4) | BIT(3);
+ vco_cfix = BIT(0);
+ pcw = BIT(27) | BIT(22);
+ tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
+ vcodiv = false;
+ sdm_hren = true;
+ break;
+ default:
+ return;
+ }
+
+ /* Setup VCO LDO Output */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,
+ AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT |
+ AIROHA_PCS_ANA_TXPLL_LDO_OUT,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT, 0x1) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_OUT, 0x1));
+
+ /* Setup RSTB */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL,
+ AIROHA_PCS_ANA_TXPLL_PLL_RSTB |
+ AIROHA_PCS_ANA_TXPLL_RST_DLY |
+ AIROHA_PCS_ANA_TXPLL_REFIN_DIV |
+ AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL,
+ AIROHA_PCS_ANA_TXPLL_PLL_RSTB |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_RST_DLY, 0x4) |
+ AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 |
+ AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL);
+
+ /* Enable PLL force selection and Force Disable */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN);
+
+ /* Setup SDM */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN,
+ AIROHA_PCS_ANA_TXPLL_SDM_MODE |
+ AIROHA_PCS_ANA_TXPLL_SDM_IFM |
+ AIROHA_PCS_ANA_TXPLL_SDM_DI_LS |
+ AIROHA_PCS_ANA_TXPLL_SDM_DI_EN,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SDM_MODE, 0) |
+ AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23);
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,
+ AIROHA_PCS_ANA_TXPLL_SDM_HREN |
+ AIROHA_PCS_ANA_TXPLL_SDM_OUT |
+ AIROHA_PCS_ANA_TXPLL_SDM_ORD,
+ (sdm_hren ? AIROHA_PCS_ANA_TXPLL_SDM_HREN : 0) |
+ AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM);
+
+ /* Setup SSC */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1,
+ AIROHA_PCS_ANA_TXPLL_SSC_DELTA |
+ AIROHA_PCS_ANA_TXPLL_SSC_DELTA1,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA1, 0x0));
+
+ regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN,
+ AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN |
+ AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI |
+ AIROHA_PCS_ANA_TXPLL_SSC_EN);
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,
+ AIROHA_PCS_ANA_TXPLL_SSC_PERIOD,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_PERIOD, 0x0));
+
+ /* Setup LPF */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS,
+ AIROHA_PCS_ANA_TXPLL_LPF_BC |
+ AIROHA_PCS_ANA_TXPLL_LPF_BR |
+ AIROHA_PCS_ANA_TXPLL_CHP_IOFST |
+ AIROHA_PCS_ANA_TXPLL_CHP_IBIAS,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BC, 0x1f) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BR, 0x5) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IOFST, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IBIAS, lpf_chp_ibias));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,
+ AIROHA_PCS_ANA_TXPLL_LPF_BWC |
+ AIROHA_PCS_ANA_TXPLL_LPF_BWR |
+ AIROHA_PCS_ANA_TXPLL_LPF_BP,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWC, lpf_bwc) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWR, lpf_bwr) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BP, lpf_bp));
+
+ /* Setup VCO */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+ AIROHA_PCS_ANA_TXPLL_VCO_CFIX,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_CFIX, vco_cfix));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN,
+ AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L |
+ AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H |
+ AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR |
+ AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR |
+ AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H, 0x4) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR, 0x4) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR, 0x7) |
+ AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN);
+
+ /* Setup PCW */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW,
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);
+
+ /* Setup KBand */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE,
+ AIROHA_PCS_ANA_TXPLL_KBAND_KF |
+ AIROHA_PCS_ANA_TXPLL_KBAND_KFC |
+ AIROHA_PCS_ANA_TXPLL_KBAND_DIV |
+ AIROHA_PCS_ANA_TXPLL_KBAND_CODE,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KF, 0x3) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KFC, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_DIV, 0x4) |
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_CODE, 0xe4));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,
+ AIROHA_PCS_ANA_TXPLL_KBAND_KS,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KS, 0x1));
+
+ regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,
+ AIROHA_PCS_ANA_TXPLL_KBAND_OPTION);
+
+ /* Setup DIV */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,
+ AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE |
+ AIROHA_PCS_ANA_TXPLL_POSTDIV_EN,
+ AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2);
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+ AIROHA_PCS_ANA_TXPLL_VCODIV,
+ vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 :
+ AIROHA_PCS_ANA_TXPLL_VCODIV_1);
+
+ /* Setup TCL */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF,
+ AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF, 0xf));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN,
+ AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF |
+ AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN,
+ FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF, tcl_amp_vref) |
+ AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4);
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
+ AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW |
+ AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN,
+ AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 |
+ AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN);
+
+ regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,
+ AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN);
+
+ /* Enable PLL */
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN);
+
+ /* Enale PLL Output */
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN |
+ AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN);
+}
+
+static void airoha_pcs_pll_bringup(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ airoha_pcs_jcpll_bringup(priv, interface);
+
+ usleep_range(200, 300);
+
+ airoha_pcs_txpll_bringup(priv, interface);
+
+ usleep_range(200, 300);
+}
+
+static void airoha_pcs_tx_bringup(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 tx_rate_ctrl;
+ u32 ckin_divisor;
+ u32 fir_cn1, fir_c0b, fir_c1;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ ckin_divisor = BIT(1);
+ tx_rate_ctrl = BIT(0);
+ fir_cn1 = 0;
+ fir_c0b = 12;
+ fir_c1 = 0;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ ckin_divisor = BIT(2);
+ tx_rate_ctrl = BIT(0);
+ fir_cn1 = 0;
+ fir_c0b = 11;
+ fir_c1 = 1;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ ckin_divisor = BIT(2) | BIT(0);
+ tx_rate_ctrl = BIT(1);
+ fir_cn1 = 1;
+ fir_c0b = 1;
+ fir_c1 = 11;
+ break;
+ default:
+ return;
+ }
+
+ /* Set TX rate ctrl */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
+ tx_rate_ctrl));
+
+ /* Setup TX Config */
+ regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TX_CKLDO_EN,
+ AIROHA_PCS_ANA_TX_DMEDGEGEN_EN |
+ AIROHA_PCS_ANA_TX_CKLDO_EN);
+
+ udelay(1);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL);
+
+ /* FIXME: Ask Airoha TX term is OK to reset? */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+ AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,
+ ckin_divisor) |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL, 0x0));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
+ tx_rate_ctrl));
+
+ /* Setup TX FIR Load Parameters (Reference 660mV) */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+ AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1));
+
+ /* Reset TX Bar */
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_TX_RST_B,
+ AIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B);
+}
+
+static void airoha_pcs_rx_bringup(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ u32 rx_rate_ctrl;
+ u32 osr;
+ u32 pr_cdr_beta_dac;
+ u32 cdr_pr_buf_in_sr;
+ bool cdr_pr_cap_en;
+ u32 sigdet_vth_sel;
+ u32 phyck_div, phyck_sel;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ osr = BIT(1) | BIT(0); /* 1.25G */
+ pr_cdr_beta_dac = BIT(3);
+ rx_rate_ctrl = 0;
+ cdr_pr_cap_en = false;
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+ sigdet_vth_sel = BIT(2) | BIT(1);
+ phyck_div = BIT(5) | BIT(3) | BIT(0);
+ phyck_sel = BIT(0);
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ osr = BIT(0); /* 2.5G */
+ pr_cdr_beta_dac = BIT(2) | BIT(1);
+ rx_rate_ctrl = 0;
+ cdr_pr_cap_en = true;
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1);
+ sigdet_vth_sel = BIT(2) | BIT(1);
+ phyck_div = BIT(3) | BIT(1) | BIT(0);
+ phyck_sel = BIT(0);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ osr = 0; /* 10G */
+ cdr_pr_cap_en = false;
+ pr_cdr_beta_dac = BIT(3);
+ rx_rate_ctrl = BIT(1);
+ cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
+ sigdet_vth_sel = BIT(1);
+ phyck_div = BIT(6) | BIT(1);
+ phyck_sel = BIT(1);
+ break;
+ default:
+ return;
+ }
+
+ /* Set RX rate ctrl */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_2,
+ AIROHA_PCS_PMA_CK_RATE,
+ AIROHA_PCS_PMA_CK_RATE_10);
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1,
+ AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL, rx_rate_ctrl));
+
+ /* Setup RX Path */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_5,
+ AIROHA_PCS_PMA_FLL_IDAC_MIN |
+ AIROHA_PCS_PMA_FLL_IDAC_MAX,
+ FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) |
+ FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff));
+
+ regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ,
+ AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ |
+ AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ |
+ AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ |
+ AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ);
+
+ regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB,
+ AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ);
+
+ regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB,
+ AIROHA_PCS_ANA_FE_VCM_GEN_PWDB);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1,
+ AIROHA_PCS_PMA_LCPLL_MAN_PWDB);
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_AEQ_CFORCE,
+ AIROHA_PCS_ANA_AEQ_OFORCE,
+ AIROHA_PCS_ANA_AEQ_OFORCE_CTLE);
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW,
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE,
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH |
+ AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS);
+
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4,
+ AIROHA_PCS_PMA_DISB_BLWC_OFFSET);
+
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL,
+ AIROHA_PCS_PMA_DISB_LEQ);
+
+ regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV,
+ AIROHA_PCS_ANA_CDR_PD_EDGE_DIS |
+ AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV);
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON |
+ AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL);
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,
+ AIROHA_PCS_ANA_RX_DAC_MON |
+ AIROHA_PCS_ANA_CDR_PR_XFICK_EN |
+ AIROHA_PCS_ANA_CDR_PR_MONDPI_EN |
+ AIROHA_PCS_ANA_CDR_PR_MONDPR_EN,
+ FIELD_PREP(AIROHA_PCS_ANA_RX_DAC_MON, 0x0) |
+ AIROHA_PCS_ANA_CDR_PR_XFICK_EN);
+
+ /* Setup FE Gain and FE Peacking */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PEAKING_CTRL |
+ AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL, 0x0));
+
+ /* Setup FE VOS */
+ if (interface != PHY_INTERFACE_MODE_USXGMII &&
+ interface != PHY_INTERFACE_MODE_10GBASER)
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+ AIROHA_PCS_PMA_FORCE_DA_FE_VOS,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0));
+
+ /* Setup FLL PR FMeter (no bypass mode)*/
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0,
+ AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1,
+ AIROHA_PCS_PMA_PLL_LOCK_TARGET_END |
+ AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) |
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3,
+ AIROHA_PCS_PMA_PLL_LOCK_LOCKTH,
+ FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1));
+
+ /* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */
+ /* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */
+ /* Setup REV */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_REV_0,
+ AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL |
+ AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL |
+ AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK,
+ FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL, BIT(2)) |
+ FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL, BIT(2)) |
+ FIELD_PREP(AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK, 0x0));
+
+ /* Setup Rdy Timeout */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5,
+ AIROHA_PCS_PMA_RX_RDY |
+ AIROHA_PCS_PMA_RX_BLWC_RDY_EN,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5));
+
+ /* Setup CaBoundry Init */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,
+ AIROHA_PCS_PMA_RX_OS_START |
+ AIROHA_PCS_PMA_OSC_SPEED_OPT,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) |
+ AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1);
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6,
+ AIROHA_PCS_PMA_RX_OS_END,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1,
+ AIROHA_PCS_PMA_RX_PICAL_END |
+ AIROHA_PCS_PMA_RX_PICAL_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4,
+ AIROHA_PCS_PMA_RX_SDCAL_END |
+ AIROHA_PCS_PMA_RX_SDCAL_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2,
+ AIROHA_PCS_PMA_RX_PDOS_END |
+ AIROHA_PCS_PMA_RX_PDOS_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3,
+ AIROHA_PCS_PMA_RX_FEOS_END |
+ AIROHA_PCS_PMA_RX_FEOS_START,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) |
+ FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2));
+
+ /* Setup By Serdes*/
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+ AIROHA_PCS_PMA_FORCE_DA_OSR_SEL,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr));
+
+ /* Setup RX OSR */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV,
+ AIROHA_PCS_ANA_CDR_PD_EDGE_DIS,
+ osr ? AIROHA_PCS_ANA_CDR_PD_EDGE_DIS : 0);
+
+ /* Setup CDR LPF Ratio */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO,
+ AIROHA_PCS_ANA_CDR_LPF_TOP_LIM |
+ AIROHA_PCS_ANA_CDR_LPF_RATIO,
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_TOP_LIM, 0x20000) |
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_RATIO, osr));
+
+ /* Setup CDR PR */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC,
+ AIROHA_PCS_ANA_CDR_PR_KBAND_DIV |
+ AIROHA_PCS_ANA_CDR_PR_BETA_SEL |
+ AIROHA_PCS_ANA_CDR_PR_VCOADC_OS |
+ AIROHA_PCS_ANA_CDR_PR_BETA_DAC,
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_KBAND_DIV, 0x4) |
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_SEL, 0x1) |
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VCOADC_OS, 0x8) |
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_DAC, pr_cdr_beta_dac));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL,
+ AIROHA_PCS_ANA_CDR_PR_FBKSEL |
+ AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND |
+ AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL |
+ AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL,
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_FBKSEL, 0x0) |
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND, pr_cdr_beta_dac) |
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL, 0x6) |
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL, 0x6));
+
+ /* Setup Eye Mon */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_3,
+ AIROHA_PCS_PMA_EQ_DEBUG_SEL |
+ AIROHA_PCS_PMA_FOM_NUM_ORDER |
+ AIROHA_PCS_PMA_A_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) |
+ FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) |
+ FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,
+ AIROHA_PCS_PMA_DATA_SHIFT |
+ AIROHA_PCS_PMA_EYECNT_FAST,
+ AIROHA_PCS_PMA_EYECNT_FAST);
+
+ /* Calibration Start */
+
+ /* Enable SYS */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0,
+ AIROHA_PCS_PMA_RX_SYS_EN_SEL,
+ FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1));
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0,
+ AIROHA_PCS_PMA_SW_LCPLL_EN);
+
+ usleep_range(500, 600);
+
+ /* Setup FLL PR FMeter (bypass mode)*/
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
+ AIROHA_PCS_PMA_DISB_FBCK_LOCK);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
+ AIROHA_PCS_PMA_FORCE_FBCK_LOCK);
+
+ /* Enable CMLEQ */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN,
+ AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |
+ AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |
+ AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN |
+ AIROHA_PCS_ANA_RX_FE_EQ_HZEN,
+ AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |
+ AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |
+ AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN);
+
+ /* Setup CDR PR */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,
+ AIROHA_PCS_ANA_CDR_PR_CAP_EN |
+ AIROHA_PCS_ANA_CDR_BUF_IN_SR,
+ (cdr_pr_cap_en ? AIROHA_PCS_ANA_CDR_PR_CAP_EN : 0) |
+ FIELD_PREP(AIROHA_PCS_ANA_CDR_BUF_IN_SR, cdr_pr_buf_in_sr));
+
+ /* Setup CDR xxx Pwdb, set force and disable */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB);
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB);
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB);
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B |
+ AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB);
+
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+ AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+ AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+ /* FIXME: Ask Airoha WHY it's cleared? */
+ /* regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+ * AIROHA_PCS_ANA_RX_FE_50OHMS_SEL);
+ */
+
+ /* Setup SigDet */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
+ AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL |
+ AIROHA_PCS_ANA_RX_SIGDET_PEAK,
+ FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL, sigdet_vth_sel) |
+ FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_PEAK, BIT(1)));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_RANGE,
+ AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL,
+ FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL, BIT(1) | BIT(0)));
+
+ /* Disable SigDet Pwdb */
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+ AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+
+ /* Setup PHYCK */
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV,
+ AIROHA_PCS_ANA_RX_TDC_CK_SEL |
+ AIROHA_PCS_ANA_RX_PHYCK_RSTB |
+ AIROHA_PCS_ANA_RX_PHYCK_SEL |
+ AIROHA_PCS_ANA_RX_PHYCK_DIV,
+ AIROHA_PCS_ANA_RX_PHYCK_RSTB |
+ FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_SEL, phyck_sel) |
+ FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_DIV, phyck_div));
+
+ regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL,
+ AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE |
+ AIROHA_PCS_ANA_RX_PHY_CK_SEL,
+ AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE);
+
+ usleep_range(100, 200);
+
+ /* Enable CDR xxx Pwdb */
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
+ AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
+ AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
+ AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
+ AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
+
+ /* Enable SigDet Pwdb */
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
+ AIROHA_PCS_PMA_RX_SIDGET_PWDB);
+}
+
+static unsigned int airoha_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv,
+ u32 cdr_pr_idac)
+{
+ u32 val;
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+ FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
+ cdr_pr_idac));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0);
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN,
+ AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL);
+
+ usleep_range(5000, 7000);
+
+ regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+
+ return FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val);
+}
+
+static void airoha_pcs_rx_prcal(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ unsigned int remaining_prcal_search_bits = 8;
+ unsigned int prcal_search_bit;
+ bool prcal_search_from_bottom;
+ unsigned int prcal_search;
+ unsigned int fl_out_diff = UINT_MAX;
+ unsigned int fl_out;
+ int cdr_pr_idac = 0;
+
+ u32 target_fl_out;
+ u32 cyclecnt;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII: /* DS_1.25G / US_1.25G */
+ case PHY_INTERFACE_MODE_1000BASEX:
+ target_fl_out = 0xa3d6;
+ cyclecnt = 32767;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G / US_9.95328G */
+ target_fl_out = 0xa000;
+ cyclecnt = 20000;
+ break;
+ case PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G / US_1.25G */
+ case PHY_INTERFACE_MODE_10GBASER:
+ target_fl_out = 0x9edf;
+ cyclecnt = 32767;
+ break;
+ default:
+ return;
+ }
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2,
+ AIROHA_PCS_PMA_LOCK_TARGET_END |
+ AIROHA_PCS_PMA_LOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1,
+ AIROHA_PCS_PMA_UNLOCK_CYCLECNT |
+ AIROHA_PCS_PMA_LOCK_CYCLECNT,
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
+ AIROHA_PCS_PMA_LOCK_UNLOCKTH |
+ AIROHA_PCS_PMA_LOCK_LOCKTH,
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) |
+ FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3));
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3,
+ AIROHA_PCS_PMA_UNLOCK_TARGET_END |
+ AIROHA_PCS_PMA_UNLOCK_TARGET_BEG,
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) |
+ FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100));
+
+ regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE,
+ AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF);
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ /* Calibration logic:
+ * First check the major value by looping with every
+ * value in the last 3 bit of CDR_PR_IDAC.
+ * Get the signal level and save the value that if closer to
+ * the target.
+ *
+ * Then fine tune for the remaining 7 bit to find the one that
+ * produce the closest signal level.
+ */
+ for (prcal_search = 0; prcal_search < 8 ; prcal_search++) {
+ u32 cdr_pr_idac_tmp;
+
+ /* try to find the upper value by setting the last 3 bit */
+ cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
+ prcal_search);
+ fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ if (abs(fl_out - target_fl_out) < fl_out_diff) {
+ cdr_pr_idac = cdr_pr_idac_tmp;
+ fl_out_diff = abs(fl_out - target_fl_out);
+ }
+ }
+
+ /* Understand if we need to fine tune by increasing or decreasing fl_out.
+ * This is done by setting BIT (7) and check if the abs fl_out diff from target
+ * increase or decrease.
+ * If it does increase, we need to decrease fl_out, hence we search from MAX to MIN.
+ * If it does decrease, we need to increase fl_out, hence we search from MIN to MAX.
+ */
+ fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac | BIT(7));
+ if (abs(fl_out - target_fl_out) < fl_out_diff) {
+ prcal_search_from_bottom = false;
+ prcal_search_bit = 7;
+ } else {
+ prcal_search_from_bottom = true;
+ prcal_search_bit = 0;
+ }
+
+ /* Fine tune part.
+ * Continue searching until we find a deadline where the signal
+ * level starts to increase/decrease. Once that is reached, start
+ * the loop again to progressely find a closer signal level to
+ * the target.
+ */
+ while (remaining_prcal_search_bits) {
+ unsigned int fl_out_diff_new;
+ u32 cdr_pr_idac_tmp;
+
+ cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
+ fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);
+
+ /* Use absolute values to find the closest one to target */
+ fl_out_diff_new = abs(fl_out - target_fl_out);
+ /* Assume we found the deadline when the new absolue signal difference
+ * from target is greater than the previous and the difference is at
+ * least 10% greater between the old and new value.
+ * This is to account for signal detection level tollerance making
+ * sure we are actually over a deadline (AKA we are getting farther
+ * from target)
+ */
+ if (fl_out_diff_new > fl_out_diff &&
+ (abs(fl_out_diff_new - fl_out_diff) * 100) / fl_out_diff > 10) {
+ /* Exit early if we are already at the deadline */
+ if (prcal_search_bit == 0 || prcal_search_bit == 7)
+ break;
+
+ /* We found the deadline, set the value to the previous
+ * bit, and reset the loop to fine tune with the
+ * remaining values.
+ */
+ if (prcal_search_from_bottom) {
+ cdr_pr_idac |= BIT(prcal_search_bit - 1);
+ remaining_prcal_search_bits = prcal_search_bit - 1;
+ prcal_search_bit = 0;
+ } else {
+ cdr_pr_idac |= BIT(prcal_search_bit + 1);
+ remaining_prcal_search_bits = prcal_search_bit + 1;
+ }
+ } else {
+ /* Update the signal level diff and try the next bit */
+ fl_out_diff = fl_out_diff_new;
+
+ /* If we didn't found the deadline, set the last bit
+ * and stop searching. This should not happen as it's expected
+ * we find an high signal level and we decrease it as it's
+ * much harder to reach target level by increasing the
+ * signal (by using a lower DAC value).
+ */
+ if (prcal_search_from_bottom) {
+ if (prcal_search_bit == 7) {
+ cdr_pr_idac |= BIT(prcal_search_bit);
+ break;
+ }
+
+ prcal_search_bit++;
+ } else {
+ if (prcal_search_bit == 0) {
+ cdr_pr_idac |= BIT(prcal_search_bit);
+ break;
+ }
+
+ prcal_search_bit--;
+ }
+ }
+ }
+
+ fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac);
+ dev_dbg(priv->dev, "Selected CDR Pr Idac: %x Fl Out: %x\n", cdr_pr_idac, fl_out);
+ if (abs(fl_out - target_fl_out) > 100)
+ dev_warn(priv->dev, "Fl Out is %d far from target %d. PCS might not function properly.\n",
+ abs(fl_out - target_fl_out), target_fl_out);
+
+ /* Setup Load Band */
+ regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE,
+ AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF);
+
+ /* Disable force of LPF C previously enabled */
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
+
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_B,
+ AIROHA_PCS_PMA_LOAD_EN);
+
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_1,
+ AIROHA_PCS_PMA_LPATH_IDAC,
+ FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac));
+
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
+
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+}
+
+/* This is used to both calibrate and lock to signal (after a previous
+ * calibration) after a global reset.
+ */
+static void airoha_pcs_cdr_reset(struct airoha_pcs_priv *priv,
+ phy_interface_t interface, bool calibrate)
+{
+ /* Setup LPF L2D force and disable */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+
+ /* Calibrate IDAC and setup Load Band */
+ if (calibrate)
+ airoha_pcs_rx_prcal(priv, interface);
+
+ /* Setup LPF RSTB force and disable */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+ usleep_range(700, 1000);
+
+ /* Force Enable LPF RSTB */
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
+
+ usleep_range(100, 200);
+
+ /* Force Enable LPF L2D */
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);
+
+ /* Disable LPF RSTB force bit */
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
+
+ /* Disable LPF L2D force bit */
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
+ AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
+}
+
+static int airoha_pcs_phya_bringup(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ int calibration_try = 0;
+ u32 val;
+
+ airoha_pcs_tx_bringup(priv, interface);
+ airoha_pcs_rx_bringup(priv, interface);
+
+ usleep_range(100, 200);
+
+retry_calibration:
+ airoha_pcs_cdr_reset(priv, interface, true);
+
+ /* Global reset clear */
+ regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+ AIROHA_PCS_PMA_SW_REF_RST_N |
+ AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+ AIROHA_PCS_PMA_SW_PMA_RST_N |
+ AIROHA_PCS_PMA_SW_TX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N,
+ AIROHA_PCS_PMA_SW_REF_RST_N);
+
+ usleep_range(100, 200);
+
+ /* Global reset */
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
+ AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
+ AIROHA_PCS_PMA_SW_REF_RST_N |
+ AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
+ AIROHA_PCS_PMA_SW_PMA_RST_N |
+ AIROHA_PCS_PMA_SW_TX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_RST_N |
+ AIROHA_PCS_PMA_SW_RX_FIFO_RST_N);
+
+ usleep_range(5000, 7000);
+
+ airoha_pcs_cdr_reset(priv, interface, false);
+
+ /* It was discovered that after a global reset and auto mode gets
+ * actually enabled, the fl_out from calibration might change and
+ * might deviates a lot from the expected value it was calibrated for.
+ * To correctly work, the PCS FreqDet module needs to Lock to the fl_out
+ * (frequency level output) or no signal can correctly be transmitted.
+ * This is detected by checking the FreqDet module Lock bit.
+ *
+ * If it's detected that the FreqDet module is not locked, retry
+ * calibration. From observation on real hardware with a 10g SFP module,
+ * it required a maximum of an additional calibration to actually make
+ * the FreqDet module to lock. Try 10 times before failing to handle
+ * really strange case.
+ */
+ regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
+ if (!(val & AIROHA_PCS_PMA_FBCK_LOCK)) {
+ if (calibration_try > AIROHA_PCS_MAX_CALIBRATION_TRY) {
+ dev_err(priv->dev, "No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\n",
+ AIROHA_PCS_MAX_CALIBRATION_TRY);
+ return -EIO;
+ }
+
+ calibration_try++;
+
+ dev_dbg(priv->dev, "No FBCK Lock from FreqDet module, retry calibration.\n");
+ goto retry_calibration;
+ }
+
+ return 0;
+}
+
+static void airoha_pcs_get_state_sgmii(struct airoha_pcs_priv *priv,
+ unsigned int neg_mode,
+ struct phylink_link_state *state)
+{
+ u32 bmsr, lpa;
+
+ regmap_read(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,
+ &bmsr);
+ regmap_read(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5,
+ &lpa);
+
+ bmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
+ lpa = AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY & lpa;
+
+ phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa);
+}
+
+static void airoha_pcs_get_state_usxgmii(struct airoha_pcs_priv *priv,
+ struct phylink_link_state *state)
+{
+ u32 lpa;
+
+ /* Toggle AN Status */
+ regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+ regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
+ AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
+
+ regmap_read(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &lpa);
+
+ state->link = !!(lpa & MDIO_USXGMII_LINK);
+ state->an_complete = state->link;
+
+ phylink_decode_usxgmii_word(state, lpa);
+}
+
+static void airoha_pcs_get_state(struct phylink_pcs *pcs,
+ unsigned int neg_mode,
+ struct phylink_link_state *state)
+{
+ struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+ switch (state->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ airoha_pcs_get_state_sgmii(priv, neg_mode, state);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ airoha_pcs_get_state_usxgmii(priv, state);
+ break;
+ default:
+ return;
+ }
+}
+
+static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+ bool permit_pause_to_mac)
+{
+ struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+ u32 rate_adapt;
+ int ret;
+
+ priv->interface = interface;
+
+ /* Select HSGMII or USXGMII in SCU regs */
+ airoha_pcs_setup_scu(priv, interface);
+
+ /* Enable Analog Common Lane */
+ regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CMN_EN,
+ AIROHA_PCS_ANA_CMN_EN);
+
+ /* Setup PLL */
+ airoha_pcs_pll_bringup(priv, interface);
+
+ /* Setup PHYA */
+ ret = airoha_pcs_phya_bringup(priv, interface);
+ if (ret)
+ return ret;
+
+ /* Set final configuration for various modes */
+ airoha_pcs_init(priv, interface);
+
+ /* Configure Interrupt for various modes */
+ airoha_pcs_interrupt_init(priv, interface);
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;
+ else
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;
+
+ /* AN Auto Settings (Rate Adaptation) */
+ regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt);
+
+ if (interface == PHY_INTERFACE_MODE_USXGMII ||
+ interface == PHY_INTERFACE_MODE_10GBASER) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ regmap_set_bits(priv->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+ else
+ regmap_clear_bits(priv->usxgmii_pcs,
+ AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_ENABLE);
+ }
+
+ /* Clear any force bit that my be set by bootloader */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+ AIROHA_PCS_LINK_MODE_P0 |
+ AIROHA_PCS_FORCE_SPD_MODE_P0 |
+ AIROHA_PCS_FORCE_LINKDOWN_P0 |
+ AIROHA_PCS_FORCE_LINKUP_P0);
+ }
+
+ /* Toggle Rate Adaption for SGMII/HSGMII mode */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ regmap_clear_bits(priv->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+ AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+ else
+ regmap_set_bits(priv->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
+ AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
+ }
+
+ /* Setup AN Link Timer */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ u32 an_timer;
+
+ an_timer = phylink_get_link_timer_ns(interface);
+
+ /* Value needs to be shifted by 4, seems value is internally * 16 */
+ regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11,
+ AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+ FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
+ an_timer >> 4));
+
+ regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_3,
+ AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+ FIELD_PREP(AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
+ an_timer >> 4));
+ }
+
+ /* Setup SGMII AN and advertisement in DEV_ABILITY */
+ if (interface == PHY_INTERFACE_MODE_SGMII &&
+ neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ int advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
+ advertising);
+ if (advertise < 0)
+ return advertise;
+
+ regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+
+ regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4,
+ AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+ FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
+ advertise));
+ } else {
+ regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 if_mode = AIROHA_PCS_HSGMII_AN_SGMII_EN |
+ AIROHA_PCS_HSGMII_AN_SIDEBAND_EN;
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+
+ /* Clear force speed bits and MAC mode */
+ regmap_clear_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+ AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+ } else {
+ if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN;
+
+ regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
+
+ /* AN off force rate adaption, speed is set later in Link Up */
+ regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_MAC_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT,
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
+ }
+
+ regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode);
+
+ /* FIXME: Airoha apply a different configuration here */
+ /* They force rate adaption */
+ regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_TX_ENABLE |
+ AIROHA_PCS_HSGMII_PCS_MODE2_EN);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_1000BASEX &&
+ neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_SGMII_SEND_AN_ERR_EN);
+
+ regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37,
+ AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE);
+ }
+
+ /* Configure Flow Control on XFI */
+ regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN,
+ permit_pause_to_mac ?
+ AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN :
+ 0);
+
+ return 0;
+}
+
+static void airoha_pcs_an_restart(struct phylink_pcs *pcs)
+{
+ struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+ switch (priv->interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+ udelay(3);
+ regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_RESTART);
+ udelay(3);
+ regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
+ AIROHA_PCS_USXGMII_AN_RESTART);
+ default:
+ return;
+ }
+}
+
+static void airoha_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface, int speed, int duplex)
+{
+ struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ regmap_update_bits(priv->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0));
+ udelay(1);
+ regmap_update_bits(priv->hsgmii_rate_adp,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
+ AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5));
+ }
+ } else {
+ if (interface == PHY_INTERFACE_MODE_USXGMII ||
+ interface == PHY_INTERFACE_MODE_10GBASER) {
+ u32 mode;
+ u32 rate_adapt;
+
+ switch (speed) {
+ case SPEED_10000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000;
+ mode = AIROHA_PCS_USXGMII_MODE_10000;
+ break;
+ case SPEED_5000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000;
+ mode = AIROHA_PCS_USXGMII_MODE_5000;
+ break;
+ case SPEED_2500:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500;
+ mode = AIROHA_PCS_USXGMII_MODE_2500;
+ break;
+ case SPEED_1000:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000;
+ mode = AIROHA_PCS_USXGMII_MODE_1000;
+ break;
+ case SPEED_100:
+ rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100;
+ mode = AIROHA_PCS_USXGMII_MODE_100;
+ break;
+ }
+
+ /* Trigger USXGMII change mode and force selected speed */
+ regmap_update_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
+ AIROHA_PCS_USXGMII_RATE_UPDATE_MODE |
+ AIROHA_PCS_USXGMII_MODE,
+ AIROHA_PCS_USXGMII_RATE_UPDATE_MODE | mode);
+
+ regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11,
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE,
+ AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
+ rate_adapt);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_1000BASEX) {
+ u32 force_speed;
+ u32 rate_adapt;
+
+ switch (speed) {
+ case SPEED_1000:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000;
+ break;
+ case SPEED_100:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100;
+ break;
+ case SPEED_10:
+ force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10;
+ rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10;
+ break;
+ }
+
+ regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
+ AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
+ AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL,
+ force_speed | rate_adapt);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_2500BASEX) {
+ u32 ck_gen_mode;
+ u32 speed_reg;
+ u32 if_mode;
+
+ switch (speed) {
+ case SPEED_2500:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G;
+ break;
+ case SPEED_1000:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_1G;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000;
+ break;
+ case SPEED_100:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100;
+ break;
+ case SPEED_10:
+ speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
+ if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10;
+ ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10;
+ break;
+ }
+
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
+ AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE,
+ if_mode);
+
+ regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE,
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE |
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL,
+ ck_gen_mode |
+ AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL);
+ }
+
+ regmap_update_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
+ AIROHA_PCS_LINK_MODE_P0 |
+ AIROHA_PCS_FORCE_SPD_MODE_P0,
+ speed_reg |
+ AIROHA_PCS_FORCE_SPD_MODE_P0);
+ }
+ }
+
+ /* Reset TXPCS on link up */
+ regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+
+ usleep_range(100, 200);
+
+ regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
+ AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
+}
+
+static const struct phylink_pcs_ops airoha_pcs_ops = {
+ .pcs_get_state = airoha_pcs_get_state,
+ .pcs_config = airoha_pcs_config,
+ .pcs_an_restart = airoha_pcs_an_restart,
+ .pcs_link_up = airoha_pcs_link_up,
+};
+
+static const struct regmap_config airoha_pcs_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int airoha_pcs_probe(struct platform_device *pdev)
+{
+ struct regmap_config syscon_config = airoha_pcs_regmap_config;
+ struct device *dev = &pdev->dev;
+ struct airoha_pcs_priv *priv;
+ void *base;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ priv->data = of_device_get_match_data(dev);
+
+ base = devm_platform_ioremap_resource_byname(pdev, "xfi_mac");
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ syscon_config.name = "xfi_mac";
+ priv->xfi_mac = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->xfi_mac))
+ return PTR_ERR(priv->xfi_mac);
+
+ base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_an");
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ syscon_config.name = "hsgmii_an";
+ priv->hsgmii_an = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->hsgmii_an))
+ return PTR_ERR(priv->hsgmii_an);
+
+ base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_pcs");
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ syscon_config.name = "hsgmii_pcs";
+ priv->hsgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->hsgmii_pcs))
+ return PTR_ERR(priv->hsgmii_pcs);
+
+ base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_rate_adp");
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ syscon_config.name = "hsgmii_rate_adp";
+ priv->hsgmii_rate_adp = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->hsgmii_rate_adp))
+ return PTR_ERR(priv->hsgmii_rate_adp);
+
+ base = devm_platform_ioremap_resource_byname(pdev, "multi_sgmii");
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ syscon_config.name = "multi_sgmii";
+ priv->multi_sgmii = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->multi_sgmii))
+ return PTR_ERR(priv->multi_sgmii);
+
+ base = devm_platform_ioremap_resource_byname(pdev, "usxgmii");
+ if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+ return PTR_ERR(base);
+
+ syscon_config.name = "usxgmii";
+ priv->usxgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->usxgmii_pcs))
+ return PTR_ERR(priv->usxgmii_pcs);
+
+ base = devm_platform_ioremap_resource_byname(pdev, "xfi_pma");
+ if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+ return PTR_ERR(base);
+
+ syscon_config.name = "xfi_pma";
+ priv->xfi_pma = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->xfi_pma))
+ return PTR_ERR(priv->xfi_pma);
+
+ base = devm_platform_ioremap_resource_byname(pdev, "xfi_ana");
+ if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+ return PTR_ERR(base);
+
+ syscon_config.name = "xfi_ana";
+ priv->xfi_ana = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->xfi_ana))
+ return PTR_ERR(priv->xfi_ana);
+
+ /* SCU is used to toggle XFI or HSGMII in global SoC registers */
+ priv->scu = syscon_regmap_lookup_by_compatible("airoha,en7581-scu");
+ if (IS_ERR(priv->scu))
+ return PTR_ERR(priv->scu);
+
+ priv->rsts[0].id = "mac";
+ priv->rsts[1].id = "phy";
+ ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to get bulk reset lines\n");
+
+ platform_set_drvdata(pdev, priv);
+
+ priv->pcs.ops = &airoha_pcs_ops;
+ priv->pcs.poll = true;
+
+ __set_bit(PHY_INTERFACE_MODE_SGMII, priv->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX, priv->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX, priv->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER, priv->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, priv->pcs.supported_interfaces);
+
+ return of_pcs_add_provider(dev->of_node, of_pcs_simple_get,
+ &priv->pcs);
+}
+
+static void airoha_pcs_remove(struct platform_device *pdev)
+{
+ struct airoha_pcs_priv *priv = platform_get_drvdata(pdev);
+
+ phylink_pcs_release(&priv->pcs);
+
+ of_pcs_del_provider(pdev->dev.of_node);
+}
+
+static const struct airoha_pcs_match_data an7581_pcs_eth = {
+ .port_type = AIROHA_PCS_ETH,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_pon = {
+ .port_type = AIROHA_PCS_PON,
+};
+
+static const struct of_device_id airoha_pcs_of_table[] = {
+ { .compatible = "airoha,an7581-pcs-eth", .data = &an7581_pcs_eth },
+ { .compatible = "airoha,an7581-pcs-pon", .data = &an7581_pcs_pon },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);
+
+static struct platform_driver airoha_pcs_driver = {
+ .driver = {
+ .name = "airoha-pcs",
+ .of_match_table = airoha_pcs_of_table,
+ },
+ .probe = airoha_pcs_probe,
+ .remove = airoha_pcs_remove,
+};
+module_platform_driver(airoha_pcs_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Airoha PCS driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
diff --git a/include/linux/pcs/pcs-airoha.h b/include/linux/pcs/pcs-airoha.h
new file mode 100644
index 000000000000..07797645ff15
--- /dev/null
+++ b/include/linux/pcs/pcs-airoha.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __LINUX_PCS_AIROHA_H
+#define __LINUX_PCS_AIROHA_H
+
+/* XFI_MAC */
+#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG 0x0
+#define AIROHA_PCS_XFI_TX_FC_EN BIT(5)
+#define AIROHA_PCS_XFI_RX_FC_EN BIT(4)
+
+#endif /* __LINUX_PCS_AIROHA_H */
--
2.48.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [net-next PATCH 6/6] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS
2025-03-18 23:58 [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF Christian Marangi
` (4 preceding siblings ...)
2025-03-18 23:58 ` [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC Christian Marangi
@ 2025-03-18 23:58 ` Christian Marangi
2025-03-21 16:22 ` Rob Herring
2025-03-19 17:29 ` [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF Russell King (Oracle)
2025-04-02 0:14 ` Sean Anderson
7 siblings, 1 reply; 34+ messages in thread
From: Christian Marangi @ 2025-03-18 23:58 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Russell King, Philipp Zabel, Christian Marangi,
Daniel Golle, netdev, devicetree, linux-kernel, upstream
Document support for Airoha Ethernet PCS for AN7581 SoC.
Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
the various Serdes port supporting different Media Independent Interface
(10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
This follow the new PCS provider with the use of #pcs-cells property.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
.../bindings/net/pcs/airoha,pcs.yaml | 112 ++++++++++++++++++
1 file changed, 112 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
diff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
new file mode 100644
index 000000000000..8bcf7757c728
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha Ethernet PCS and Serdes
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description:
+ Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
+ the various Serdes port supporting different Media Independent Interface
+ (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
+
+properties:
+ compatible:
+ enum:
+ - airoha,an7581-pcs-eth
+ - airoha,an7581-pcs-pon
+
+ reg:
+ items:
+ - description: XFI MAC reg
+ - description: HSGMII AN reg
+ - description: HSGMII PCS reg
+ - description: MULTI SGMII reg
+ - description: USXGMII reg
+ - description: HSGMII rate adaption reg
+ - description: XFI Analog register
+ - description: XFI PMA (Physical Medium Attachment) register
+
+ reg-names:
+ items:
+ - const: xfi_mac
+ - const: hsgmii_an
+ - const: hsgmii_pcs
+ - const: multi_sgmii
+ - const: usxgmii
+ - const: hsgmii_rate_adp
+ - const: xfi_ana
+ - const: xfi_pma
+
+ resets:
+ items:
+ - description: MAC reset
+ - description: PHY reset
+
+ reset-names:
+ items:
+ - const: mac
+ - const: phy
+
+ "#pcs-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - resets
+ - reset-names
+ - "#pcs-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/airoha,en7581-reset.h>
+
+ pcs@1fa08000 {
+ compatible = "airoha,an7581-pcs-pon";
+ reg = <0x1fa08000 0x1000>,
+ <0x1fa80000 0x60>,
+ <0x1fa80a00 0x164>,
+ <0x1fa84000 0x450>,
+ <0x1fa85900 0x338>,
+ <0x1fa86000 0x300>,
+ <0x1fa8a000 0x1000>,
+ <0x1fa8b000 0x1000>;
+ reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "usxgmii",
+ "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
+
+ resets = <&scuclk EN7581_XPON_MAC_RST>,
+ <&scuclk EN7581_XPON_PHY_RST>;
+ reset-names = "mac", "phy";
+
+ #pcs-cells = <0>;
+ };
+
+ pcs@1fa09000 {
+ compatible = "airoha,an7581-pcs-eth";
+ reg = <0x1fa09000 0x1000>,
+ <0x1fa70000 0x60>,
+ <0x1fa70a00 0x164>,
+ <0x1fa74000 0x450>,
+ <0x1fa75900 0x338>,
+ <0x1fa76000 0x300>,
+ <0x1fa7a000 0x1000>,
+ <0x1fa7b000 0x1000>;
+ reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "usxgmii",
+ "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
+
+ resets = <&scuclk EN7581_XSI_MAC_RST>,
+ <&scuclk EN7581_XSI_PHY_RST>;
+ reset-names = "mac", "phy";
+
+ #pcs-cells = <0>;
+ };
--
2.48.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver
2025-03-18 23:58 ` [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver Christian Marangi
@ 2025-03-19 9:11 ` Christian Marangi
2025-03-19 9:25 ` Christian Marangi
` (3 subsequent siblings)
4 siblings, 0 replies; 34+ messages in thread
From: Christian Marangi @ 2025-03-19 9:11 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Russell King, Philipp Zabel, Daniel Golle,
netdev, devicetree, linux-kernel, upstream
On Wed, Mar 19, 2025 at 12:58:38AM +0100, Christian Marangi wrote:
> Implement the foundation of OF support for PCS driver.
>
> To support this, implement a simple Provider API where a PCS driver can
> expose multiple PCS with an xlate .get function.
>
> PCS driver will have to call of_pcs_add_provider() and pass the device
> node pointer and a xlate function to return the correct PCS for the
> requested interface and the passed #pcs-cells.
>
> This will register the PCS in a global list of providers so that
> consumer can access it.
>
> Consumer will then use of_pcs_get() to get the actual PCS by passing the
> device_node pointer, the index for #pcs-cells and the requested
> interface.
>
> For simple implementation where #pcs-cells is 0 and the PCS driver
> expose a single PCS, the xlate function of_pcs_simple_get() is
> provided. In such case the passed interface is ignored and is expected
> that the PCS supports any interface mode supported by the MAC.
>
> For advanced implementation a custom xlate function is required. Such
> function should return an error if the PCS is not supported for the
> requested interface type.
>
> This is needed for the correct function of of_phylink_mac_select_pcs()
> later described.
>
> PCS driver on removal should first call phylink_pcs_release() on every
> PCS the driver provides and then correctly delete as a provider with
> the usage of of_pcs_del_provider().
>
> A generic function for .mac_select_pcs is provided for any MAC driver
> that will declare PCS in DT, of_phylink_mac_select_pcs().
> This function will parse "pcs-handle" property and will try every PCS
> declared in DT until one that supports the requested interface type is
> found. This works by leveraging the return value of the xlate function
> returned by of_pcs_get() and checking if it's an ERROR or NULL, in such
> case the next PCS in the phandle array is tested.
>
> Some additional helper are provided for xlate functions,
> pcs_supports_interface() as a simple function to check if the requested
> interface is supported by the PCS and phylink_pcs_release() to release a
> PCS from a phylink instance.
>
> Co-developed-by: Daniel Golle <daniel@makrotopia.org>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> drivers/net/pcs/Kconfig | 7 ++
> drivers/net/pcs/Makefile | 1 +
> drivers/net/pcs/pcs.c | 185 +++++++++++++++++++++++++++++++
> drivers/net/phy/phylink.c | 21 ++++
> include/linux/pcs/pcs-provider.h | 46 ++++++++
> include/linux/pcs/pcs.h | 62 +++++++++++
> include/linux/phylink.h | 2 +
> 7 files changed, 324 insertions(+)
> create mode 100644 drivers/net/pcs/pcs.c
> create mode 100644 include/linux/pcs/pcs-provider.h
> create mode 100644 include/linux/pcs/pcs.h
>
> diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
> index f6aa437473de..8c3b720de6fd 100644
> --- a/drivers/net/pcs/Kconfig
> +++ b/drivers/net/pcs/Kconfig
> @@ -5,6 +5,13 @@
>
> menu "PCS device drivers"
>
> +config OF_PCS
> + tristate
> + depends on OF
> + depends on PHYLINK
> + help
> + OpenFirmware PCS accessors
> +
> config PCS_XPCS
> tristate "Synopsys DesignWare Ethernet XPCS"
> select PHYLINK
> diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
> index 4f7920618b90..29881f0f981f 100644
> --- a/drivers/net/pcs/Makefile
> +++ b/drivers/net/pcs/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
> # Makefile for Linux PCS drivers
>
> +obj-$(CONFIG_OF_PCS) += pcs.o
> pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
> pcs-xpcs-nxp.o pcs-xpcs-wx.o
>
> diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
> new file mode 100644
> index 000000000000..af04a76ef825
> --- /dev/null
> +++ b/drivers/net/pcs/pcs.c
> @@ -0,0 +1,185 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +
> +#include <linux/mutex.h>
> +#include <linux/of.h>
> +#include <linux/phylink.h>
> +#include <linux/pcs/pcs.h>
> +#include <linux/pcs/pcs-provider.h>
> +
> +struct of_pcs_provider {
> + struct list_head link;
> +
> + struct device_node *node;
> + struct phylink_pcs *(*get)(struct of_phandle_args *pcsspec,
> + void *data,
> + phy_interface_t interface);
> +
> + void *data;
> +};
> +
> +static LIST_HEAD(of_pcs_providers);
> +static DEFINE_MUTEX(of_pcs_mutex);
> +
> +struct phylink_pcs *of_pcs_simple_get(struct of_phandle_args *pcsspec, void *data,
> + phy_interface_t interface)
> +{
> + struct phylink_pcs *pcs = data;
> +
> + if (!pcs_supports_interface(pcs, interface))
> + return ERR_PTR(-EOPNOTSUPP);
> +
> + return data;
> +}
> +EXPORT_SYMBOL_GPL(of_pcs_simple_get);
> +
> +int of_pcs_add_provider(struct device_node *np,
> + struct phylink_pcs *(*get)(struct of_phandle_args *pcsspec,
> + void *data,
> + phy_interface_t interface),
> + void *data)
> +{
> + struct of_pcs_provider *pp;
> +
> + if (!np)
> + return 0;
> +
> + pp = kzalloc(sizeof(*pp), GFP_KERNEL);
> + if (!pp)
> + return -ENOMEM;
> +
> + pp->node = of_node_get(np);
> + pp->data = data;
> + pp->get = get;
> +
> + mutex_lock(&of_pcs_mutex);
> + list_add(&pp->link, &of_pcs_providers);
> + mutex_unlock(&of_pcs_mutex);
> + pr_debug("Added pcs provider from %pOF\n", np);
> +
> + fwnode_dev_initialized(&np->fwnode, true);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(of_pcs_add_provider);
> +
> +void of_pcs_del_provider(struct device_node *np)
> +{
> + struct of_pcs_provider *pp;
> +
> + if (!np)
> + return;
> +
> + mutex_lock(&of_pcs_mutex);
> + list_for_each_entry(pp, &of_pcs_providers, link) {
> + if (pp->node == np) {
> + list_del(&pp->link);
> + fwnode_dev_initialized(&np->fwnode, false);
> + of_node_put(pp->node);
> + kfree(pp);
> + break;
> + }
> + }
> + mutex_unlock(&of_pcs_mutex);
> +}
> +EXPORT_SYMBOL_GPL(of_pcs_del_provider);
> +
> +static int of_parse_pcsspec(const struct device_node *np, int index,
> + const char *name, struct of_phandle_args *out_args)
> +{
> + int ret = -ENOENT;
> +
> + if (!np)
> + return -ENOENT;
> +
> + if (name)
> + index = of_property_match_string(np, "pcs-names", name);
> +
> + ret = of_parse_phandle_with_args(np, "pcs-handle", "#pcs-cells",
> + index, out_args);
> + if (ret || (name && index < 0))
> + return ret;
> +
> + return 0;
> +}
> +
> +static struct phylink_pcs *
> +of_pcs_get_from_pcsspec(struct of_phandle_args *pcsspec,
> + phy_interface_t interface)
> +{
> + struct of_pcs_provider *provider;
> + struct phylink_pcs *pcs = ERR_PTR(-EPROBE_DEFER);
> +
> + if (!pcsspec)
> + return ERR_PTR(-EINVAL);
> +
> + mutex_lock(&of_pcs_mutex);
> + list_for_each_entry(provider, &of_pcs_providers, link) {
> + if (provider->node == pcsspec->np) {
> + pcs = provider->get(pcsspec, provider->data,
> + interface);
> + if (!IS_ERR(pcs))
> + break;
> + }
> + }
> + mutex_unlock(&of_pcs_mutex);
> +
> + return pcs;
> +}
> +
> +static struct phylink_pcs *__of_pcs_get(struct device_node *np, int index,
> + const char *con_id,
> + phy_interface_t interface)
> +{
> + struct of_phandle_args pcsspec;
> + struct phylink_pcs *pcs;
> + int ret;
> +
> + ret = of_parse_pcsspec(np, index, con_id, &pcsspec);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + pcs = of_pcs_get_from_pcsspec(&pcsspec, interface);
> + of_node_put(pcsspec.np);
> +
> + return pcs;
> +}
> +
> +struct phylink_pcs *of_pcs_get(struct device_node *np, int index,
> + phy_interface_t interface)
> +{
> + return __of_pcs_get(np, index, NULL, interface);
> +}
> +EXPORT_SYMBOL_GPL(of_pcs_get);
> +
> +struct phylink_pcs *of_phylink_mac_select_pcs(struct phylink_config *config,
> + phy_interface_t interface)
> +{
> + int i, count;
> + struct device *dev = config->dev;
> + struct device_node *np = dev->of_node;
> + struct phylink_pcs *pcs = ERR_PTR(-ENODEV);
> +
> + /* To enable using_mac_select_pcs on phylink_create */
> + if (interface == PHY_INTERFACE_MODE_NA)
> + return NULL;
> +
> + /* Reject configuring PCS with Internal mode */
> + if (interface == PHY_INTERFACE_MODE_INTERNAL)
> + return ERR_PTR(-EINVAL);
> +
> + if (!of_property_present(np, "pcs-handle"))
> + return pcs;
> +
> + count = of_count_phandle_with_args(np, "pcs-handle", "#pcs-cells");
> + if (count < 0)
> + return ERR_PTR(count);
> +
> + for (i = 0; i < count; i++) {
> + pcs = of_pcs_get(np, i, interface);
> + if (!IS_ERR_OR_NULL(pcs))
> + return pcs;
> + }
> +
> + return pcs;
> +}
> +EXPORT_SYMBOL_GPL(of_phylink_mac_select_pcs);
> diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
> index eef1712ec22c..7f71547e89fe 100644
> --- a/drivers/net/phy/phylink.c
> +++ b/drivers/net/phy/phylink.c
> @@ -1130,6 +1130,27 @@ int phylink_pcs_pre_init(struct phylink *pl, struct phylink_pcs *pcs)
> }
> EXPORT_SYMBOL_GPL(phylink_pcs_pre_init);
>
> +/**
> + * phylink_pcs_release() - release a PCS
> + * @pl: a pointer to &struct phylink_pcs
This is a typo and will be fixed in v2.
> + *
> + * PCS provider can use this to release a PCS from a phylink
> + * instance by stopping the attached netdev. This is only done
> + * if the PCS is actually attached to a phylink, otherwise is
> + * ignored.
> + */
> +void phylink_pcs_release(struct phylink_pcs *pcs)
> +{
> + struct phylink *pl = pcs->phylink;
> +
> + if (pl) {
> + rtnl_lock();
> + dev_close(pl->netdev);
> + rtnl_unlock();
> + }
> +}
> +EXPORT_SYMBOL_GPL(phylink_pcs_release);
> +
> static void phylink_mac_config(struct phylink *pl,
> const struct phylink_link_state *state)
> {
> diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
> new file mode 100644
> index 000000000000..0172d0286f07
> --- /dev/null
> +++ b/include/linux/pcs/pcs-provider.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +#ifndef __LINUX_PCS_PROVIDER_H
> +#define __LINUX_PCS_PROVIDER_H
> +
> +#include <linux/phy.h>
> +
> +/**
> + * of_pcs_simple_get - Simple xlate function to retrieve PCS
> + * @pcsspec: Phandle arguments
> + * @data: Context data (assumed assigned to the single PCS)
> + * @interface: requested PHY interface type for PCS
> + *
> + * Returns the PCS (pointed by data) or an -EOPNOTSUPP pointer
> + * if the PCS doesn't support the requested interface.
> + */
> +struct phylink_pcs *of_pcs_simple_get(struct of_phandle_args *pcsspec, void *data,
> + phy_interface_t interface);
> +
> +/**
> + * of_pcs_add_provider - Registers a new PCS provider
> + * @np: Device node
> + * @get: xlate function to retrieve the PCS
> + * @data: Context data
> + *
> + * Register and add a new PCS to the global providers list
> + * for the device node. A function to get the PCS from
> + * device node with the use of phandle args.
> + * To the get function is also passed the interface type
> + * requested for the PHY. PCS driver will use the passed
> + * interface to understand if the PCS can support it or not.
> + *
> + * Returns 0 on success or -ENOMEM on allocation failure.
> + */
> +int of_pcs_add_provider(struct device_node *np,
> + struct phylink_pcs *(*get)(struct of_phandle_args *pcsspec,
> + void *data,
> + phy_interface_t interface),
> + void *data);
> +
> +/**
> + * of_pcs_del_provider - Removes a PCS provider
> + * @np: Device node
> + */
> +void of_pcs_del_provider(struct device_node *np);
> +
> +#endif /* __LINUX_PCS_PROVIDER_H */
> diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
> new file mode 100644
> index 000000000000..b681bf05ac08
> --- /dev/null
> +++ b/include/linux/pcs/pcs.h
> @@ -0,0 +1,62 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +#ifndef __LINUX_PCS_H
> +#define __LINUX_PCS_H
> +
> +#include <linux/phy.h>
> +#include <linux/phylink.h>
> +
> +static inline bool pcs_supports_interface(struct phylink_pcs *pcs,
> + phy_interface_t interface)
> +{
> + return test_bit(interface, pcs->supported_interfaces);
> +}
> +
> +#ifdef CONFIG_OF_PCS
> +/**
> + * of_pcs_get - Retrieves a PCS from a device node
> + * @np: Device node
> + * @index: Index of PCS handle in Device Node
> + * @interface: requested PHY interface type for PCS
> + *
> + * Get a PCS for the requested PHY interface type from the
> + * device node at index.
> + *
> + * Returns a pointer to the phylink_pcs or a negative
> + * error pointer. Can return -EPROBE_DEFER if the PCS is not
> + * present in global providers list (either due to driver
> + * still needs to be probed or it failed to probe/removed)
> + */
> +struct phylink_pcs *of_pcs_get(struct device_node *np, int index,
> + phy_interface_t interface);
> +
> +/**
> + * of_phylink_mac_select_pcs - Generic MAC select pcs for OF PCS provider
> + * @config: phylink config pointer
> + * @interface: requested PHY interface type for PCS
> + *
> + * Generic helper function to get a PCS from a "pcs-handle" OF property
> + * defined in device tree. Each phandle defined in "pcs-handle" will be
> + * tested until a PCS that supports the requested PHY interface is found.
> + *
> + * Returns a pointer to the selected PCS or an error pointer.
> + * Return NULL for PHY_INTERFACE_MODE_NA and a -EINVAL error pointer
> + * for PHY_INTERFACE_MODE_INTERNAL. It can also return -EPROBE_DEFER,
> + * refer to of_pcs_get for details about it.
> + */
> +struct phylink_pcs *of_phylink_mac_select_pcs(struct phylink_config *config,
> + phy_interface_t interface);
> +#else
> +static inline struct phylink_pcs *of_pcs_get(struct device_node *np, int index,
> + phy_interface_t interface)
> +{
> + return PTR_ERR(-ENOENT);
> +}
> +
> +static inline struct phylink_pcs *of_phylink_mac_select_pcs(struct phylink_config *config,
> + phy_interface_t interface)
> +{
> + return PTR_ERR(-EOPNOTSUPP);
> +}
> +#endif
> +
> +#endif /* __LINUX_PCS_H */
> diff --git a/include/linux/phylink.h b/include/linux/phylink.h
> index c187267a15b6..80367d4fbad9 100644
> --- a/include/linux/phylink.h
> +++ b/include/linux/phylink.h
> @@ -695,6 +695,8 @@ void phylink_pcs_change(struct phylink_pcs *, bool up);
>
> int phylink_pcs_pre_init(struct phylink *pl, struct phylink_pcs *pcs);
>
> +void phylink_pcs_release(struct phylink_pcs *pcs);
> +
> void phylink_start(struct phylink *);
> void phylink_stop(struct phylink *);
>
> --
> 2.48.1
>
--
Ansuel
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC
2025-03-18 23:58 ` [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC Christian Marangi
@ 2025-03-19 9:13 ` Christian Marangi
2025-03-19 20:41 ` kernel test robot
` (2 subsequent siblings)
3 siblings, 0 replies; 34+ messages in thread
From: Christian Marangi @ 2025-03-19 9:13 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Russell King, Philipp Zabel, Daniel Golle,
netdev, devicetree, linux-kernel, upstream
On Wed, Mar 19, 2025 at 12:58:41AM +0100, Christian Marangi wrote:
> Add PCS driver for Airoha SoC for Ethernet Serdes and PCS and permit
> usage of external PHY or connected SFP cage. Supported modes are
> USXGMII, 10-BASER, 2500BASE-X, 1000BASE-X and SGMII.
>
> The driver register as a PCS provider and supports poll mode to detect
> PCS port state. While interrupt is supported by the HW, there are some
> defect with the interrupt not fired on cable detach.
>
> The PCS require complex calibration to correctly work and might require
> multiple try until the signal detection module "lock" on the signal
> level to correct work with the attached PHY.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> drivers/net/pcs/Kconfig | 6 +
> drivers/net/pcs/Makefile | 1 +
> drivers/net/pcs/pcs-airoha.c | 2858 ++++++++++++++++++++++++++++++++
> include/linux/pcs/pcs-airoha.h | 11 +
> 4 files changed, 2876 insertions(+)
> create mode 100644 drivers/net/pcs/pcs-airoha.c
> create mode 100644 include/linux/pcs/pcs-airoha.h
>
> diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
> index 8c3b720de6fd..f0ad087286be 100644
> --- a/drivers/net/pcs/Kconfig
> +++ b/drivers/net/pcs/Kconfig
> @@ -12,6 +12,12 @@ config OF_PCS
> help
> OpenFirmware PCS accessors
>
> +config PCS_AIROHA
> + tristate "Airoha PCS driver"
> + help
> + This module provides helper to phylink for managing the Airoha
> + PCS for SoC Ethernet Serdes and PCS.
> +
In adding the final changes from staging, it was forgot to add
select OF_PCS to PCS_AIROHA. This will be fixed in v2.
(the cause of the compilation error)
> config PCS_XPCS
> tristate "Synopsys DesignWare Ethernet XPCS"
> select PHYLINK
> diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
> index 29881f0f981f..4ce759cd6ad9 100644
> --- a/drivers/net/pcs/Makefile
> +++ b/drivers/net/pcs/Makefile
> @@ -2,6 +2,7 @@
> # Makefile for Linux PCS drivers
>
> obj-$(CONFIG_OF_PCS) += pcs.o
> +obj-$(CONFIG_PCS_AIROHA) += pcs-airoha.o
> pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
> pcs-xpcs-nxp.o pcs-xpcs-wx.o
>
> diff --git a/drivers/net/pcs/pcs-airoha.c b/drivers/net/pcs/pcs-airoha.c
> new file mode 100644
> index 000000000000..7f33d5c0799e
> --- /dev/null
> +++ b/drivers/net/pcs/pcs-airoha.c
> @@ -0,0 +1,2858 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2024 AIROHA Inc
> + * Author: Christian Marangi <ansuelsmth@gmail.com>
> + */
> +
> +#include <linux/device.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/pcs/pcs-airoha.h>
> +#include <linux/pcs/pcs-provider.h>
> +#include <linux/phylink.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +
> +/* SCU*/
> +#define AIROHA_SCU_WAN_CONF 0x70
> +#define AIROHA_SCU_WAN_SEL GENMASK(7, 0)
> +#define AIROHA_SCU_WAN_SEL_SGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)
> +#define AIROHA_SCU_WAN_SEL_HSGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)
> +#define AIROHA_SCU_WAN_SEL_USXGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12)
> +#define AIROHA_SCU_SSR3 0x94
> +#define AIROHA_SCU_ETH_XSI_SEL GENMASK(14, 13)
> +#define AIROHA_SCU_ETH_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1)
> +#define AIROHA_SCU_ETH_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2)
> +#define AIROHA_SCU_SSTR 0x9c
> +#define AIROHA_SCU_PON_XSI_SEL GENMASK(10, 9)
> +#define AIROHA_SCU_PON_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1)
> +#define AIROHA_SCU_PON_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2)
> +
> +/* HSGMII_AN */
> +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0 0x0
> +#define AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE BIT(12)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART BIT(9)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1 0x4 /* BMSR */
> +#define AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4 0x10
> +#define AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5 0x14 /* LPA */
> +#define AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11 0x2c
> +#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER GENMASK(19, 0)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13 0x34
> +#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5)
> +#define AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4)
> +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2)
> +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2)
> +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1)
> +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0)
> +#define AIROHA_PCS_HSGMII_AN_SIDEBAND_EN BIT(1)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_EN BIT(0)
> +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60
> +#define AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE BIT(0)
> +
> +/* HSGMII_PCS */
> +#define AIROHA_PCS_HSGMII_PCS_CTROL_1 0x0
> +#define AIROHA_PCS_TBI_10B_MODE BIT(30)
> +#define AIROHA_PCS_SGMII_SEND_AN_ERR_EN BIT(24)
> +#define AIROHA_PCS_REMOTE_FAULT_DIS BIT(12)
> +#define AIROHA_PCS_HSGMII_PCS_CTROL_3 0x8
> +#define AIROHA_PCS_HSGMII_PCS_LINK_STSTIME GENMASK(19, 0)
> +#define AIROHA_PCS_HSGMII_PCS_CTROL_6 0x14
> +#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14)
> +#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13)
> +#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12)
> +#define AIROHA_PCS_HSGMII_PCS_MAC_MODE BIT(8)
> +#define AIROHA_PCS_HSGMII_PCS_TX_ENABLE BIT(4)
> +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2)
> +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0)
> +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1)
> +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2)
> +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT BIT(1)
> +#define AIROHA_PCS_HSGMII_PCS_MODE2_EN BIT(0)
> +#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20
> +#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11)
> +#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10)
> +#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9)
> +#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8)
> +#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5)
> +#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT BIT(4)
> +#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3)
> +#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2)
> +#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1)
> +#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT BIT(0)
> +#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24
> +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
> +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0)
> +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1)
> +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2)
> +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0)
> +#define ARIOHA_PCS_HSGMII_PCS_STATE_2 0x104
> +#define AIROHA_PCS_HSGMII_PCS_RX_SYNC BIT(5)
> +#define AIROHA_PCS_HSGMII_PCS_AN_DONE BIT(0)
> +#define AIROHA_PCS_HSGMII_PCS_INT_STATE 0x15c
> +#define AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4)
> +#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS BIT(3)
> +#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2)
> +#define AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC BIT(1)
> +#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE BIT(0)
> +
> +/* MULTI_SGMII */
> +#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0 0x14
> +#define AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0 BIT(0)
> +#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18
> +#define AIROHA_PCS_LINK_MODE_P0 GENMASK(5, 4)
> +#define AIROHA_PCS_LINK_MODE_P0_2_5G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3)
> +#define AIROHA_PCS_LINK_MODE_P0_1G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2)
> +#define AIROHA_PCS_LINK_MODE_P0_100M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1)
> +#define AIROHA_PCS_LINK_MODE_P0_10M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0)
> +#define AIROHA_PCS_FORCE_SPD_MODE_P0 BIT(2)
> +#define AIROHA_PCS_FORCE_LINKDOWN_P0 BIT(1)
> +#define AIROHA_PCS_FORCE_LINKUP_P0 BIT(0)
> +#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0 0x100
> +#define AIROHA_PCS_HSGMII_XFI_SEL BIT(28)
> +#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL 0x14c
> +#define AIROHA_PCS_HSGMII_PCS_INT BIT(0)
> +#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15 0x43c
> +#define AIROHA_PCS_LINK_STS_P0 BIT(3)
> +#define AIROHA_PCS_SPEED_STS_P0 GENMASK(2, 0)
> +#define AIROHA_PCS_SPEED_STS_P0_1G FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2)
> +#define AIROHA_PCS_SPEED_STS_P0_100M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1)
> +#define AIROHA_PCS_SPEED_STS_P0_10M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0)
> +#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18 0x448
> +#define AIROHA_PCS_P0_SGMII_IS_10 BIT(2)
> +#define AIROHA_PCS_P0_SGMII_IS_100 BIT(1)
> +#define AIROHA_PCS_P0_SGMII_IS_1000 BIT(0)
> +
> +/* HSGMII_RATE_ADP */
> +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0 0x0
> +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27)
> +#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26)
> +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN BIT(4)
> +#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN BIT(0)
> +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1 0x4
> +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16)
> +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24)
> +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6 0x18
> +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0)
> +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8 0x20
> +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0)
> +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11 0x2c
> +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8)
> +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12)
> +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \
> + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0)
> +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \
> + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1)
> +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \
> + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2)
> +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \
> + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4)
> +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \
> + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6)
> +#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0 0x100
> +#define AIROHA_PCS_HSGMII_P0_DIS_MII_MODE BIT(31)
> +
> +/* USXGMII */
> +#define AIROHA_PCS_USXGMII_PCS_CTROL_1 0x0
> +#define AIROHA_PCS_USXGMII_SPEED_SEL_H BIT(13)
> +#define AIROHA_PCS_USXGMII_PCS_STUS_1 0x30
> +#define AIROHA_PCS_USXGMII_RX_LINK_STUS BIT(12)
> +#define AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3)
> +#define AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2)
> +#define AIROHA_PCS_USXGMII_PCS_BLK_LK BIT(0)
> +#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116 0x22c
> +#define AIROHA_PCS_USXGMII_PCS_CTRL_0 0x2c0
> +#define AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN BIT(24)
> +#define AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN BIT(16)
> +#define AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN BIT(8)
> +#define AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN BIT(0)
> +#define AIROHA_PCS_USXGMII_PCS_CTRL_1 0x2c4
> +#define AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN BIT(24)
> +#define AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN BIT(16)
> +#define AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8)
> +#define AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN BIT(0)
> +#define AIROHA_PCS_USXGMII_PCS_CTRL_2 0x2c8
> +#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24)
> +#define AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN BIT(16)
> +#define AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN BIT(8)
> +#define AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN BIT(0)
> +#define AIROHA_PCS_USXGMII_PCS_CTRL_3 0x2cc
> +#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24)
> +#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16)
> +#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN BIT(8)
> +#define AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN BIT(0)
> +#define AIROHA_PCS_USXGMII_PCS_INT_STA_2 0x2d8
> +#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24)
> +#define AIROHA_PCS_USXGMII_R_TYPE_E_INT BIT(16)
> +#define AIROHA_PCS_USXGMII_R_TYPE_T_INT BIT(8)
> +#define AIROHA_PCS_USXGMII_R_TYPE_D_INT BIT(0)
> +#define AIROHA_PCS_USXGMII_PCS_INT_STA_3 0x2dc
> +#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24)
> +#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16)
> +#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT BIT(8)
> +#define AIROHA_PCS_USXGMII_HI_BER_ST_INT BIT(0)
> +#define AIROHA_PCS_USXGMII_PCS_CTRL_4 0x2e0
> +#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0)
> +#define AIROHA_PCS_USXGMII_PCS_INT_STA_4 0x2e4
> +#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0)
> +#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0 0x2f8
> +#define AIROHA_PCS_USXGMII_AN_RESTART BIT(8)
> +#define AIROHA_PCS_USXGMII_AN_ENABLE BIT(0)
> +#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0 0x310
> +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE GENMASK(30, 28)
> +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0)
> +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1)
> +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2)
> +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3)
> +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4)
> +#define AIROHA_PCS_USXGMII_PARTNER_ABILITY GENMASK(15, 0)
> +#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2 0x318
> +#define AIROHA_PCS_USXGMII_PCS_AN_COMPLETE BIT(24)
> +#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6 0x31c
> +#define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)
> +#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7 0x320
> +#define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE BIT(12)
> +#define AIROHA_PCS_USXGMII_MODE GENMASK(10, 8)
> +#define AIROHA_PCS_USXGMII_MODE_10000 FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x0)
> +#define AIROHA_PCS_USXGMII_MODE_5000 FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x1)
> +#define AIROHA_PCS_USXGMII_MODE_2500 FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x2)
> +#define AIROHA_PCS_USXGMII_MODE_1000 FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x3)
> +#define AIROHA_PCS_USXGMII_MODE_100 FIELD_PREP(AIROHA_PCS_USXGMII_MODE, 0x4)
> +
> +/* PMA_PHYA */
> +#define AIROHA_PCS_ANA_PXP_CMN_EN 0x0
> +#define AIROHA_PCS_ANA_CMN_EN BIT(0)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN 0x4
> +#define AIROHA_PCS_ANA_JCPLL_CHP_IOFST GENMASK(29, 24)
> +#define AIROHA_PCS_ANA_JCPLL_CHP_IBIAS GENMASK(21, 16)
> +#define AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN BIT(8)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR 0x8
> +#define AIROHA_PCS_ANA_JCPLL_LPF_BWR GENMASK(28, 24)
> +#define AIROHA_PCS_ANA_JCPLL_LPF_BP GENMASK(20, 16)
> +#define AIROHA_PCS_ANA_JCPLL_LPF_BC GENMASK(12, 8)
> +#define AIROHA_PCS_ANA_JCPLL_LPF_BR GENMASK(4, 0)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC 0xc
> +#define AIROHA_PCS_ANA_JCPLL_KBAND_DIV GENMASK(26, 24)
> +#define AIROHA_PCS_ANA_JCPLL_KBAND_CODE GENMASK(23, 16)
> +#define AIROHA_PCS_ANA_JCPLL_KBAND_OPTION BIT(8)
> +#define AIROHA_PCS_ANA_JCPLL_LPF_BWC GENMASK(4, 0)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC 0x10
> +#define AIROHA_PCS_ANA_JCPLL_KBAND_KS GENMASK(17, 16)
> +#define AIROHA_PCS_ANA_JCPLL_KBAND_KF GENMASK(9, 8)
> +#define AIROHA_PCS_ANA_JCPLL_KBAND_KFC GENMASK(1, 0)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14
> +#define AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 BIT(24)
> +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0)
> +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x0)
> +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x1)
> +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x2)
> +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x3)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY 0x1c
> +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS GENMASK(25, 24)
> +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x0)
> +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x1)
> +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x2)
> +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x3)
> +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_EN BIT(16)
> +#define AIROHA_PCS_ANA_JCPLL_PLL_RSTB BIT(8)
> +#define AIROHA_PCS_ANA_JCPLL_RST_DLY GENMASK(2, 0)
> +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x1)
> +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x2)
> +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x3)
> +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x4)
> +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x5)
> +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x6)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM 0x20
> +#define AIROHA_PCS_ANA_JCPLL_SDM_OUT BIT(24)
> +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD GENMASK(17, 16)
> +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0)
> +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x1)
> +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x2)
> +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x3)
> +#define AIROHA_PCS_ANA_JCPLL_SDM_MODE GENMASK(9, 8)
> +#define AIROHA_PCS_ANA_JCPLL_SDM_IFM BIT(0)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN 0x24
> +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF GENMASK(28, 24)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN GENMASK(18, 16)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x0)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x1)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x2)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x3)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x4)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN BIT(8)
> +#define AIROHA_PCS_ANA_JCPLL_SDM_HREN BIT(0)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN 0x28
> +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x0)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x1)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x2)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x3)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x4)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x6)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN BIT(16)
> +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV 0x2c
> +#define AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR GENMASK(26, 24)
> +#define AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN BIT(16)
> +#define AIROHA_PCS_ANA_JCPLL_VCO_CFIX GENMASK(9, 8)
> +#define AIROHA_PCS_ANA_JCPLL_VCODIV GENMASK(1, 0)
> +#define AIROHA_PCS_ANA_JCPLL_VCODIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x0)
> +#define AIROHA_PCS_ANA_JCPLL_VCODIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x1)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR 0x30
> +#define AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI BIT(17)
> +#define AIROHA_PCS_ANA_JCPLL_SSC_EN BIT(16)
> +#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8)
> +#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3)
> +#define AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR GENMASK(2, 0)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN 0x34
> +#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 GENMASK(23, 8)
> +#define AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN BIT(0)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA 0x38
> +#define AIROHA_PCS_ANA_JCPLL_SSC_PERIOD GENMASK(31, 16)
> +#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA GENMASK(15, 0)
> +#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H 0x48
> +#define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF GENMASK(20, 16)
> +#define AIROHA_PCS_ANA_JCPLL_SPARE_L GENMASK(15, 8)
> +#define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5))
> +#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS 0x50
> +#define AIROHA_PCS_ANA_TXPLL_LPF_BC GENMASK(28, 24)
> +#define AIROHA_PCS_ANA_TXPLL_LPF_BR GENMASK(20, 16)
> +#define AIROHA_PCS_ANA_TXPLL_CHP_IOFST GENMASK(13, 8)
> +#define AIROHA_PCS_ANA_TXPLL_CHP_IBIAS GENMASK(5, 0)
> +#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP 0x54
> +#define AIROHA_PCS_ANA_TXPLL_KBAND_OPTION BIT(24)
> +#define AIROHA_PCS_ANA_TXPLL_LPF_BWC GENMASK(20, 16)
> +#define AIROHA_PCS_ANA_TXPLL_LPF_BWR GENMASK(12, 8)
> +#define AIROHA_PCS_ANA_TXPLL_LPF_BP GENMASK(4, 0)
> +#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE 0x58
> +#define AIROHA_PCS_ANA_TXPLL_KBAND_KF GENMASK(25, 24)
> +#define AIROHA_PCS_ANA_TXPLL_KBAND_KFC GENMASK(17, 16)
> +#define AIROHA_PCS_ANA_TXPLL_KBAND_DIV GENMASK(10, 8)
> +#define AIROHA_PCS_ANA_TXPLL_KBAND_CODE GENMASK(7, 0)
> +#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS 0x5c
> +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE GENMASK(17, 16)
> +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x0)
> +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x1)
> +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x2)
> +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x3)
> +#define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN BIT(8)
> +#define AIROHA_PCS_ANA_TXPLL_KBAND_KS GENMASK(1, 0)
> +#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL 0x64
> +#define AIROHA_PCS_ANA_TXPLL_PLL_RSTB BIT(24)
> +#define AIROHA_PCS_ANA_TXPLL_RST_DLY GENMASK(18, 16)
> +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV GENMASK(9, 8)
> +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x0)
> +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x1)
> +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x2)
> +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x3)
> +#define AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL BIT(0)
> +#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN 0x68
> +#define AIROHA_PCS_ANA_TXPLL_SDM_MODE GENMASK(25, 24)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_IFM BIT(16)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS GENMASK(9, 8)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x0)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x1)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x2)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x3)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_EN BIT(0)
> +#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD 0x6c
> +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN BIT(24)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_HREN BIT(16)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_OUT BIT(8)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD GENMASK(1, 0)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x0)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x1)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x2)
> +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x3)
> +#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN 0x70
> +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF GENMASK(12, 8)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN GENMASK(2, 0)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x0)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x1)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x2)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x3)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x4)
> +#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN 0x74
> +#define AIROHA_PCS_ANA_TXPLL_VCO_CFIX GENMASK(25, 24)
> +#define AIROHA_PCS_ANA_TXPLL_VCODIV GENMASK(17, 16)
> +#define AIROHA_PCS_ANA_TXPLL_VCODIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x0)
> +#define AIROHA_PCS_ANA_TXPLL_VCODIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1)
> +#define AIROHA_PCS_ANA_TXPLL_VCODIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW GENMASK(10, 8)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x0)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x1)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x2)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x3)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x4)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x6)
> +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN BIT(0)
> +#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN 0x78
> +#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27)
> +#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24)
> +#define AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR GENMASK(18, 16)
> +#define AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR GENMASK(10, 8)
> +#define AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN BIT(0)
> +#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN 0x7c
> +#define AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN BIT(16)
> +#define AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI BIT(8)
> +#define AIROHA_PCS_ANA_TXPLL_SSC_EN BIT(0)
> +#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1 0x80
> +#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA GENMASK(31, 16)
> +#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA1 GENMASK(15, 0)
> +#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD 0x84
> +#define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT GENMASK(25, 24)
> +#define AIROHA_PCS_ANA_TXPLL_LDO_OUT GENMASK(17, 16)
> +#define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD GENMASK(15, 0)
> +#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF 0x94
> +#define AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF GENMASK(4, 0)
> +#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN 0xc4
> +#define AIROHA_PCS_ANA_TX_DMEDGEGEN_EN BIT(24)
> +#define AIROHA_PCS_ANA_TX_CKLDO_EN BIT(0)
> +#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL 0xcc
> +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE BIT(24)
> +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL BIT(16) /* 0: from PR 1: from DES */
> +#define AIROHA_PCS_ANA_PXP_RX_REV_0 0xd4
> +#define AIROHA_PCS_ANA_RX_REV_1 GENMASK(31, 16)
> +#define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
> +#define AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24)
> +#define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
> +#define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK GENMASK(19, 18)
> +#define AIROHA_PCS_ANA_REV_1_FECUR_PWDB BIT(16)
> +#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV 0xd8
> +#define AIROHA_PCS_ANA_RX_TDC_CK_SEL BIT(24)
> +#define AIROHA_PCS_ANA_RX_PHYCK_RSTB BIT(16)
> +#define AIROHA_PCS_ANA_RX_PHYCK_SEL GENMASK(9, 8)
> +#define AIROHA_PCS_ANA_RX_PHYCK_DIV GENMASK(7, 0)
> +#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc
> +#define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS BIT(8)
> +#define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV BIT(0)
> +#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO 0xe8
> +#define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM GENMASK(26, 8)
> +#define AIROHA_PCS_ANA_CDR_LPF_RATIO GENMASK(1, 0)
> +#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE 0xf4
> +#define AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF BIT(24)
> +#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC 0xf8
> +#define AIROHA_PCS_ANA_CDR_PR_KBAND_DIV GENMASK(26, 24)
> +#define AIROHA_PCS_ANA_CDR_PR_BETA_SEL GENMASK(19, 16)
> +#define AIROHA_PCS_ANA_CDR_PR_VCOADC_OS GENMASK(11, 8)
> +#define AIROHA_PCS_ANA_CDR_PR_BETA_DAC GENMASK(6, 0)
> +#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc
> +#define AIROHA_PCS_ANA_CDR_PR_FBKSEL GENMASK(25, 24)
> +#define AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND GENMASK(20, 16)
> +#define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL GENMASK(10, 8)
> +#define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL GENMASK(2, 0)
> +#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN 0x10c
> +#define AIROHA_PCS_ANA_RX_DAC_MON GENMASK(28, 24)
> +#define AIROHA_PCS_ANA_CDR_PR_CAP_EN BIT(19)
> +#define AIROHA_PCS_ANA_CDR_BUF_IN_SR GENMASK(18, 16)
> +#define AIROHA_PCS_ANA_CDR_PR_XFICK_EN BIT(2)
> +#define AIROHA_PCS_ANA_CDR_PR_MONDPI_EN BIT(1)
> +#define AIROHA_PCS_ANA_CDR_PR_MONDPR_EN BIT(0)
> +#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE 0x110
> +#define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL GENMASK(25, 24)
> +#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH 0x114
> +#define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL GENMASK(25, 24)
> +#define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL GENMASK(20, 16)
> +#define AIROHA_PCS_ANA_RX_SIGDET_PEAK GENMASK(9, 8)
> +#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN 0x118
> +#define AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN BIT(24)
> +#define AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN BIT(16)
> +#define AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN BIT(8)
> +#define AIROHA_PCS_ANA_RX_FE_EQ_HZEN BIT(0)
> +#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB 0x11c
> +#define AIROHA_PCS_ANA_FE_VCM_GEN_PWDB BIT(0)
> +#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW 0x120
> +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE GENMASK(17, 8)
> +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(0))
> +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(1))
> +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(2))
> +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(3))
> +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(4))
> +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(5))
> +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(6))
> +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(7))
> +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(8))
> +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(9))
> +#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE 0x13c
> +#define AIROHA_PCS_ANA_AEQ_OFORCE GENMASK(19, 8)
> +#define AIROHA_PCS_ANA_AEQ_OFORCE_SAOS FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(0))
> +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(1))
> +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(2))
> +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(3))
> +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(4))
> +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(5))
> +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(6))
> +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(7))
> +#define AIROHA_PCS_ANA_AEQ_OFORCE_VGA FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(8))
> +#define AIROHA_PCS_ANA_AEQ_OFORCE_CTLE FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(9))
> +#define AIROHA_PCS_ANA_AEQ_OFORCE_ATT FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(10))
> +#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144
> +#define AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ BIT(24)
> +#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ 0x148
> +#define AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ BIT(24)
> +#define AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ BIT(16)
> +#define AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ BIT(8)
> +#define AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ BIT(0)
> +
> +/* PMA_PHYD */
> +#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0 0x0
> +#define AIROHA_PCS_PMA_SW_LCPLL_EN BIT(24)
> +#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1 0x4
> +#define AIROHA_PCS_PMA_LCPLL_MAN_PWDB BIT(0)
> +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2 0x88
> +#define AIROHA_PCS_PMA_DATA_SHIFT BIT(8)
> +#define AIROHA_PCS_PMA_EYECNT_FAST BIT(0)
> +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0 0x8c
> +#define AIROHA_PCS_PMA_RX_OS_START GENMASK(23, 8)
> +#define AIROHA_PCS_PMA_OSC_SPEED_OPT GENMASK(2, 0)
> +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0)
> +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1)
> +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2)
> +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3)
> +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4)
> +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5)
> +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6)
> +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7)
> +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1 0x90
> +#define AIROHA_PCS_PMA_RX_PICAL_END GENMASK(31, 16)
> +#define AIROHA_PCS_PMA_RX_PICAL_START GENMASK(15, 0)
> +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2 0x94
> +#define AIROHA_PCS_PMA_RX_PDOS_END GENMASK(31, 16)
> +#define AIROHA_PCS_PMA_RX_PDOS_START GENMASK(15, 0)
> +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3 0x98
> +#define AIROHA_PCS_PMA_RX_FEOS_END GENMASK(31, 16)
> +#define AIROHA_PCS_PMA_RX_FEOS_START GENMASK(15, 0)
> +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4 0x9c
> +#define AIROHA_PCS_PMA_RX_SDCAL_END GENMASK(31, 16)
> +#define AIROHA_PCS_PMA_RX_SDCAL_START GENMASK(15, 0)
> +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5 0x100
> +#define AIROHA_PCS_PMA_RX_RDY GENMASK(31, 16)
> +#define AIROHA_PCS_PMA_RX_BLWC_RDY_EN GENMASK(15, 0)
> +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6 0x104
> +#define AIROHA_PCS_PMA_RX_OS_END GENMASK(15, 0)
> +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c
> +#define AIROHA_PCS_PMA_DISB_RX_RDY BIT(24)
> +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114
> +#define AIROHA_PCS_PMA_FORCE_RX_RDY BIT(24)
> +#define AIROHA_PCS_PMA_PHY_EQ_CTRL_3 0x120
> +#define AIROHA_PCS_PMA_EQ_DEBUG_SEL GENMASK(17, 16)
> +#define AIROHA_PCS_PMA_FOM_NUM_ORDER GENMASK(12, 8)
> +#define AIROHA_PCS_PMA_A_SEL GENMASK(1, 0)
> +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1 0x14c
> +#define AIROHA_PCS_PMA_UNLOCK_CYCLECNT GENMASK(31, 16)
> +#define AIROHA_PCS_PMA_LOCK_CYCLECNT GENMASK(15, 0)
> +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2 0x150
> +#define AIROHA_PCS_PMA_LOCK_TARGET_END GENMASK(31, 16)
> +#define AIROHA_PCS_PMA_LOCK_TARGET_BEG GENMASK(15, 0)
> +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3 0x154
> +#define AIROHA_PCS_PMA_UNLOCK_TARGET_END GENMASK(31, 16)
> +#define AIROHA_PCS_PMA_UNLOCK_TARGET_BEG GENMASK(15, 0)
> +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4 0x158
> +#define AIROHA_PCS_PMA_LOCK_UNLOCKTH GENMASK(15, 12)
> +#define AIROHA_PCS_PMA_LOCK_LOCKTH GENMASK(11, 8)
> +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN GENMASK(2, 0)
> +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0)
> +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1)
> +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)
> +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)
> +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)
> +#define AIROHA_PCS_PMA_SS_RX_SIGDET_1 0x16c
> +#define AIROHA_PCS_PMA_SIGDET_EN BIT(0)
> +#define AIROHA_PCS_PMA_RX_FLL_1 0x174
> +#define AIROHA_PCS_PMA_LPATH_IDAC GENMASK(10, 0)
> +#define AIROHA_PCS_PMA_RX_FLL_2 0x178
> +#define AIROHA_PCS_PMA_CK_RATE GENMASK(18, 16)
> +#define AIROHA_PCS_PMA_CK_RATE_20 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0)
> +#define AIROHA_PCS_PMA_CK_RATE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1)
> +#define AIROHA_PCS_PMA_CK_RATE_5 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2)
> +#define AIROHA_PCS_PMA_RX_FLL_5 0x184
> +#define AIROHA_PCS_PMA_FLL_IDAC_MIN GENMASK(26, 16)
> +#define AIROHA_PCS_PMA_FLL_IDAC_MAX GENMASK(10, 0)
> +#define AIROHA_PCS_PMA_RX_FLL_B 0x19c
> +#define AIROHA_PCS_PMA_LOAD_EN BIT(0)
> +#define AIROHA_PCS_PMA_RX_RESET_1 0x208
> +#define AIROHA_PCS_PMA_SIGDET_RST_B BIT(8)
> +#define AIROHA_PCS_PMA_TX_RST_B 0x260
> +#define AIROHA_PCS_PMA_TXCALIB_RST_B BIT(8)
> +#define AIROHA_PCS_PMA_TX_TOP_RST_B BIT(0)
> +#define AIROHA_PCS_PMA_RX_DISB_MODE_4 0x320
> +#define AIROHA_PCS_PMA_DISB_BLWC_OFFSET BIT(24)
> +#define AIROHA_PCS_PMA_RX_FORCE_MODE_9 0x330
> +#define AIROHA_PCS_PMA_FORCE_FBCK_LOCK BIT(0)
> +#define AIROHA_PCS_PMA_RX_DISB_MODE_8 0x33c
> +#define AIROHA_PCS_PMA_DISB_FBCK_LOCK BIT(0)
> +#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0 0x38c
> +#define AIROHA_PCS_PMA_RX_SYS_EN_SEL GENMASK(1, 0)
> +#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0 0x390
> +#define AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT GENMASK(15, 0)
> +#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1 0x394
> +#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_END GENMASK(31, 16)
> +#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG GENMASK(15, 0)
> +#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3 0x39c
> +#define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH GENMASK(11, 8)
> +#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL 0x48c
> +#define AIROHA_PCS_PMA_DISB_LEQ BIT(0)
> +#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0 0x34c
> +#define AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB BIT(24)
> +#define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB BIT(16)
> +#define AIROHA_PCS_PMA_XPON_CDR_PW_PWDB BIT(8)
> +#define AIROHA_PCS_PMA_XPON_RX_FE_PWDB BIT(0)
> +#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1 0x350
> +#define AIROHA_PCS_PMA_RX_SIDGET_PWDB BIT(0)
> +#define AIROHA_PCS_PMA_DIG_RESERVE_0 0x360
> +#define AIROHA_PCS_PMA_DIG_RO_RESERVE_2 0x380
> +#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1 0x374
> +#define AIROHA_PCS_PMA_XPON_RX_RATE_CTRL GENMASK(1, 0)
> +#define AIROHA_PCS_PMA_SW_RST_SET 0x460
> +#define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N BIT(11)
> +#define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N BIT(10)
> +#define AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N BIT(9)
> +#define AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N BIT(8)
> +#define AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N BIT(7)
> +#define AIROHA_PCS_PMA_SW_TX_FIFO_RST_N BIT(6)
> +#define AIROHA_PCS_PMA_SW_REF_RST_N BIT(5)
> +#define AIROHA_PCS_PMA_SW_ALLPCS_RST_N BIT(4)
> +#define AIROHA_PCS_PMA_SW_PMA_RST_N BIT(3)
> +#define AIROHA_PCS_PMA_SW_TX_RST_N BIT(2)
> +#define AIROHA_PCS_PMA_SW_RX_RST_N BIT(1)
> +#define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N BIT(0)
> +#define AIROHA_PCS_PMA_XPON_INT_EN_3 0x474
> +#define AIROHA_PCS_PMA_RX_SIGDET_INT_EN BIT(16)
> +#define AIROHA_PCS_PMA_XPON_INT_STA_3 0x47c
> +#define AIROHA_PCS_PMA_RX_SIGDET_INT BIT(16)
> +#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL 0x48c
> +#define AIROHA_PCS_PMA_DISB_LEQ BIT(0)
> +#define AIROHA_PCS_PMA_RX_FREQDET 0x530
> +#define AIROHA_PCS_PMA_FL_OUT GENMASK(31, 16)
> +#define AIROHA_PCS_PMA_FBCK_LOCK BIT(0)
> +#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL 0x580
> +#define AIROHA_PCS_PMA_PON_TX_RATE_CTRL GENMASK(1, 0)
> +#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN 0x768
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PEAKING_CTRL BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL GENMASK(19, 16)
> +#define AIROHA_PCS_PMA_PXP_AEQ_SPEED 0x76c
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_OSR_SEL GENMASK(17, 16)
> +#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B 0x778
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 GENMASK(20, 16)
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B GENMASK(5, 0)
> +#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL 0x77c
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16)
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL GENMASK(2, 0)
> +#define AIROHA_PCS_PMA_PXP_TX_FIR_C1 0x780
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 GENMASK(20, 16)
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1 GENMASK(5, 0)
> +#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL 0x784
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0)
> +#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC 0x794
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)
> +#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC GENMASK(10, 0)
> +#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8)
> +#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW 0x798
> +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW GENMASK(30, 0)
> +#define AIROHA_PCS_PMA_PXP_RX_FE_VOS 0x79c
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16)
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_FE_VOS GENMASK(5, 0)
> +#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW 0x800
> +#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW GENMASK(30, 0)
> +#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS 0x80c
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON BIT(16)
> +#define AIROHA_PCS_PMA_PXP_AEQ_RSTB 0x814
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL BIT(16)
> +#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA 0x818
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB BIT(16)
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0)
> +#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB 0x81c
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16)
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0)
> +#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN 0x820
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16)
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0)
> +#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB 0x824
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB BIT(16)
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0)
> +#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN 0x828
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN BIT(16)
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)
> +#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B 0x84c
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B BIT(0)
> +#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN 0x854
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN BIT(16)
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)
> +#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN 0x874
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL BIT(16)
> +#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL 0x88c
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0)
> +#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB 0x894
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24)
> +#define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN BIT(16)
> +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)
> +#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB BIT(0)
> +
> +#define AIROHA_PCS_MAX_CALIBRATION_TRY 50
> +#define AIROHA_PCS_MAX_NUM_RSTS 2
> +
> +enum xfi_port_type {
> + AIROHA_PCS_ETH,
> + AIROHA_PCS_PON,
> +};
> +
> +struct airoha_pcs_match_data {
> + enum xfi_port_type port_type;
> +};
> +
> +struct airoha_pcs_priv {
> + struct device *dev;
> + const struct airoha_pcs_match_data *data;
> + phy_interface_t interface;
> +
> + struct regmap *scu;
> +
> + struct regmap *xfi_mac;
> + struct regmap *hsgmii_an;
> + struct regmap *hsgmii_pcs;
> + struct regmap *hsgmii_rate_adp;
> + struct regmap *multi_sgmii;
> + struct regmap *usxgmii_pcs;
> +
> + struct regmap *xfi_pma;
> + struct regmap *xfi_ana;
> +
> + struct reset_control_bulk_data rsts[AIROHA_PCS_MAX_NUM_RSTS];
> +
> + struct phylink_pcs pcs;
> +};
> +
> +static struct airoha_pcs_priv *phylink_pcs_to_airoha_pcs_port(struct phylink_pcs *pcs)
> +{
> + return container_of(pcs, struct airoha_pcs_priv, pcs);
> +}
> +
> +static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv,
> + phy_interface_t interface)
> +{
> + u32 xsi_sel;
> +
> + switch (interface) {
> + case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_1000BASEX:
> + case PHY_INTERFACE_MODE_2500BASEX:
> + xsi_sel = AIROHA_SCU_ETH_XSI_HSGMII;
> + break;
> + case PHY_INTERFACE_MODE_USXGMII:
> + case PHY_INTERFACE_MODE_10GBASER:
> + default:
> + xsi_sel = AIROHA_SCU_ETH_XSI_USXGMII;
> + }
> +
> + regmap_update_bits(priv->scu, AIROHA_SCU_SSR3,
> + AIROHA_SCU_ETH_XSI_SEL,
> + xsi_sel);
> +}
> +
> +static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv,
> + phy_interface_t interface)
> +{
> + u32 xsi_sel, wan_sel;
> +
> + switch (interface) {
> + case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_1000BASEX:
> + wan_sel = AIROHA_SCU_WAN_SEL_SGMII;
> + xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
> + break;
> + case PHY_INTERFACE_MODE_2500BASEX:
> + wan_sel = AIROHA_SCU_WAN_SEL_HSGMII;
> + xsi_sel = AIROHA_SCU_PON_XSI_HSGMII;
> + break;
> + case PHY_INTERFACE_MODE_USXGMII:
> + case PHY_INTERFACE_MODE_10GBASER:
> + default:
> + wan_sel = AIROHA_SCU_WAN_SEL_USXGMII;
> + xsi_sel = AIROHA_SCU_PON_XSI_USXGMII;
> + }
> +
> + regmap_update_bits(priv->scu, AIROHA_SCU_SSTR,
> + AIROHA_SCU_PON_XSI_SEL,
> + xsi_sel);
> +
> + regmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF,
> + AIROHA_SCU_WAN_SEL,
> + wan_sel);
> +}
> +
> +static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv,
> + phy_interface_t interface)
> +{
> + int ret;
> +
> + switch (priv->data->port_type) {
> + case AIROHA_PCS_ETH:
> + airoha_pcs_setup_scu_eth(priv, interface);
> + break;
> + case AIROHA_PCS_PON:
> + airoha_pcs_setup_scu_pon(priv, interface);
> + break;
> + }
> +
> + ret = reset_control_bulk_assert(ARRAY_SIZE(priv->rsts),
> + priv->rsts);
> + if (ret)
> + return ret;
> +
> + ret = reset_control_bulk_deassert(ARRAY_SIZE(priv->rsts),
> + priv->rsts);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv)
> +{
> + regmap_set_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
> + AIROHA_PCS_HSGMII_XFI_SEL);
> +
> + /* Disable Hibernation */
> + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1,
> + AIROHA_PCS_USXGMII_SPEED_SEL_H);
> +
> + /* FIXME: wait Airoha */
> + /* Avoid PCS sending garbage to MAC in some HW revision (E0) */
> + regmap_write(priv->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0);
> +}
> +
> +static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv)
> +{
> + regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
> + AIROHA_PCS_HSGMII_XFI_SEL);
> +
> + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
> + AIROHA_PCS_TBI_10B_MODE);
> +}
> +
> +static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv)
> +{
> + regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
> + AIROHA_PCS_HSGMII_XFI_SEL);
> +
> + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
> + AIROHA_PCS_TBI_10B_MODE);
> +
> + regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6,
> + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L,
> + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707));
> +
> + regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8,
> + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C,
> + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff));
> +}
> +
> +static void airoha_pcs_init(struct airoha_pcs_priv *priv,
> + phy_interface_t interface)
> +{
> + switch (interface) {
> + case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_1000BASEX:
> + airoha_pcs_init_sgmii(priv);
> + break;
> + case PHY_INTERFACE_MODE_2500BASEX:
> + airoha_pcs_init_hsgmii(priv);
> + break;
> + case PHY_INTERFACE_MODE_USXGMII:
> + case PHY_INTERFACE_MODE_10GBASER:
> + airoha_pcs_init_usxgmii(priv);
> + break;
> + default:
> + return;
> + }
> +}
> +
> +static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv)
> +{
> + /* Disable every interrupt */
> + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
> + AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT |
> + AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT |
> + AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT |
> + AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT |
> + AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT);
> +
> + /* Clear interrupt */
> + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
> + AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
> + AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
> + AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
> + AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
> + AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
> +
> + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
> + AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
> + AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
> + AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
> + AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
> + AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
> +}
> +
> +static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv)
> +{
> + /* Disable every Interrupt */
> + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0,
> + AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN |
> + AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN |
> + AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN |
> + AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN);
> +
> + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1,
> + AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN |
> + AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN |
> + AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN |
> + AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN);
> +
> + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2,
> + AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN |
> + AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN |
> + AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN |
> + AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN);
> +
> + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3,
> + AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN |
> + AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN |
> + AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN |
> + AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN);
> +
> + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4,
> + AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN);
> +
> + /* Clear any pending interrupt */
> + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2,
> + AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT |
> + AIROHA_PCS_USXGMII_R_TYPE_E_INT |
> + AIROHA_PCS_USXGMII_R_TYPE_T_INT |
> + AIROHA_PCS_USXGMII_R_TYPE_D_INT);
> +
> + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3,
> + AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT |
> + AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT |
> + AIROHA_PCS_USXGMII_LINK_UP_ST_INT |
> + AIROHA_PCS_USXGMII_HI_BER_ST_INT);
> +
> + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4,
> + AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT);
> +
> + /* Interrupt saddly seems to be not weel supported for Link Down.
> + * PCS Poll is a must to correctly read and react on Cable Deatch
> + * as only cable attach interrupt are fired and Link Down interrupt
> + * are fired only in special case like AN restart.
> + */
> +}
> +
> +static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv,
> + phy_interface_t interface)
> +{
> + switch (interface) {
> + case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_1000BASEX:
> + case PHY_INTERFACE_MODE_2500BASEX:
> + return airoha_pcs_interrupt_init_sgmii(priv);
> + case PHY_INTERFACE_MODE_USXGMII:
> + case PHY_INTERFACE_MODE_10GBASER:
> + return airoha_pcs_interrupt_init_usxgmii(priv);
> + default:
> + return;
> + }
> +}
> +
> +static void airoha_pcs_jcpll_bringup(struct airoha_pcs_priv *priv,
> + phy_interface_t interface)
> +{
> + u32 kband_vref;
> +
> + switch (interface) {
> + case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_1000BASEX:
> + case PHY_INTERFACE_MODE_2500BASEX:
> + kband_vref = 0x10;
> + break;
> + case PHY_INTERFACE_MODE_USXGMII:
> + case PHY_INTERFACE_MODE_10GBASER:
> + kband_vref = 0xf;
> + break;
> + default:
> + return;
> + }
> +
> + /* Setup LDO */
> + usleep_range(200, 300);
> +
> + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H,
> + AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO);
> +
> + /* Setup RSTB */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
> + AIROHA_PCS_ANA_JCPLL_RST_DLY,
> + AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200);
> +
> + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
> + AIROHA_PCS_ANA_JCPLL_PLL_RSTB);
> +
> + /* Enable PLL force selection and Force Disable */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN |
> + AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN);
> +
> + /* Setup SDM */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY,
> + AIROHA_PCS_ANA_JCPLL_SDM_DI_LS |
> + AIROHA_PCS_ANA_JCPLL_SDM_DI_EN,
> + AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23);
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM,
> + AIROHA_PCS_ANA_JCPLL_SDM_OUT |
> + AIROHA_PCS_ANA_JCPLL_SDM_ORD |
> + AIROHA_PCS_ANA_JCPLL_SDM_MODE |
> + AIROHA_PCS_ANA_JCPLL_SDM_IFM,
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0) |
> + AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM |
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_MODE, 0x0));
> +
> + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN,
> + AIROHA_PCS_ANA_JCPLL_SDM_HREN);
> +
> + /* Setup SSC */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA,
> + AIROHA_PCS_ANA_JCPLL_SSC_PERIOD |
> + AIROHA_PCS_ANA_JCPLL_SSC_DELTA,
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_PERIOD, 0x0) |
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA, 0x0));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN,
> + AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 |
> + AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN,
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA1, 0x0));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR,
> + AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI |
> + AIROHA_PCS_ANA_JCPLL_SSC_EN |
> + AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L |
> + AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR,
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) |
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x0));
> +
> + /* Setup LPF */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN,
> + AIROHA_PCS_ANA_JCPLL_CHP_IOFST |
> + AIROHA_PCS_ANA_JCPLL_CHP_IBIAS |
> + AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN,
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IOFST, 0x0) |
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IBIAS, 0x18));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR,
> + AIROHA_PCS_ANA_JCPLL_LPF_BWR |
> + AIROHA_PCS_ANA_JCPLL_LPF_BP |
> + AIROHA_PCS_ANA_JCPLL_LPF_BC |
> + AIROHA_PCS_ANA_JCPLL_LPF_BR,
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWR, 0x0) |
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BP, 0x10) |
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BC, 0x1f) |
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BR, BIT(3) | BIT(1)));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC,
> + AIROHA_PCS_ANA_JCPLL_LPF_BWC,
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWC, 0x0));
> +
> + /* Setup VCO */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV,
> + AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR |
> + AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN |
> + AIROHA_PCS_ANA_JCPLL_VCO_CFIX,
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR, 0x4) |
> + AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN |
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_CFIX, 0x1));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR,
> + AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L |
> + AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H |
> + AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR,
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) |
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H, 0x3) |
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x3));
> +
> + /* Setup PCW */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW,
> + AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW,
> + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000));
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW);
> +
> + /* Setup DIV */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE,
> + AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 |
> + AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE,
> + AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2);
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV,
> + AIROHA_PCS_ANA_JCPLL_VCODIV,
> + AIROHA_PCS_ANA_JCPLL_VCODIV_1);
> +
> + /* Setup KBand */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC,
> + AIROHA_PCS_ANA_JCPLL_KBAND_KS |
> + AIROHA_PCS_ANA_JCPLL_KBAND_KF |
> + AIROHA_PCS_ANA_JCPLL_KBAND_KFC,
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KS, 0x0) |
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KF, 0x3) |
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KFC, 0x0));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC,
> + AIROHA_PCS_ANA_JCPLL_KBAND_DIV |
> + AIROHA_PCS_ANA_JCPLL_KBAND_CODE |
> + AIROHA_PCS_ANA_JCPLL_KBAND_OPTION,
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_DIV, 0x2) |
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_CODE, 0xe4));
> +
> + /* Setup TCL */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H,
> + AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF,
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF, kband_vref));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN,
> + AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF |
> + AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN |
> + AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN,
> + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF, 0x5) |
> + AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 |
> + AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN);
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN,
> + AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW |
> + AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN,
> + AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 |
> + AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN);
> +
> + /* Enable PLL */
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
> + AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN);
> +
> + /* Enale PLL Output */
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN |
> + AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN);
> +}
> +
> +static void airoha_pcs_txpll_bringup(struct airoha_pcs_priv *priv,
> + phy_interface_t interface)
> +{
> + u32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc;
> + u32 vco_cfix;
> + u32 pcw;
> + u32 tcl_amp_vref;
> + bool sdm_hren;
> + bool vcodiv;
> +
> + switch (interface) {
> + case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_1000BASEX:
> + lpf_chp_ibias = 0xf;
> + lpf_bp = BIT(1);
> + lpf_bwr = BIT(3) | BIT(1) | BIT(0);
> + lpf_bwc = BIT(4) | BIT(3);
> + vco_cfix = BIT(1) | BIT(0);
> + pcw = BIT(27);
> + tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
> + vcodiv = false;
> + sdm_hren = false;
> + break;
> + case PHY_INTERFACE_MODE_2500BASEX:
> + lpf_chp_ibias = 0xa;
> + lpf_bp = BIT(2) | BIT(0);
> + lpf_bwr = 0;
> + lpf_bwc = 0;
> + vco_cfix = 0;
> + pcw = BIT(27) | BIT(25);
> + tcl_amp_vref = BIT(3) | BIT(2) | BIT(0);
> + vcodiv = true;
> + sdm_hren = false;
> + break;
> + case PHY_INTERFACE_MODE_USXGMII:
> + case PHY_INTERFACE_MODE_10GBASER:
> + lpf_chp_ibias = 0xf;
> + lpf_bp = BIT(1);
> + lpf_bwr = BIT(3) | BIT(1) | BIT(0);
> + lpf_bwc = BIT(4) | BIT(3);
> + vco_cfix = BIT(0);
> + pcw = BIT(27) | BIT(22);
> + tcl_amp_vref = BIT(3) | BIT(1) | BIT(0);
> + vcodiv = false;
> + sdm_hren = true;
> + break;
> + default:
> + return;
> + }
> +
> + /* Setup VCO LDO Output */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,
> + AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT |
> + AIROHA_PCS_ANA_TXPLL_LDO_OUT,
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT, 0x1) |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_OUT, 0x1));
> +
> + /* Setup RSTB */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL,
> + AIROHA_PCS_ANA_TXPLL_PLL_RSTB |
> + AIROHA_PCS_ANA_TXPLL_RST_DLY |
> + AIROHA_PCS_ANA_TXPLL_REFIN_DIV |
> + AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL,
> + AIROHA_PCS_ANA_TXPLL_PLL_RSTB |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_RST_DLY, 0x4) |
> + AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 |
> + AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL);
> +
> + /* Enable PLL force selection and Force Disable */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN |
> + AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN);
> +
> + /* Setup SDM */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN,
> + AIROHA_PCS_ANA_TXPLL_SDM_MODE |
> + AIROHA_PCS_ANA_TXPLL_SDM_IFM |
> + AIROHA_PCS_ANA_TXPLL_SDM_DI_LS |
> + AIROHA_PCS_ANA_TXPLL_SDM_DI_EN,
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SDM_MODE, 0) |
> + AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23);
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,
> + AIROHA_PCS_ANA_TXPLL_SDM_HREN |
> + AIROHA_PCS_ANA_TXPLL_SDM_OUT |
> + AIROHA_PCS_ANA_TXPLL_SDM_ORD,
> + (sdm_hren ? AIROHA_PCS_ANA_TXPLL_SDM_HREN : 0) |
> + AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM);
> +
> + /* Setup SSC */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1,
> + AIROHA_PCS_ANA_TXPLL_SSC_DELTA |
> + AIROHA_PCS_ANA_TXPLL_SSC_DELTA1,
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA, 0x0) |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA1, 0x0));
> +
> + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN,
> + AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN |
> + AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI |
> + AIROHA_PCS_ANA_TXPLL_SSC_EN);
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD,
> + AIROHA_PCS_ANA_TXPLL_SSC_PERIOD,
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_PERIOD, 0x0));
> +
> + /* Setup LPF */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS,
> + AIROHA_PCS_ANA_TXPLL_LPF_BC |
> + AIROHA_PCS_ANA_TXPLL_LPF_BR |
> + AIROHA_PCS_ANA_TXPLL_CHP_IOFST |
> + AIROHA_PCS_ANA_TXPLL_CHP_IBIAS,
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BC, 0x1f) |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BR, 0x5) |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IOFST, 0x0) |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IBIAS, lpf_chp_ibias));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,
> + AIROHA_PCS_ANA_TXPLL_LPF_BWC |
> + AIROHA_PCS_ANA_TXPLL_LPF_BWR |
> + AIROHA_PCS_ANA_TXPLL_LPF_BP,
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWC, lpf_bwc) |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWR, lpf_bwr) |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BP, lpf_bp));
> +
> + /* Setup VCO */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
> + AIROHA_PCS_ANA_TXPLL_VCO_CFIX,
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_CFIX, vco_cfix));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN,
> + AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L |
> + AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H |
> + AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR |
> + AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR |
> + AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN,
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L, 0x0) |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H, 0x4) |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR, 0x4) |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR, 0x7) |
> + AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN);
> +
> + /* Setup PCW */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW,
> + AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW);
> +
> + /* Setup KBand */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE,
> + AIROHA_PCS_ANA_TXPLL_KBAND_KF |
> + AIROHA_PCS_ANA_TXPLL_KBAND_KFC |
> + AIROHA_PCS_ANA_TXPLL_KBAND_DIV |
> + AIROHA_PCS_ANA_TXPLL_KBAND_CODE,
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KF, 0x3) |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KFC, 0x0) |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_DIV, 0x4) |
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_CODE, 0xe4));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,
> + AIROHA_PCS_ANA_TXPLL_KBAND_KS,
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KS, 0x1));
> +
> + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP,
> + AIROHA_PCS_ANA_TXPLL_KBAND_OPTION);
> +
> + /* Setup DIV */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS,
> + AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE |
> + AIROHA_PCS_ANA_TXPLL_POSTDIV_EN,
> + AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2);
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
> + AIROHA_PCS_ANA_TXPLL_VCODIV,
> + vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 :
> + AIROHA_PCS_ANA_TXPLL_VCODIV_1);
> +
> + /* Setup TCL */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF,
> + AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF,
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF, 0xf));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN,
> + AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF |
> + AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN,
> + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF, tcl_amp_vref) |
> + AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4);
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN,
> + AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW |
> + AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN,
> + AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 |
> + AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN);
> +
> + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD,
> + AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN);
> +
> + /* Enable PLL */
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
> + AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN);
> +
> + /* Enale PLL Output */
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN |
> + AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN);
> +}
> +
> +static void airoha_pcs_pll_bringup(struct airoha_pcs_priv *priv,
> + phy_interface_t interface)
> +{
> + airoha_pcs_jcpll_bringup(priv, interface);
> +
> + usleep_range(200, 300);
> +
> + airoha_pcs_txpll_bringup(priv, interface);
> +
> + usleep_range(200, 300);
> +}
> +
> +static void airoha_pcs_tx_bringup(struct airoha_pcs_priv *priv,
> + phy_interface_t interface)
> +{
> + u32 tx_rate_ctrl;
> + u32 ckin_divisor;
> + u32 fir_cn1, fir_c0b, fir_c1;
> +
> + switch (interface) {
> + case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_1000BASEX:
> + ckin_divisor = BIT(1);
> + tx_rate_ctrl = BIT(0);
> + fir_cn1 = 0;
> + fir_c0b = 12;
> + fir_c1 = 0;
> + break;
> + case PHY_INTERFACE_MODE_2500BASEX:
> + ckin_divisor = BIT(2);
> + tx_rate_ctrl = BIT(0);
> + fir_cn1 = 0;
> + fir_c0b = 11;
> + fir_c1 = 1;
> + break;
> + case PHY_INTERFACE_MODE_USXGMII:
> + case PHY_INTERFACE_MODE_10GBASER:
> + ckin_divisor = BIT(2) | BIT(0);
> + tx_rate_ctrl = BIT(1);
> + fir_cn1 = 1;
> + fir_c0b = 1;
> + fir_c1 = 11;
> + break;
> + default:
> + return;
> + }
> +
> + /* Set TX rate ctrl */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL,
> + AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
> + FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL,
> + tx_rate_ctrl));
> +
> + /* Setup TX Config */
> + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TX_CKLDO_EN,
> + AIROHA_PCS_ANA_TX_DMEDGEGEN_EN |
> + AIROHA_PCS_ANA_TX_CKLDO_EN);
> +
> + udelay(1);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL |
> + AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL);
> +
> + /* FIXME: Ask Airoha TX term is OK to reset? */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
> + AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR |
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL |
> + AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR |
> + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR,
> + ckin_divisor) |
> + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL, 0x0));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
> + AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL |
> + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL,
> + tx_rate_ctrl));
> +
> + /* Setup TX FIR Load Parameters (Reference 660mV) */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
> + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 |
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
> + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 |
> + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) |
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B |
> + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 |
> + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 |
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
> + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 |
> + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1));
> +
> + /* Reset TX Bar */
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_TX_RST_B,
> + AIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B);
> +}
> +
> +static void airoha_pcs_rx_bringup(struct airoha_pcs_priv *priv,
> + phy_interface_t interface)
> +{
> + u32 rx_rate_ctrl;
> + u32 osr;
> + u32 pr_cdr_beta_dac;
> + u32 cdr_pr_buf_in_sr;
> + bool cdr_pr_cap_en;
> + u32 sigdet_vth_sel;
> + u32 phyck_div, phyck_sel;
> +
> + switch (interface) {
> + case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_1000BASEX:
> + osr = BIT(1) | BIT(0); /* 1.25G */
> + pr_cdr_beta_dac = BIT(3);
> + rx_rate_ctrl = 0;
> + cdr_pr_cap_en = false;
> + cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
> + sigdet_vth_sel = BIT(2) | BIT(1);
> + phyck_div = BIT(5) | BIT(3) | BIT(0);
> + phyck_sel = BIT(0);
> + break;
> + case PHY_INTERFACE_MODE_2500BASEX:
> + osr = BIT(0); /* 2.5G */
> + pr_cdr_beta_dac = BIT(2) | BIT(1);
> + rx_rate_ctrl = 0;
> + cdr_pr_cap_en = true;
> + cdr_pr_buf_in_sr = BIT(2) | BIT(1);
> + sigdet_vth_sel = BIT(2) | BIT(1);
> + phyck_div = BIT(3) | BIT(1) | BIT(0);
> + phyck_sel = BIT(0);
> + break;
> + case PHY_INTERFACE_MODE_USXGMII:
> + case PHY_INTERFACE_MODE_10GBASER:
> + osr = 0; /* 10G */
> + cdr_pr_cap_en = false;
> + pr_cdr_beta_dac = BIT(3);
> + rx_rate_ctrl = BIT(1);
> + cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0);
> + sigdet_vth_sel = BIT(1);
> + phyck_div = BIT(6) | BIT(1);
> + phyck_sel = BIT(1);
> + break;
> + default:
> + return;
> + }
> +
> + /* Set RX rate ctrl */
> + if (interface == PHY_INTERFACE_MODE_2500BASEX)
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_2,
> + AIROHA_PCS_PMA_CK_RATE,
> + AIROHA_PCS_PMA_CK_RATE_10);
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1,
> + AIROHA_PCS_PMA_XPON_RX_RATE_CTRL,
> + FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL, rx_rate_ctrl));
> +
> + /* Setup RX Path */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_5,
> + AIROHA_PCS_PMA_FLL_IDAC_MIN |
> + AIROHA_PCS_PMA_FLL_IDAC_MAX,
> + FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) |
> + FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff));
> +
> + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ,
> + AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ |
> + AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ |
> + AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ |
> + AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ);
> +
> + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB,
> + AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ);
> +
> + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB,
> + AIROHA_PCS_ANA_FE_VCM_GEN_PWDB);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1,
> + AIROHA_PCS_PMA_LCPLL_MAN_PWDB);
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_AEQ_CFORCE,
> + AIROHA_PCS_ANA_AEQ_OFORCE,
> + AIROHA_PCS_ANA_AEQ_OFORCE_CTLE);
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW,
> + AIROHA_PCS_ANA_RX_OSCAL_FORCE,
> + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS |
> + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS |
> + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS |
> + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS |
> + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS |
> + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS |
> + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS |
> + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS |
> + AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH |
> + AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS);
> +
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4,
> + AIROHA_PCS_PMA_DISB_BLWC_OFFSET);
> +
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL,
> + AIROHA_PCS_PMA_DISB_LEQ);
> +
> + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV,
> + AIROHA_PCS_ANA_CDR_PD_EDGE_DIS |
> + AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV);
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON |
> + AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL |
> + AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL);
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,
> + AIROHA_PCS_ANA_RX_DAC_MON |
> + AIROHA_PCS_ANA_CDR_PR_XFICK_EN |
> + AIROHA_PCS_ANA_CDR_PR_MONDPI_EN |
> + AIROHA_PCS_ANA_CDR_PR_MONDPR_EN,
> + FIELD_PREP(AIROHA_PCS_ANA_RX_DAC_MON, 0x0) |
> + AIROHA_PCS_ANA_CDR_PR_XFICK_EN);
> +
> + /* Setup FE Gain and FE Peacking */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL |
> + AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL,
> + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PEAKING_CTRL |
> + AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL,
> + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_PEAKING_CTRL, 0x0));
> +
> + /* Setup FE VOS */
> + if (interface != PHY_INTERFACE_MODE_USXGMII &&
> + interface != PHY_INTERFACE_MODE_10GBASER)
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
> + AIROHA_PCS_PMA_FORCE_DA_FE_VOS,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS |
> + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0));
> +
> + /* Setup FLL PR FMeter (no bypass mode)*/
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0,
> + AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT,
> + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1,
> + AIROHA_PCS_PMA_PLL_LOCK_TARGET_END |
> + AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG,
> + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) |
> + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3,
> + AIROHA_PCS_PMA_PLL_LOCK_LOCKTH,
> + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1));
> +
> + /* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */
> + /* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */
> + /* Setup REV */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_REV_0,
> + AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL |
> + AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL |
> + AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK,
> + FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL, BIT(2)) |
> + FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL, BIT(2)) |
> + FIELD_PREP(AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK, 0x0));
> +
> + /* Setup Rdy Timeout */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5,
> + AIROHA_PCS_PMA_RX_RDY |
> + AIROHA_PCS_PMA_RX_BLWC_RDY_EN,
> + FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) |
> + FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5));
> +
> + /* Setup CaBoundry Init */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0,
> + AIROHA_PCS_PMA_RX_OS_START |
> + AIROHA_PCS_PMA_OSC_SPEED_OPT,
> + FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) |
> + AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1);
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6,
> + AIROHA_PCS_PMA_RX_OS_END,
> + FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1,
> + AIROHA_PCS_PMA_RX_PICAL_END |
> + AIROHA_PCS_PMA_RX_PICAL_START,
> + FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) |
> + FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4,
> + AIROHA_PCS_PMA_RX_SDCAL_END |
> + AIROHA_PCS_PMA_RX_SDCAL_START,
> + FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) |
> + FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2,
> + AIROHA_PCS_PMA_RX_PDOS_END |
> + AIROHA_PCS_PMA_RX_PDOS_START,
> + FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) |
> + FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3,
> + AIROHA_PCS_PMA_RX_FEOS_END |
> + AIROHA_PCS_PMA_RX_FEOS_START,
> + FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) |
> + FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2));
> +
> + /* Setup By Serdes*/
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
> + AIROHA_PCS_PMA_FORCE_DA_OSR_SEL,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL |
> + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr));
> +
> + /* Setup RX OSR */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV,
> + AIROHA_PCS_ANA_CDR_PD_EDGE_DIS,
> + osr ? AIROHA_PCS_ANA_CDR_PD_EDGE_DIS : 0);
> +
> + /* Setup CDR LPF Ratio */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO,
> + AIROHA_PCS_ANA_CDR_LPF_TOP_LIM |
> + AIROHA_PCS_ANA_CDR_LPF_RATIO,
> + FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_TOP_LIM, 0x20000) |
> + FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_RATIO, osr));
> +
> + /* Setup CDR PR */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC,
> + AIROHA_PCS_ANA_CDR_PR_KBAND_DIV |
> + AIROHA_PCS_ANA_CDR_PR_BETA_SEL |
> + AIROHA_PCS_ANA_CDR_PR_VCOADC_OS |
> + AIROHA_PCS_ANA_CDR_PR_BETA_DAC,
> + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_KBAND_DIV, 0x4) |
> + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_SEL, 0x1) |
> + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VCOADC_OS, 0x8) |
> + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_DAC, pr_cdr_beta_dac));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL,
> + AIROHA_PCS_ANA_CDR_PR_FBKSEL |
> + AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND |
> + AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL |
> + AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL,
> + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_FBKSEL, 0x0) |
> + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_DAC_BAND, pr_cdr_beta_dac) |
> + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL, 0x6) |
> + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL, 0x6));
> +
> + /* Setup Eye Mon */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_3,
> + AIROHA_PCS_PMA_EQ_DEBUG_SEL |
> + AIROHA_PCS_PMA_FOM_NUM_ORDER |
> + AIROHA_PCS_PMA_A_SEL,
> + FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) |
> + FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) |
> + FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2,
> + AIROHA_PCS_PMA_DATA_SHIFT |
> + AIROHA_PCS_PMA_EYECNT_FAST,
> + AIROHA_PCS_PMA_EYECNT_FAST);
> +
> + /* Calibration Start */
> +
> + /* Enable SYS */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0,
> + AIROHA_PCS_PMA_RX_SYS_EN_SEL,
> + FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1));
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0,
> + AIROHA_PCS_PMA_SW_LCPLL_EN);
> +
> + usleep_range(500, 600);
> +
> + /* Setup FLL PR FMeter (bypass mode)*/
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8,
> + AIROHA_PCS_PMA_DISB_FBCK_LOCK);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9,
> + AIROHA_PCS_PMA_FORCE_FBCK_LOCK);
> +
> + /* Enable CMLEQ */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN,
> + AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |
> + AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |
> + AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN |
> + AIROHA_PCS_ANA_RX_FE_EQ_HZEN,
> + AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN |
> + AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN |
> + AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN);
> +
> + /* Setup CDR PR */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN,
> + AIROHA_PCS_ANA_CDR_PR_CAP_EN |
> + AIROHA_PCS_ANA_CDR_BUF_IN_SR,
> + (cdr_pr_cap_en ? AIROHA_PCS_ANA_CDR_PR_CAP_EN : 0) |
> + FIELD_PREP(AIROHA_PCS_ANA_CDR_BUF_IN_SR, cdr_pr_buf_in_sr));
> +
> + /* Setup CDR xxx Pwdb, set force and disable */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB |
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB |
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB);
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB |
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB |
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB |
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB);
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN |
> + AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN |
> + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB |
> + AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB);
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB |
> + AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB |
> + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B |
> + AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB);
> +
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
> + AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB |
> + AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
> + AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
> + AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
> +
> + /* FIXME: Ask Airoha WHY it's cleared? */
> + /* regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
> + * AIROHA_PCS_ANA_RX_FE_50OHMS_SEL);
> + */
> +
> + /* Setup SigDet */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH,
> + AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL |
> + AIROHA_PCS_ANA_RX_SIGDET_PEAK,
> + FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL, sigdet_vth_sel) |
> + FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_PEAK, BIT(1)));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_RANGE,
> + AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL,
> + FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL, BIT(1) | BIT(0)));
> +
> + /* Disable SigDet Pwdb */
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
> + AIROHA_PCS_PMA_RX_SIDGET_PWDB);
> +
> + /* Setup PHYCK */
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV,
> + AIROHA_PCS_ANA_RX_TDC_CK_SEL |
> + AIROHA_PCS_ANA_RX_PHYCK_RSTB |
> + AIROHA_PCS_ANA_RX_PHYCK_SEL |
> + AIROHA_PCS_ANA_RX_PHYCK_DIV,
> + AIROHA_PCS_ANA_RX_PHYCK_RSTB |
> + FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_SEL, phyck_sel) |
> + FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_DIV, phyck_div));
> +
> + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL,
> + AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE |
> + AIROHA_PCS_ANA_RX_PHY_CK_SEL,
> + AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE);
> +
> + usleep_range(100, 200);
> +
> + /* Enable CDR xxx Pwdb */
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB |
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB,
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB,
> + AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B,
> + AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0,
> + AIROHA_PCS_PMA_XPON_CDR_PR_PD_PWDB |
> + AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB |
> + AIROHA_PCS_PMA_XPON_CDR_PW_PWDB |
> + AIROHA_PCS_PMA_XPON_RX_FE_PWDB);
> +
> + /* Enable SigDet Pwdb */
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1,
> + AIROHA_PCS_PMA_RX_SIDGET_PWDB);
> +}
> +
> +static unsigned int airoha_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv,
> + u32 cdr_pr_idac)
> +{
> + u32 val;
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
> + AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
> + FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC,
> + cdr_pr_idac));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
> + AIROHA_PCS_PMA_FREQLOCK_DET_EN,
> + AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0);
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
> + AIROHA_PCS_PMA_FREQLOCK_DET_EN,
> + AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL);
> +
> + usleep_range(5000, 7000);
> +
> + regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
> +
> + return FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val);
> +}
> +
> +static void airoha_pcs_rx_prcal(struct airoha_pcs_priv *priv,
> + phy_interface_t interface)
> +{
> + unsigned int remaining_prcal_search_bits = 8;
> + unsigned int prcal_search_bit;
> + bool prcal_search_from_bottom;
> + unsigned int prcal_search;
> + unsigned int fl_out_diff = UINT_MAX;
> + unsigned int fl_out;
> + int cdr_pr_idac = 0;
> +
> + u32 target_fl_out;
> + u32 cyclecnt;
> +
> + switch (interface) {
> + case PHY_INTERFACE_MODE_SGMII: /* DS_1.25G / US_1.25G */
> + case PHY_INTERFACE_MODE_1000BASEX:
> + target_fl_out = 0xa3d6;
> + cyclecnt = 32767;
> + break;
> + case PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G / US_9.95328G */
> + target_fl_out = 0xa000;
> + cyclecnt = 20000;
> + break;
> + case PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G / US_1.25G */
> + case PHY_INTERFACE_MODE_10GBASER:
> + target_fl_out = 0x9edf;
> + cyclecnt = 32767;
> + break;
> + default:
> + return;
> + }
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
> + AIROHA_PCS_PMA_SW_REF_RST_N);
> +
> + usleep_range(100, 200);
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2,
> + AIROHA_PCS_PMA_LOCK_TARGET_END |
> + AIROHA_PCS_PMA_LOCK_TARGET_BEG,
> + FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) |
> + FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1,
> + AIROHA_PCS_PMA_UNLOCK_CYCLECNT |
> + AIROHA_PCS_PMA_LOCK_CYCLECNT,
> + FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) |
> + FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4,
> + AIROHA_PCS_PMA_LOCK_UNLOCKTH |
> + AIROHA_PCS_PMA_LOCK_LOCKTH,
> + FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) |
> + FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3));
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3,
> + AIROHA_PCS_PMA_UNLOCK_TARGET_END |
> + AIROHA_PCS_PMA_UNLOCK_TARGET_BEG,
> + FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) |
> + FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100));
> +
> + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE,
> + AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF);
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN |
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN |
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN |
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
> +
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
> +
> + /* Calibration logic:
> + * First check the major value by looping with every
> + * value in the last 3 bit of CDR_PR_IDAC.
> + * Get the signal level and save the value that if closer to
> + * the target.
> + *
> + * Then fine tune for the remaining 7 bit to find the one that
> + * produce the closest signal level.
> + */
> + for (prcal_search = 0; prcal_search < 8 ; prcal_search++) {
> + u32 cdr_pr_idac_tmp;
> +
> + /* try to find the upper value by setting the last 3 bit */
> + cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR,
> + prcal_search);
> + fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);
> +
> + /* Use absolute values to find the closest one to target */
> + if (abs(fl_out - target_fl_out) < fl_out_diff) {
> + cdr_pr_idac = cdr_pr_idac_tmp;
> + fl_out_diff = abs(fl_out - target_fl_out);
> + }
> + }
> +
> + /* Understand if we need to fine tune by increasing or decreasing fl_out.
> + * This is done by setting BIT (7) and check if the abs fl_out diff from target
> + * increase or decrease.
> + * If it does increase, we need to decrease fl_out, hence we search from MAX to MIN.
> + * If it does decrease, we need to increase fl_out, hence we search from MIN to MAX.
> + */
> + fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac | BIT(7));
> + if (abs(fl_out - target_fl_out) < fl_out_diff) {
> + prcal_search_from_bottom = false;
> + prcal_search_bit = 7;
> + } else {
> + prcal_search_from_bottom = true;
> + prcal_search_bit = 0;
> + }
> +
> + /* Fine tune part.
> + * Continue searching until we find a deadline where the signal
> + * level starts to increase/decrease. Once that is reached, start
> + * the loop again to progressely find a closer signal level to
> + * the target.
> + */
> + while (remaining_prcal_search_bits) {
> + unsigned int fl_out_diff_new;
> + u32 cdr_pr_idac_tmp;
> +
> + cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit);
> + fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp);
> +
> + /* Use absolute values to find the closest one to target */
> + fl_out_diff_new = abs(fl_out - target_fl_out);
> + /* Assume we found the deadline when the new absolue signal difference
> + * from target is greater than the previous and the difference is at
> + * least 10% greater between the old and new value.
> + * This is to account for signal detection level tollerance making
> + * sure we are actually over a deadline (AKA we are getting farther
> + * from target)
> + */
> + if (fl_out_diff_new > fl_out_diff &&
> + (abs(fl_out_diff_new - fl_out_diff) * 100) / fl_out_diff > 10) {
> + /* Exit early if we are already at the deadline */
> + if (prcal_search_bit == 0 || prcal_search_bit == 7)
> + break;
> +
> + /* We found the deadline, set the value to the previous
> + * bit, and reset the loop to fine tune with the
> + * remaining values.
> + */
> + if (prcal_search_from_bottom) {
> + cdr_pr_idac |= BIT(prcal_search_bit - 1);
> + remaining_prcal_search_bits = prcal_search_bit - 1;
> + prcal_search_bit = 0;
> + } else {
> + cdr_pr_idac |= BIT(prcal_search_bit + 1);
> + remaining_prcal_search_bits = prcal_search_bit + 1;
> + }
> + } else {
> + /* Update the signal level diff and try the next bit */
> + fl_out_diff = fl_out_diff_new;
> +
> + /* If we didn't found the deadline, set the last bit
> + * and stop searching. This should not happen as it's expected
> + * we find an high signal level and we decrease it as it's
> + * much harder to reach target level by increasing the
> + * signal (by using a lower DAC value).
> + */
> + if (prcal_search_from_bottom) {
> + if (prcal_search_bit == 7) {
> + cdr_pr_idac |= BIT(prcal_search_bit);
> + break;
> + }
> +
> + prcal_search_bit++;
> + } else {
> + if (prcal_search_bit == 0) {
> + cdr_pr_idac |= BIT(prcal_search_bit);
> + break;
> + }
> +
> + prcal_search_bit--;
> + }
> + }
> + }
> +
> + fl_out = airoha_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac);
> + dev_dbg(priv->dev, "Selected CDR Pr Idac: %x Fl Out: %x\n", cdr_pr_idac, fl_out);
> + if (abs(fl_out - target_fl_out) > 100)
> + dev_warn(priv->dev, "Fl Out is %d far from target %d. PCS might not function properly.\n",
> + abs(fl_out - target_fl_out), target_fl_out);
> +
> + /* Setup Load Band */
> + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE,
> + AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF);
> +
> + /* Disable force of LPF C previously enabled */
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN);
> +
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_B,
> + AIROHA_PCS_PMA_LOAD_EN);
> +
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_1,
> + AIROHA_PCS_PMA_LPATH_IDAC,
> + FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac));
> +
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
> + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB);
> +
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB);
> +
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
> + AIROHA_PCS_PMA_SW_REF_RST_N);
> +
> + usleep_range(100, 200);
> +}
> +
> +/* This is used to both calibrate and lock to signal (after a previous
> + * calibration) after a global reset.
> + */
> +static void airoha_pcs_cdr_reset(struct airoha_pcs_priv *priv,
> + phy_interface_t interface, bool calibrate)
> +{
> + /* Setup LPF L2D force and disable */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA |
> + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
> +
> + /* Calibrate IDAC and setup Load Band */
> + if (calibrate)
> + airoha_pcs_rx_prcal(priv, interface);
> +
> + /* Setup LPF RSTB force and disable */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB |
> + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
> +
> + usleep_range(700, 1000);
> +
> + /* Force Enable LPF RSTB */
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
> + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB);
> +
> + usleep_range(100, 200);
> +
> + /* Force Enable LPF L2D */
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
> + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA);
> +
> + /* Disable LPF RSTB force bit */
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB);
> +
> + /* Disable LPF L2D force bit */
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA,
> + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA);
> +}
> +
> +static int airoha_pcs_phya_bringup(struct airoha_pcs_priv *priv,
> + phy_interface_t interface)
> +{
> + int calibration_try = 0;
> + u32 val;
> +
> + airoha_pcs_tx_bringup(priv, interface);
> + airoha_pcs_rx_bringup(priv, interface);
> +
> + usleep_range(100, 200);
> +
> +retry_calibration:
> + airoha_pcs_cdr_reset(priv, interface, true);
> +
> + /* Global reset clear */
> + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
> + AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
> + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
> + AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N |
> + AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
> + AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
> + AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
> + AIROHA_PCS_PMA_SW_REF_RST_N |
> + AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
> + AIROHA_PCS_PMA_SW_PMA_RST_N |
> + AIROHA_PCS_PMA_SW_TX_RST_N |
> + AIROHA_PCS_PMA_SW_RX_RST_N |
> + AIROHA_PCS_PMA_SW_RX_FIFO_RST_N,
> + AIROHA_PCS_PMA_SW_REF_RST_N);
> +
> + usleep_range(100, 200);
> +
> + /* Global reset */
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
> + AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N |
> + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N |
> + AIROHA_PCS_PMA_SW_HSG_RXPCS_BIST_RST_N |
> + AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N |
> + AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N |
> + AIROHA_PCS_PMA_SW_TX_FIFO_RST_N |
> + AIROHA_PCS_PMA_SW_REF_RST_N |
> + AIROHA_PCS_PMA_SW_ALLPCS_RST_N |
> + AIROHA_PCS_PMA_SW_PMA_RST_N |
> + AIROHA_PCS_PMA_SW_TX_RST_N |
> + AIROHA_PCS_PMA_SW_RX_RST_N |
> + AIROHA_PCS_PMA_SW_RX_FIFO_RST_N);
> +
> + usleep_range(5000, 7000);
> +
> + airoha_pcs_cdr_reset(priv, interface, false);
> +
> + /* It was discovered that after a global reset and auto mode gets
> + * actually enabled, the fl_out from calibration might change and
> + * might deviates a lot from the expected value it was calibrated for.
> + * To correctly work, the PCS FreqDet module needs to Lock to the fl_out
> + * (frequency level output) or no signal can correctly be transmitted.
> + * This is detected by checking the FreqDet module Lock bit.
> + *
> + * If it's detected that the FreqDet module is not locked, retry
> + * calibration. From observation on real hardware with a 10g SFP module,
> + * it required a maximum of an additional calibration to actually make
> + * the FreqDet module to lock. Try 10 times before failing to handle
> + * really strange case.
> + */
> + regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val);
> + if (!(val & AIROHA_PCS_PMA_FBCK_LOCK)) {
> + if (calibration_try > AIROHA_PCS_MAX_CALIBRATION_TRY) {
> + dev_err(priv->dev, "No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\n",
> + AIROHA_PCS_MAX_CALIBRATION_TRY);
> + return -EIO;
> + }
> +
> + calibration_try++;
> +
> + dev_dbg(priv->dev, "No FBCK Lock from FreqDet module, retry calibration.\n");
> + goto retry_calibration;
> + }
> +
> + return 0;
> +}
> +
> +static void airoha_pcs_get_state_sgmii(struct airoha_pcs_priv *priv,
> + unsigned int neg_mode,
> + struct phylink_link_state *state)
> +{
> + u32 bmsr, lpa;
> +
> + regmap_read(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1,
> + &bmsr);
> + regmap_read(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5,
> + &lpa);
> +
> + bmsr = (AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE |
> + AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT |
> + AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY |
> + AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS) & bmsr;
> + lpa = AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY & lpa;
> +
> + phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa);
> +}
> +
> +static void airoha_pcs_get_state_usxgmii(struct airoha_pcs_priv *priv,
> + struct phylink_link_state *state)
> +{
> + u32 lpa;
> +
> + /* Toggle AN Status */
> + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
> + AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
> + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6,
> + AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS);
> +
> + regmap_read(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_STATS_0, &lpa);
> +
> + state->link = !!(lpa & MDIO_USXGMII_LINK);
> + state->an_complete = state->link;
> +
> + phylink_decode_usxgmii_word(state, lpa);
> +}
> +
> +static void airoha_pcs_get_state(struct phylink_pcs *pcs,
> + unsigned int neg_mode,
> + struct phylink_link_state *state)
> +{
> + struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
> +
> + switch (state->interface) {
> + case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_1000BASEX:
> + case PHY_INTERFACE_MODE_2500BASEX:
> + airoha_pcs_get_state_sgmii(priv, neg_mode, state);
> + break;
> + case PHY_INTERFACE_MODE_USXGMII:
> + case PHY_INTERFACE_MODE_10GBASER:
> + airoha_pcs_get_state_usxgmii(priv, state);
> + break;
> + default:
> + return;
> + }
> +}
> +
> +static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
> + phy_interface_t interface,
> + const unsigned long *advertising,
> + bool permit_pause_to_mac)
> +{
> + struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
> + u32 rate_adapt;
> + int ret;
> +
> + priv->interface = interface;
> +
> + /* Select HSGMII or USXGMII in SCU regs */
> + airoha_pcs_setup_scu(priv, interface);
> +
> + /* Enable Analog Common Lane */
> + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CMN_EN,
> + AIROHA_PCS_ANA_CMN_EN);
> +
> + /* Setup PLL */
> + airoha_pcs_pll_bringup(priv, interface);
> +
> + /* Setup PHYA */
> + ret = airoha_pcs_phya_bringup(priv, interface);
> + if (ret)
> + return ret;
> +
> + /* Set final configuration for various modes */
> + airoha_pcs_init(priv, interface);
> +
> + /* Configure Interrupt for various modes */
> + airoha_pcs_interrupt_init(priv, interface);
> +
> + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
> + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
> + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;
> + else
> + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
> + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |
> + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
> + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN;
> +
> + /* AN Auto Settings (Rate Adaptation) */
> + regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0,
> + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS |
> + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS |
> + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN |
> + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt);
> +
> + if (interface == PHY_INTERFACE_MODE_USXGMII ||
> + interface == PHY_INTERFACE_MODE_10GBASER) {
> + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
> + regmap_set_bits(priv->usxgmii_pcs,
> + AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
> + AIROHA_PCS_USXGMII_AN_ENABLE);
> + else
> + regmap_clear_bits(priv->usxgmii_pcs,
> + AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
> + AIROHA_PCS_USXGMII_AN_ENABLE);
> + }
> +
> + /* Clear any force bit that my be set by bootloader */
> + if (interface == PHY_INTERFACE_MODE_SGMII ||
> + interface == PHY_INTERFACE_MODE_1000BASEX ||
> + interface == PHY_INTERFACE_MODE_2500BASEX) {
> + regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
> + AIROHA_PCS_LINK_MODE_P0 |
> + AIROHA_PCS_FORCE_SPD_MODE_P0 |
> + AIROHA_PCS_FORCE_LINKDOWN_P0 |
> + AIROHA_PCS_FORCE_LINKUP_P0);
> + }
> +
> + /* Toggle Rate Adaption for SGMII/HSGMII mode */
> + if (interface == PHY_INTERFACE_MODE_SGMII ||
> + interface == PHY_INTERFACE_MODE_1000BASEX ||
> + interface == PHY_INTERFACE_MODE_2500BASEX) {
> + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
> + regmap_clear_bits(priv->hsgmii_rate_adp,
> + AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
> + AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
> + else
> + regmap_set_bits(priv->hsgmii_rate_adp,
> + AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0,
> + AIROHA_PCS_HSGMII_P0_DIS_MII_MODE);
> + }
> +
> + /* Setup AN Link Timer */
> + if (interface == PHY_INTERFACE_MODE_SGMII ||
> + interface == PHY_INTERFACE_MODE_1000BASEX ||
> + interface == PHY_INTERFACE_MODE_2500BASEX) {
> + u32 an_timer;
> +
> + an_timer = phylink_get_link_timer_ns(interface);
> +
> + /* Value needs to be shifted by 4, seems value is internally * 16 */
> + regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11,
> + AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
> + FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER,
> + an_timer >> 4));
> +
> + regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_3,
> + AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
> + FIELD_PREP(AIROHA_PCS_HSGMII_PCS_LINK_STSTIME,
> + an_timer >> 4));
> + }
> +
> + /* Setup SGMII AN and advertisement in DEV_ABILITY */
> + if (interface == PHY_INTERFACE_MODE_SGMII &&
> + neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
> + int advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
> + advertising);
> + if (advertise < 0)
> + return advertise;
> +
> + regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
> + AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
> +
> + regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4,
> + AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
> + FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY,
> + advertise));
> + } else {
> + regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
> + AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE);
> + }
> +
> + if (interface == PHY_INTERFACE_MODE_SGMII ||
> + interface == PHY_INTERFACE_MODE_1000BASEX) {
> + u32 if_mode = AIROHA_PCS_HSGMII_AN_SGMII_EN |
> + AIROHA_PCS_HSGMII_AN_SIDEBAND_EN;
> +
> + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
> + regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
> + AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
> +
> + /* Clear force speed bits and MAC mode */
> + regmap_clear_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
> + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
> + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
> + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
> + AIROHA_PCS_HSGMII_PCS_MAC_MODE |
> + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL |
> + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
> + } else {
> + if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN;
> +
> + regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
> + AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS);
> +
> + /* AN off force rate adaption, speed is set later in Link Up */
> + regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
> + AIROHA_PCS_HSGMII_PCS_MAC_MODE |
> + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT,
> + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT);
> + }
> +
> + regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
> + AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode);
> +
> + /* FIXME: Airoha apply a different configuration here */
> + /* They force rate adaption */
> + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
> + AIROHA_PCS_HSGMII_PCS_TX_ENABLE |
> + AIROHA_PCS_HSGMII_PCS_MODE2_EN);
> + }
> +
> + if (interface == PHY_INTERFACE_MODE_1000BASEX &&
> + neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
> + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
> + AIROHA_PCS_SGMII_SEND_AN_ERR_EN);
> +
> + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37,
> + AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE);
> + }
> +
> + /* Configure Flow Control on XFI */
> + regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
> + AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN,
> + permit_pause_to_mac ?
> + AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN :
> + 0);
> +
> + return 0;
> +}
> +
> +static void airoha_pcs_an_restart(struct phylink_pcs *pcs)
> +{
> + struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
> +
> + switch (priv->interface) {
> + case PHY_INTERFACE_MODE_SGMII:
> + case PHY_INTERFACE_MODE_1000BASEX:
> + case PHY_INTERFACE_MODE_2500BASEX:
> + regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
> + AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
> + udelay(3);
> + regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
> + AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
> + break;
> + case PHY_INTERFACE_MODE_USXGMII:
> + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
> + AIROHA_PCS_USXGMII_AN_RESTART);
> + udelay(3);
> + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
> + AIROHA_PCS_USXGMII_AN_RESTART);
> + default:
> + return;
> + }
> +}
> +
> +static void airoha_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
> + phy_interface_t interface, int speed, int duplex)
> +{
> + struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
> +
> + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
> + if (interface == PHY_INTERFACE_MODE_SGMII) {
> + regmap_update_bits(priv->hsgmii_rate_adp,
> + AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
> + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
> + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
> + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) |
> + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0));
> + udelay(1);
> + regmap_update_bits(priv->hsgmii_rate_adp,
> + AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1,
> + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR |
> + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR,
> + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) |
> + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5));
> + }
> + } else {
> + if (interface == PHY_INTERFACE_MODE_USXGMII ||
> + interface == PHY_INTERFACE_MODE_10GBASER) {
> + u32 mode;
> + u32 rate_adapt;
> +
> + switch (speed) {
> + case SPEED_10000:
> + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000;
> + mode = AIROHA_PCS_USXGMII_MODE_10000;
> + break;
> + case SPEED_5000:
> + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000;
> + mode = AIROHA_PCS_USXGMII_MODE_5000;
> + break;
> + case SPEED_2500:
> + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500;
> + mode = AIROHA_PCS_USXGMII_MODE_2500;
> + break;
> + case SPEED_1000:
> + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000;
> + mode = AIROHA_PCS_USXGMII_MODE_1000;
> + break;
> + case SPEED_100:
> + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100;
> + mode = AIROHA_PCS_USXGMII_MODE_100;
> + break;
> + }
> +
> + /* Trigger USXGMII change mode and force selected speed */
> + regmap_update_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
> + AIROHA_PCS_USXGMII_RATE_UPDATE_MODE |
> + AIROHA_PCS_USXGMII_MODE,
> + AIROHA_PCS_USXGMII_RATE_UPDATE_MODE | mode);
> +
> + regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11,
> + AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
> + AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE,
> + AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN |
> + rate_adapt);
> + }
> +
> + if (interface == PHY_INTERFACE_MODE_SGMII ||
> + interface == PHY_INTERFACE_MODE_1000BASEX) {
> + u32 force_speed;
> + u32 rate_adapt;
> +
> + switch (speed) {
> + case SPEED_1000:
> + force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000;
> + rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000;
> + break;
> + case SPEED_100:
> + force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100;
> + rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100;
> + break;
> + case SPEED_10:
> + force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10;
> + rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10;
> + break;
> + }
> +
> + regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6,
> + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 |
> + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 |
> + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 |
> + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL,
> + force_speed | rate_adapt);
> + }
> +
> + if (interface == PHY_INTERFACE_MODE_SGMII ||
> + interface == PHY_INTERFACE_MODE_2500BASEX) {
> + u32 ck_gen_mode;
> + u32 speed_reg;
> + u32 if_mode;
> +
> + switch (speed) {
> + case SPEED_2500:
> + speed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G;
> + break;
> + case SPEED_1000:
> + speed_reg = AIROHA_PCS_LINK_MODE_P0_1G;
> + if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000;
> + ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000;
> + break;
> + case SPEED_100:
> + speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
> + if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100;
> + ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100;
> + break;
> + case SPEED_10:
> + speed_reg = AIROHA_PCS_LINK_MODE_P0_100M;
> + if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10;
> + ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10;
> + break;
> + }
> +
> + if (interface == PHY_INTERFACE_MODE_SGMII) {
> + regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13,
> + AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE,
> + if_mode);
> +
> + regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE,
> + AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE |
> + AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL,
> + ck_gen_mode |
> + AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL);
> + }
> +
> + regmap_update_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0,
> + AIROHA_PCS_LINK_MODE_P0 |
> + AIROHA_PCS_FORCE_SPD_MODE_P0,
> + speed_reg |
> + AIROHA_PCS_FORCE_SPD_MODE_P0);
> + }
> + }
> +
> + /* Reset TXPCS on link up */
> + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
> + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
> +
> + usleep_range(100, 200);
> +
> + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET,
> + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N);
> +}
> +
> +static const struct phylink_pcs_ops airoha_pcs_ops = {
> + .pcs_get_state = airoha_pcs_get_state,
> + .pcs_config = airoha_pcs_config,
> + .pcs_an_restart = airoha_pcs_an_restart,
> + .pcs_link_up = airoha_pcs_link_up,
> +};
> +
> +static const struct regmap_config airoha_pcs_regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +static int airoha_pcs_probe(struct platform_device *pdev)
> +{
> + struct regmap_config syscon_config = airoha_pcs_regmap_config;
> + struct device *dev = &pdev->dev;
> + struct airoha_pcs_priv *priv;
> + void *base;
Missing __iomem type here, will be fixed in v2.
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->dev = dev;
> + priv->data = of_device_get_match_data(dev);
> +
> + base = devm_platform_ioremap_resource_byname(pdev, "xfi_mac");
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + syscon_config.name = "xfi_mac";
> + priv->xfi_mac = devm_regmap_init_mmio(dev, base, &syscon_config);
> + if (IS_ERR(priv->xfi_mac))
> + return PTR_ERR(priv->xfi_mac);
> +
> + base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_an");
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + syscon_config.name = "hsgmii_an";
> + priv->hsgmii_an = devm_regmap_init_mmio(dev, base, &syscon_config);
> + if (IS_ERR(priv->hsgmii_an))
> + return PTR_ERR(priv->hsgmii_an);
> +
> + base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_pcs");
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + syscon_config.name = "hsgmii_pcs";
> + priv->hsgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
> + if (IS_ERR(priv->hsgmii_pcs))
> + return PTR_ERR(priv->hsgmii_pcs);
> +
> + base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_rate_adp");
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + syscon_config.name = "hsgmii_rate_adp";
> + priv->hsgmii_rate_adp = devm_regmap_init_mmio(dev, base, &syscon_config);
> + if (IS_ERR(priv->hsgmii_rate_adp))
> + return PTR_ERR(priv->hsgmii_rate_adp);
> +
> + base = devm_platform_ioremap_resource_byname(pdev, "multi_sgmii");
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + syscon_config.name = "multi_sgmii";
> + priv->multi_sgmii = devm_regmap_init_mmio(dev, base, &syscon_config);
> + if (IS_ERR(priv->multi_sgmii))
> + return PTR_ERR(priv->multi_sgmii);
> +
> + base = devm_platform_ioremap_resource_byname(pdev, "usxgmii");
> + if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
> + return PTR_ERR(base);
> +
> + syscon_config.name = "usxgmii";
> + priv->usxgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
> + if (IS_ERR(priv->usxgmii_pcs))
> + return PTR_ERR(priv->usxgmii_pcs);
> +
> + base = devm_platform_ioremap_resource_byname(pdev, "xfi_pma");
> + if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
> + return PTR_ERR(base);
> +
> + syscon_config.name = "xfi_pma";
> + priv->xfi_pma = devm_regmap_init_mmio(dev, base, &syscon_config);
> + if (IS_ERR(priv->xfi_pma))
> + return PTR_ERR(priv->xfi_pma);
> +
> + base = devm_platform_ioremap_resource_byname(pdev, "xfi_ana");
> + if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
> + return PTR_ERR(base);
> +
> + syscon_config.name = "xfi_ana";
> + priv->xfi_ana = devm_regmap_init_mmio(dev, base, &syscon_config);
> + if (IS_ERR(priv->xfi_ana))
> + return PTR_ERR(priv->xfi_ana);
> +
> + /* SCU is used to toggle XFI or HSGMII in global SoC registers */
> + priv->scu = syscon_regmap_lookup_by_compatible("airoha,en7581-scu");
> + if (IS_ERR(priv->scu))
> + return PTR_ERR(priv->scu);
> +
> + priv->rsts[0].id = "mac";
> + priv->rsts[1].id = "phy";
> + ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(priv->rsts),
> + priv->rsts);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to get bulk reset lines\n");
> +
> + platform_set_drvdata(pdev, priv);
> +
> + priv->pcs.ops = &airoha_pcs_ops;
> + priv->pcs.poll = true;
> +
> + __set_bit(PHY_INTERFACE_MODE_SGMII, priv->pcs.supported_interfaces);
> + __set_bit(PHY_INTERFACE_MODE_1000BASEX, priv->pcs.supported_interfaces);
> + __set_bit(PHY_INTERFACE_MODE_2500BASEX, priv->pcs.supported_interfaces);
> + __set_bit(PHY_INTERFACE_MODE_10GBASER, priv->pcs.supported_interfaces);
> + __set_bit(PHY_INTERFACE_MODE_USXGMII, priv->pcs.supported_interfaces);
> +
> + return of_pcs_add_provider(dev->of_node, of_pcs_simple_get,
> + &priv->pcs);
> +}
> +
> +static void airoha_pcs_remove(struct platform_device *pdev)
> +{
> + struct airoha_pcs_priv *priv = platform_get_drvdata(pdev);
> +
> + phylink_pcs_release(&priv->pcs);
> +
> + of_pcs_del_provider(pdev->dev.of_node);
> +}
> +
> +static const struct airoha_pcs_match_data an7581_pcs_eth = {
> + .port_type = AIROHA_PCS_ETH,
> +};
> +
> +static const struct airoha_pcs_match_data an7581_pcs_pon = {
> + .port_type = AIROHA_PCS_PON,
> +};
> +
> +static const struct of_device_id airoha_pcs_of_table[] = {
> + { .compatible = "airoha,an7581-pcs-eth", .data = &an7581_pcs_eth },
> + { .compatible = "airoha,an7581-pcs-pon", .data = &an7581_pcs_pon },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);
> +
> +static struct platform_driver airoha_pcs_driver = {
> + .driver = {
> + .name = "airoha-pcs",
> + .of_match_table = airoha_pcs_of_table,
> + },
> + .probe = airoha_pcs_probe,
> + .remove = airoha_pcs_remove,
> +};
> +module_platform_driver(airoha_pcs_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("Airoha PCS driver");
> +MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
> diff --git a/include/linux/pcs/pcs-airoha.h b/include/linux/pcs/pcs-airoha.h
> new file mode 100644
> index 000000000000..07797645ff15
> --- /dev/null
> +++ b/include/linux/pcs/pcs-airoha.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +#ifndef __LINUX_PCS_AIROHA_H
> +#define __LINUX_PCS_AIROHA_H
> +
> +/* XFI_MAC */
> +#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG 0x0
> +#define AIROHA_PCS_XFI_TX_FC_EN BIT(5)
> +#define AIROHA_PCS_XFI_RX_FC_EN BIT(4)
> +
> +#endif /* __LINUX_PCS_AIROHA_H */
> --
> 2.48.1
>
--
Ansuel
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver
2025-03-18 23:58 ` [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver Christian Marangi
2025-03-19 9:11 ` Christian Marangi
@ 2025-03-19 9:25 ` Christian Marangi
2025-03-19 15:17 ` Russell King (Oracle)
` (2 subsequent siblings)
4 siblings, 0 replies; 34+ messages in thread
From: Christian Marangi @ 2025-03-19 9:25 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Russell King, Philipp Zabel, Daniel Golle,
netdev, devicetree, linux-kernel, upstream
On Wed, Mar 19, 2025 at 12:58:38AM +0100, Christian Marangi wrote:
> Implement the foundation of OF support for PCS driver.
>
> To support this, implement a simple Provider API where a PCS driver can
> expose multiple PCS with an xlate .get function.
>
> PCS driver will have to call of_pcs_add_provider() and pass the device
> node pointer and a xlate function to return the correct PCS for the
> requested interface and the passed #pcs-cells.
>
> This will register the PCS in a global list of providers so that
> consumer can access it.
>
> Consumer will then use of_pcs_get() to get the actual PCS by passing the
> device_node pointer, the index for #pcs-cells and the requested
> interface.
>
> For simple implementation where #pcs-cells is 0 and the PCS driver
> expose a single PCS, the xlate function of_pcs_simple_get() is
> provided. In such case the passed interface is ignored and is expected
> that the PCS supports any interface mode supported by the MAC.
>
> For advanced implementation a custom xlate function is required. Such
> function should return an error if the PCS is not supported for the
> requested interface type.
>
> This is needed for the correct function of of_phylink_mac_select_pcs()
> later described.
>
> PCS driver on removal should first call phylink_pcs_release() on every
> PCS the driver provides and then correctly delete as a provider with
> the usage of of_pcs_del_provider().
>
> A generic function for .mac_select_pcs is provided for any MAC driver
> that will declare PCS in DT, of_phylink_mac_select_pcs().
> This function will parse "pcs-handle" property and will try every PCS
> declared in DT until one that supports the requested interface type is
> found. This works by leveraging the return value of the xlate function
> returned by of_pcs_get() and checking if it's an ERROR or NULL, in such
> case the next PCS in the phandle array is tested.
>
> Some additional helper are provided for xlate functions,
> pcs_supports_interface() as a simple function to check if the requested
> interface is supported by the PCS and phylink_pcs_release() to release a
> PCS from a phylink instance.
>
> Co-developed-by: Daniel Golle <daniel@makrotopia.org>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> drivers/net/pcs/Kconfig | 7 ++
> drivers/net/pcs/Makefile | 1 +
> drivers/net/pcs/pcs.c | 185 +++++++++++++++++++++++++++++++
> drivers/net/phy/phylink.c | 21 ++++
> include/linux/pcs/pcs-provider.h | 46 ++++++++
> include/linux/pcs/pcs.h | 62 +++++++++++
> include/linux/phylink.h | 2 +
> 7 files changed, 324 insertions(+)
> create mode 100644 drivers/net/pcs/pcs.c
> create mode 100644 include/linux/pcs/pcs-provider.h
> create mode 100644 include/linux/pcs/pcs.h
>
> diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
> index f6aa437473de..8c3b720de6fd 100644
> --- a/drivers/net/pcs/Kconfig
> +++ b/drivers/net/pcs/Kconfig
> @@ -5,6 +5,13 @@
>
> menu "PCS device drivers"
>
> +config OF_PCS
> + tristate
> + depends on OF
> + depends on PHYLINK
> + help
> + OpenFirmware PCS accessors
> +
> config PCS_XPCS
> tristate "Synopsys DesignWare Ethernet XPCS"
> select PHYLINK
> diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
> index 4f7920618b90..29881f0f981f 100644
> --- a/drivers/net/pcs/Makefile
> +++ b/drivers/net/pcs/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
> # Makefile for Linux PCS drivers
>
> +obj-$(CONFIG_OF_PCS) += pcs.o
> pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
> pcs-xpcs-nxp.o pcs-xpcs-wx.o
>
> diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
> new file mode 100644
> index 000000000000..af04a76ef825
> --- /dev/null
> +++ b/drivers/net/pcs/pcs.c
> @@ -0,0 +1,185 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +
> +#include <linux/mutex.h>
> +#include <linux/of.h>
> +#include <linux/phylink.h>
> +#include <linux/pcs/pcs.h>
> +#include <linux/pcs/pcs-provider.h>
> +
> +struct of_pcs_provider {
> + struct list_head link;
> +
> + struct device_node *node;
> + struct phylink_pcs *(*get)(struct of_phandle_args *pcsspec,
> + void *data,
> + phy_interface_t interface);
> +
> + void *data;
> +};
> +
> +static LIST_HEAD(of_pcs_providers);
> +static DEFINE_MUTEX(of_pcs_mutex);
> +
> +struct phylink_pcs *of_pcs_simple_get(struct of_phandle_args *pcsspec, void *data,
> + phy_interface_t interface)
> +{
> + struct phylink_pcs *pcs = data;
> +
> + if (!pcs_supports_interface(pcs, interface))
> + return ERR_PTR(-EOPNOTSUPP);
> +
> + return data;
> +}
> +EXPORT_SYMBOL_GPL(of_pcs_simple_get);
> +
> +int of_pcs_add_provider(struct device_node *np,
> + struct phylink_pcs *(*get)(struct of_phandle_args *pcsspec,
> + void *data,
> + phy_interface_t interface),
> + void *data)
> +{
> + struct of_pcs_provider *pp;
> +
> + if (!np)
> + return 0;
> +
> + pp = kzalloc(sizeof(*pp), GFP_KERNEL);
> + if (!pp)
> + return -ENOMEM;
> +
> + pp->node = of_node_get(np);
> + pp->data = data;
> + pp->get = get;
> +
> + mutex_lock(&of_pcs_mutex);
> + list_add(&pp->link, &of_pcs_providers);
> + mutex_unlock(&of_pcs_mutex);
> + pr_debug("Added pcs provider from %pOF\n", np);
> +
> + fwnode_dev_initialized(&np->fwnode, true);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(of_pcs_add_provider);
> +
> +void of_pcs_del_provider(struct device_node *np)
> +{
> + struct of_pcs_provider *pp;
> +
> + if (!np)
> + return;
> +
> + mutex_lock(&of_pcs_mutex);
> + list_for_each_entry(pp, &of_pcs_providers, link) {
> + if (pp->node == np) {
> + list_del(&pp->link);
> + fwnode_dev_initialized(&np->fwnode, false);
> + of_node_put(pp->node);
> + kfree(pp);
> + break;
> + }
> + }
> + mutex_unlock(&of_pcs_mutex);
> +}
> +EXPORT_SYMBOL_GPL(of_pcs_del_provider);
> +
> +static int of_parse_pcsspec(const struct device_node *np, int index,
> + const char *name, struct of_phandle_args *out_args)
> +{
> + int ret = -ENOENT;
> +
> + if (!np)
> + return -ENOENT;
> +
> + if (name)
> + index = of_property_match_string(np, "pcs-names", name);
> +
> + ret = of_parse_phandle_with_args(np, "pcs-handle", "#pcs-cells",
> + index, out_args);
> + if (ret || (name && index < 0))
> + return ret;
> +
> + return 0;
> +}
> +
> +static struct phylink_pcs *
> +of_pcs_get_from_pcsspec(struct of_phandle_args *pcsspec,
> + phy_interface_t interface)
> +{
> + struct of_pcs_provider *provider;
> + struct phylink_pcs *pcs = ERR_PTR(-EPROBE_DEFER);
> +
> + if (!pcsspec)
> + return ERR_PTR(-EINVAL);
> +
> + mutex_lock(&of_pcs_mutex);
> + list_for_each_entry(provider, &of_pcs_providers, link) {
> + if (provider->node == pcsspec->np) {
> + pcs = provider->get(pcsspec, provider->data,
> + interface);
> + if (!IS_ERR(pcs))
> + break;
> + }
> + }
> + mutex_unlock(&of_pcs_mutex);
> +
> + return pcs;
> +}
> +
> +static struct phylink_pcs *__of_pcs_get(struct device_node *np, int index,
> + const char *con_id,
> + phy_interface_t interface)
> +{
> + struct of_phandle_args pcsspec;
> + struct phylink_pcs *pcs;
> + int ret;
> +
> + ret = of_parse_pcsspec(np, index, con_id, &pcsspec);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + pcs = of_pcs_get_from_pcsspec(&pcsspec, interface);
> + of_node_put(pcsspec.np);
> +
> + return pcs;
> +}
> +
> +struct phylink_pcs *of_pcs_get(struct device_node *np, int index,
> + phy_interface_t interface)
> +{
> + return __of_pcs_get(np, index, NULL, interface);
> +}
> +EXPORT_SYMBOL_GPL(of_pcs_get);
> +
> +struct phylink_pcs *of_phylink_mac_select_pcs(struct phylink_config *config,
> + phy_interface_t interface)
> +{
> + int i, count;
> + struct device *dev = config->dev;
> + struct device_node *np = dev->of_node;
> + struct phylink_pcs *pcs = ERR_PTR(-ENODEV);
> +
> + /* To enable using_mac_select_pcs on phylink_create */
> + if (interface == PHY_INTERFACE_MODE_NA)
> + return NULL;
> +
> + /* Reject configuring PCS with Internal mode */
> + if (interface == PHY_INTERFACE_MODE_INTERNAL)
> + return ERR_PTR(-EINVAL);
> +
> + if (!of_property_present(np, "pcs-handle"))
> + return pcs;
> +
> + count = of_count_phandle_with_args(np, "pcs-handle", "#pcs-cells");
> + if (count < 0)
> + return ERR_PTR(count);
> +
> + for (i = 0; i < count; i++) {
> + pcs = of_pcs_get(np, i, interface);
> + if (!IS_ERR_OR_NULL(pcs))
> + return pcs;
> + }
> +
> + return pcs;
> +}
> +EXPORT_SYMBOL_GPL(of_phylink_mac_select_pcs);
> diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
> index eef1712ec22c..7f71547e89fe 100644
> --- a/drivers/net/phy/phylink.c
> +++ b/drivers/net/phy/phylink.c
> @@ -1130,6 +1130,27 @@ int phylink_pcs_pre_init(struct phylink *pl, struct phylink_pcs *pcs)
> }
> EXPORT_SYMBOL_GPL(phylink_pcs_pre_init);
>
> +/**
> + * phylink_pcs_release() - release a PCS
> + * @pl: a pointer to &struct phylink_pcs
> + *
> + * PCS provider can use this to release a PCS from a phylink
> + * instance by stopping the attached netdev. This is only done
> + * if the PCS is actually attached to a phylink, otherwise is
> + * ignored.
> + */
> +void phylink_pcs_release(struct phylink_pcs *pcs)
> +{
> + struct phylink *pl = pcs->phylink;
> +
> + if (pl) {
> + rtnl_lock();
> + dev_close(pl->netdev);
> + rtnl_unlock();
> + }
> +}
> +EXPORT_SYMBOL_GPL(phylink_pcs_release);
> +
> static void phylink_mac_config(struct phylink *pl,
> const struct phylink_link_state *state)
> {
> diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
> new file mode 100644
> index 000000000000..0172d0286f07
> --- /dev/null
> +++ b/include/linux/pcs/pcs-provider.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +#ifndef __LINUX_PCS_PROVIDER_H
> +#define __LINUX_PCS_PROVIDER_H
> +
> +#include <linux/phy.h>
> +
> +/**
> + * of_pcs_simple_get - Simple xlate function to retrieve PCS
> + * @pcsspec: Phandle arguments
> + * @data: Context data (assumed assigned to the single PCS)
> + * @interface: requested PHY interface type for PCS
> + *
> + * Returns the PCS (pointed by data) or an -EOPNOTSUPP pointer
> + * if the PCS doesn't support the requested interface.
> + */
> +struct phylink_pcs *of_pcs_simple_get(struct of_phandle_args *pcsspec, void *data,
> + phy_interface_t interface);
> +
> +/**
> + * of_pcs_add_provider - Registers a new PCS provider
> + * @np: Device node
> + * @get: xlate function to retrieve the PCS
> + * @data: Context data
> + *
> + * Register and add a new PCS to the global providers list
> + * for the device node. A function to get the PCS from
> + * device node with the use of phandle args.
> + * To the get function is also passed the interface type
> + * requested for the PHY. PCS driver will use the passed
> + * interface to understand if the PCS can support it or not.
> + *
> + * Returns 0 on success or -ENOMEM on allocation failure.
> + */
> +int of_pcs_add_provider(struct device_node *np,
> + struct phylink_pcs *(*get)(struct of_phandle_args *pcsspec,
> + void *data,
> + phy_interface_t interface),
> + void *data);
> +
> +/**
> + * of_pcs_del_provider - Removes a PCS provider
> + * @np: Device node
> + */
> +void of_pcs_del_provider(struct device_node *np);
> +
> +#endif /* __LINUX_PCS_PROVIDER_H */
> diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
> new file mode 100644
> index 000000000000..b681bf05ac08
> --- /dev/null
> +++ b/include/linux/pcs/pcs.h
> @@ -0,0 +1,62 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +#ifndef __LINUX_PCS_H
> +#define __LINUX_PCS_H
> +
> +#include <linux/phy.h>
> +#include <linux/phylink.h>
> +
> +static inline bool pcs_supports_interface(struct phylink_pcs *pcs,
> + phy_interface_t interface)
> +{
> + return test_bit(interface, pcs->supported_interfaces);
> +}
> +
> +#ifdef CONFIG_OF_PCS
Will be changed to IS_ENABLED to account for module config.
> +/**
> + * of_pcs_get - Retrieves a PCS from a device node
> + * @np: Device node
> + * @index: Index of PCS handle in Device Node
> + * @interface: requested PHY interface type for PCS
> + *
> + * Get a PCS for the requested PHY interface type from the
> + * device node at index.
> + *
> + * Returns a pointer to the phylink_pcs or a negative
> + * error pointer. Can return -EPROBE_DEFER if the PCS is not
> + * present in global providers list (either due to driver
> + * still needs to be probed or it failed to probe/removed)
> + */
> +struct phylink_pcs *of_pcs_get(struct device_node *np, int index,
> + phy_interface_t interface);
> +
> +/**
> + * of_phylink_mac_select_pcs - Generic MAC select pcs for OF PCS provider
> + * @config: phylink config pointer
> + * @interface: requested PHY interface type for PCS
> + *
> + * Generic helper function to get a PCS from a "pcs-handle" OF property
> + * defined in device tree. Each phandle defined in "pcs-handle" will be
> + * tested until a PCS that supports the requested PHY interface is found.
> + *
> + * Returns a pointer to the selected PCS or an error pointer.
> + * Return NULL for PHY_INTERFACE_MODE_NA and a -EINVAL error pointer
> + * for PHY_INTERFACE_MODE_INTERNAL. It can also return -EPROBE_DEFER,
> + * refer to of_pcs_get for details about it.
> + */
> +struct phylink_pcs *of_phylink_mac_select_pcs(struct phylink_config *config,
> + phy_interface_t interface);
> +#else
> +static inline struct phylink_pcs *of_pcs_get(struct device_node *np, int index,
> + phy_interface_t interface)
> +{
> + return PTR_ERR(-ENOENT);
Wrong macro for error, will be fixed in v2.
> +}
> +
> +static inline struct phylink_pcs *of_phylink_mac_select_pcs(struct phylink_config *config,
> + phy_interface_t interface)
> +{
> + return PTR_ERR(-EOPNOTSUPP);
Ditto.
> +}
> +#endif
> +
> +#endif /* __LINUX_PCS_H */
> diff --git a/include/linux/phylink.h b/include/linux/phylink.h
> index c187267a15b6..80367d4fbad9 100644
> --- a/include/linux/phylink.h
> +++ b/include/linux/phylink.h
> @@ -695,6 +695,8 @@ void phylink_pcs_change(struct phylink_pcs *, bool up);
>
> int phylink_pcs_pre_init(struct phylink *pl, struct phylink_pcs *pcs);
>
> +void phylink_pcs_release(struct phylink_pcs *pcs);
> +
> void phylink_start(struct phylink *);
> void phylink_stop(struct phylink *);
>
> --
> 2.48.1
>
--
Ansuel
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver
2025-03-18 23:58 ` [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver Christian Marangi
2025-03-19 9:11 ` Christian Marangi
2025-03-19 9:25 ` Christian Marangi
@ 2025-03-19 15:17 ` Russell King (Oracle)
2025-03-19 16:03 ` Christian Marangi
2025-03-19 17:05 ` kernel test robot
2025-04-01 20:59 ` Sean Anderson
4 siblings, 1 reply; 34+ messages in thread
From: Russell King (Oracle) @ 2025-03-19 15:17 UTC (permalink / raw)
To: Christian Marangi
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Wed, Mar 19, 2025 at 12:58:38AM +0100, Christian Marangi wrote:
> Implement the foundation of OF support for PCS driver.
>
> To support this, implement a simple Provider API where a PCS driver can
> expose multiple PCS with an xlate .get function.
>
> PCS driver will have to call of_pcs_add_provider() and pass the device
> node pointer and a xlate function to return the correct PCS for the
> requested interface and the passed #pcs-cells.
>
> This will register the PCS in a global list of providers so that
> consumer can access it.
>
> Consumer will then use of_pcs_get() to get the actual PCS by passing the
> device_node pointer, the index for #pcs-cells and the requested
> interface.
>
> For simple implementation where #pcs-cells is 0 and the PCS driver
> expose a single PCS, the xlate function of_pcs_simple_get() is
> provided. In such case the passed interface is ignored and is expected
> that the PCS supports any interface mode supported by the MAC.
>
> For advanced implementation a custom xlate function is required. Such
> function should return an error if the PCS is not supported for the
> requested interface type.
>
> This is needed for the correct function of of_phylink_mac_select_pcs()
> later described.
>
> PCS driver on removal should first call phylink_pcs_release() on every
> PCS the driver provides and then correctly delete as a provider with
> the usage of of_pcs_del_provider().
>
> A generic function for .mac_select_pcs is provided for any MAC driver
> that will declare PCS in DT, of_phylink_mac_select_pcs().
> This function will parse "pcs-handle" property and will try every PCS
> declared in DT until one that supports the requested interface type is
> found. This works by leveraging the return value of the xlate function
> returned by of_pcs_get() and checking if it's an ERROR or NULL, in such
> case the next PCS in the phandle array is tested.
>
> Some additional helper are provided for xlate functions,
> pcs_supports_interface() as a simple function to check if the requested
> interface is supported by the PCS and phylink_pcs_release() to release a
> PCS from a phylink instance.
>
> Co-developed-by: Daniel Golle <daniel@makrotopia.org>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
As a general comment, should we be developing stuff that is DT-centric
or fwnode-centric. We already have users of phylink using swnodes, and
it seems bad to design something today that is centred around just one
method of describing something.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 3/6] net: phylink: Correctly handle PCS probe defer from PCS provider
2025-03-18 23:58 ` [net-next PATCH 3/6] net: phylink: Correctly handle PCS probe defer from PCS provider Christian Marangi
@ 2025-03-19 15:58 ` Russell King (Oracle)
2025-03-19 16:18 ` Christian Marangi
0 siblings, 1 reply; 34+ messages in thread
From: Russell King (Oracle) @ 2025-03-19 15:58 UTC (permalink / raw)
To: Christian Marangi
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Wed, Mar 19, 2025 at 12:58:39AM +0100, Christian Marangi wrote:
> diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
> index 7f71547e89fe..c6d9e4efed13 100644
> --- a/drivers/net/phy/phylink.c
> +++ b/drivers/net/phy/phylink.c
> @@ -1395,6 +1395,15 @@ static void phylink_major_config(struct phylink *pl, bool restart,
> if (pl->mac_ops->mac_select_pcs) {
> pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
> if (IS_ERR(pcs)) {
> + /* PCS can be removed unexpectedly and not available
> + * anymore.
> + * PCS provider will return probe defer as the PCS
> + * can't be found in the global provider list.
> + * In such case, return -ENOENT as a more symbolic name
> + * for the error message.
> + */
> + if (PTR_ERR(pcs) == -EPROBE_DEFER)
> + pcs = ERR_PTR(-ENOENT);
I don't particularly like the idea of returning -EPROBE_DEFER from
mac_select_pcs()... there is no way *ever* that such an error code
could be handled.
> linkmode_fill(pl->supported);
> linkmode_copy(pl->link_config.advertising, pl->supported);
> - phylink_validate(pl, pl->supported, &pl->link_config);
> + ret = phylink_validate(pl, pl->supported, &pl->link_config);
> + /* The PCS might not available at the time phylink_create
> + * is called. Check this and communicate to the MAC driver
> + * that probe should be retried later.
> + *
> + * Notice that this can only happen in probe stage and PCS
> + * is expected to be avaialble in phylink_major_config.
> + */
> + if (ret == -EPROBE_DEFER) {
> + kfree(pl);
> + return ERR_PTR(ret);
> + }
This does not solve the problem - what if the interface mode is
currently not one that requires a PCS that may not yet be probed?
I don't like the idea that mac_select_pcs() might be doing a complex
lookup - that could make scanning the interface modes (as
phylink_validate_mask() does) quite slow and unreliable, and phylink
currently assumes that a PCS that is validated as present will remain
present.
If it goes away by the time phylink_major_config() is called, then we
leave the phylink state no longer reflecting how the hardware is
programmed, but we still continue to call mac_link_up() - which should
probably be fixed.
Given that netdev is severely backlogged, I'm not inclined to add to
the netdev maintainers workloads by trying to fix this until after
the merge window - it looks like they're at least one week behind.
Consequently, I'm expecting that most patches that have been
submitted during this week will be dropped from patchwork, which
means submitting patches this week is likely not useful.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver
2025-03-19 15:17 ` Russell King (Oracle)
@ 2025-03-19 16:03 ` Christian Marangi
2025-03-19 16:26 ` Russell King (Oracle)
0 siblings, 1 reply; 34+ messages in thread
From: Christian Marangi @ 2025-03-19 16:03 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Wed, Mar 19, 2025 at 03:17:27PM +0000, Russell King (Oracle) wrote:
> On Wed, Mar 19, 2025 at 12:58:38AM +0100, Christian Marangi wrote:
> > Implement the foundation of OF support for PCS driver.
> >
> > To support this, implement a simple Provider API where a PCS driver can
> > expose multiple PCS with an xlate .get function.
> >
> > PCS driver will have to call of_pcs_add_provider() and pass the device
> > node pointer and a xlate function to return the correct PCS for the
> > requested interface and the passed #pcs-cells.
> >
> > This will register the PCS in a global list of providers so that
> > consumer can access it.
> >
> > Consumer will then use of_pcs_get() to get the actual PCS by passing the
> > device_node pointer, the index for #pcs-cells and the requested
> > interface.
> >
> > For simple implementation where #pcs-cells is 0 and the PCS driver
> > expose a single PCS, the xlate function of_pcs_simple_get() is
> > provided. In such case the passed interface is ignored and is expected
> > that the PCS supports any interface mode supported by the MAC.
> >
> > For advanced implementation a custom xlate function is required. Such
> > function should return an error if the PCS is not supported for the
> > requested interface type.
> >
> > This is needed for the correct function of of_phylink_mac_select_pcs()
> > later described.
> >
> > PCS driver on removal should first call phylink_pcs_release() on every
> > PCS the driver provides and then correctly delete as a provider with
> > the usage of of_pcs_del_provider().
> >
> > A generic function for .mac_select_pcs is provided for any MAC driver
> > that will declare PCS in DT, of_phylink_mac_select_pcs().
> > This function will parse "pcs-handle" property and will try every PCS
> > declared in DT until one that supports the requested interface type is
> > found. This works by leveraging the return value of the xlate function
> > returned by of_pcs_get() and checking if it's an ERROR or NULL, in such
> > case the next PCS in the phandle array is tested.
> >
> > Some additional helper are provided for xlate functions,
> > pcs_supports_interface() as a simple function to check if the requested
> > interface is supported by the PCS and phylink_pcs_release() to release a
> > PCS from a phylink instance.
> >
> > Co-developed-by: Daniel Golle <daniel@makrotopia.org>
> > Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
>
> As a general comment, should we be developing stuff that is DT-centric
> or fwnode-centric. We already have users of phylink using swnodes, and
> it seems bad to design something today that is centred around just one
> method of describing something.
>
Honestly, at least for me testing scenario different than DT is quite
difficult, we can make changes to also support swnodes but we won't have
anything to test them. Given the bad situation PCS is currently I feel
we should first focus on DT or at least model something workable first
than put even more complex stuff on the table.
--
Ansuel
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 3/6] net: phylink: Correctly handle PCS probe defer from PCS provider
2025-03-19 15:58 ` Russell King (Oracle)
@ 2025-03-19 16:18 ` Christian Marangi
2025-03-19 17:02 ` Russell King (Oracle)
0 siblings, 1 reply; 34+ messages in thread
From: Christian Marangi @ 2025-03-19 16:18 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Wed, Mar 19, 2025 at 03:58:14PM +0000, Russell King (Oracle) wrote:
> On Wed, Mar 19, 2025 at 12:58:39AM +0100, Christian Marangi wrote:
> > diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
> > index 7f71547e89fe..c6d9e4efed13 100644
> > --- a/drivers/net/phy/phylink.c
> > +++ b/drivers/net/phy/phylink.c
> > @@ -1395,6 +1395,15 @@ static void phylink_major_config(struct phylink *pl, bool restart,
> > if (pl->mac_ops->mac_select_pcs) {
> > pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
> > if (IS_ERR(pcs)) {
> > + /* PCS can be removed unexpectedly and not available
> > + * anymore.
> > + * PCS provider will return probe defer as the PCS
> > + * can't be found in the global provider list.
> > + * In such case, return -ENOENT as a more symbolic name
> > + * for the error message.
> > + */
> > + if (PTR_ERR(pcs) == -EPROBE_DEFER)
> > + pcs = ERR_PTR(-ENOENT);
>
> I don't particularly like the idea of returning -EPROBE_DEFER from
> mac_select_pcs()... there is no way *ever* that such an error code
> could be handled.
>
Maybe this wasn't clear enough, the idea here is that at major_config
under normal situation this case should never happen unless the driver
was removed. In such case the PCS provider returns a EPROBE_DEFER that
in this case is assumed driver not present anymore. Hence phylink fails
to apply the configuration similar to the other fail case in the same
function.
The principle here is not "we need to wait for PCS" but react on the
fact that it was removed in the meantime. (something that should not
happen as the PCS driver is expected to dev_close the interface)
> > linkmode_fill(pl->supported);
> > linkmode_copy(pl->link_config.advertising, pl->supported);
> > - phylink_validate(pl, pl->supported, &pl->link_config);
> > + ret = phylink_validate(pl, pl->supported, &pl->link_config);
> > + /* The PCS might not available at the time phylink_create
> > + * is called. Check this and communicate to the MAC driver
> > + * that probe should be retried later.
> > + *
> > + * Notice that this can only happen in probe stage and PCS
> > + * is expected to be avaialble in phylink_major_config.
> > + */
> > + if (ret == -EPROBE_DEFER) {
> > + kfree(pl);
> > + return ERR_PTR(ret);
> > + }
>
> This does not solve the problem - what if the interface mode is
> currently not one that requires a PCS that may not yet be probed?
Mhhh but what are the actual real world scenario for this? If a MAC
needs a dedicated PCS to handle multiple mode then it will probably
follow this new implementation and register as a provider.
An option to handle your corner case might be an OP that wait for each
supported interface by the MAC and make sure there is a possible PCS for
it. And Ideally place it in the codeflow of validate_pcs ?
>
> I don't like the idea that mac_select_pcs() might be doing a complex
> lookup - that could make scanning the interface modes (as
> phylink_validate_mask() does) quite slow and unreliable, and phylink
> currently assumes that a PCS that is validated as present will remain
> present.
The assumption "will remain present" is already very fragile with the
current PCS so I feel this should be changed or improved. Honestly every
PCS currently implemented can be removed and phylink will stay in an
undefined state.
Also the complex lookup in 99% of the time is really checking one/2 max
PCS for a single interface and we are really checking a list and a
bitmap, nothing fancy that might introduce delay waiting for something.
>
> If it goes away by the time phylink_major_config() is called, then we
> leave the phylink state no longer reflecting how the hardware is
> programmed, but we still continue to call mac_link_up() - which should
> probably be fixed.
Again, the idea to prevent these kind of chicken-egg problem is to
enforce correct removal on the PCS driver side.
>
> Given that netdev is severely backlogged, I'm not inclined to add to
> the netdev maintainers workloads by trying to fix this until after
> the merge window - it looks like they're at least one week behind.
> Consequently, I'm expecting that most patches that have been
> submitted during this week will be dropped from patchwork, which
> means submitting patches this week is likely not useful.
>
Ok I will send next revision as RFC to not increase the "load" but IMHO
it's worth to discuss this... I really feel we need to fix the PCS
situation ASAP or more driver will come. (there are already 3 in queue
as stressed in the cover letter)
--
Ansuel
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver
2025-03-19 16:03 ` Christian Marangi
@ 2025-03-19 16:26 ` Russell King (Oracle)
0 siblings, 0 replies; 34+ messages in thread
From: Russell King (Oracle) @ 2025-03-19 16:26 UTC (permalink / raw)
To: Christian Marangi
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Wed, Mar 19, 2025 at 05:03:15PM +0100, Christian Marangi wrote:
> On Wed, Mar 19, 2025 at 03:17:27PM +0000, Russell King (Oracle) wrote:
> > On Wed, Mar 19, 2025 at 12:58:38AM +0100, Christian Marangi wrote:
> > > Implement the foundation of OF support for PCS driver.
> > >
> > > To support this, implement a simple Provider API where a PCS driver can
> > > expose multiple PCS with an xlate .get function.
> > >
> > > PCS driver will have to call of_pcs_add_provider() and pass the device
> > > node pointer and a xlate function to return the correct PCS for the
> > > requested interface and the passed #pcs-cells.
> > >
> > > This will register the PCS in a global list of providers so that
> > > consumer can access it.
> > >
> > > Consumer will then use of_pcs_get() to get the actual PCS by passing the
> > > device_node pointer, the index for #pcs-cells and the requested
> > > interface.
> > >
> > > For simple implementation where #pcs-cells is 0 and the PCS driver
> > > expose a single PCS, the xlate function of_pcs_simple_get() is
> > > provided. In such case the passed interface is ignored and is expected
> > > that the PCS supports any interface mode supported by the MAC.
> > >
> > > For advanced implementation a custom xlate function is required. Such
> > > function should return an error if the PCS is not supported for the
> > > requested interface type.
> > >
> > > This is needed for the correct function of of_phylink_mac_select_pcs()
> > > later described.
> > >
> > > PCS driver on removal should first call phylink_pcs_release() on every
> > > PCS the driver provides and then correctly delete as a provider with
> > > the usage of of_pcs_del_provider().
> > >
> > > A generic function for .mac_select_pcs is provided for any MAC driver
> > > that will declare PCS in DT, of_phylink_mac_select_pcs().
> > > This function will parse "pcs-handle" property and will try every PCS
> > > declared in DT until one that supports the requested interface type is
> > > found. This works by leveraging the return value of the xlate function
> > > returned by of_pcs_get() and checking if it's an ERROR or NULL, in such
> > > case the next PCS in the phandle array is tested.
> > >
> > > Some additional helper are provided for xlate functions,
> > > pcs_supports_interface() as a simple function to check if the requested
> > > interface is supported by the PCS and phylink_pcs_release() to release a
> > > PCS from a phylink instance.
> > >
> > > Co-developed-by: Daniel Golle <daniel@makrotopia.org>
> > > Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> >
> > As a general comment, should we be developing stuff that is DT-centric
> > or fwnode-centric. We already have users of phylink using swnodes, and
> > it seems bad to design something today that is centred around just one
> > method of describing something.
> >
>
> Honestly, at least for me testing scenario different than DT is quite
> difficult, we can make changes to also support swnodes but we won't have
> anything to test them. Given the bad situation PCS is currently I feel
> we should first focus on DT or at least model something workable first
> than put even more complex stuff on the table.
The problem I have is that once we invent DT specific interfaces, we
seem to endlessly persist with them even when we have corresponding
fwnode interfaces, even when it's easy to convert.
So, my opinion today is that we should avoid single-firmware specific
interfaces.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 3/6] net: phylink: Correctly handle PCS probe defer from PCS provider
2025-03-19 16:18 ` Christian Marangi
@ 2025-03-19 17:02 ` Russell King (Oracle)
2025-03-19 17:35 ` Christian Marangi
0 siblings, 1 reply; 34+ messages in thread
From: Russell King (Oracle) @ 2025-03-19 17:02 UTC (permalink / raw)
To: Christian Marangi
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Wed, Mar 19, 2025 at 05:18:50PM +0100, Christian Marangi wrote:
> > > linkmode_fill(pl->supported);
> > > linkmode_copy(pl->link_config.advertising, pl->supported);
> > > - phylink_validate(pl, pl->supported, &pl->link_config);
> > > + ret = phylink_validate(pl, pl->supported, &pl->link_config);
> > > + /* The PCS might not available at the time phylink_create
> > > + * is called. Check this and communicate to the MAC driver
> > > + * that probe should be retried later.
> > > + *
> > > + * Notice that this can only happen in probe stage and PCS
> > > + * is expected to be avaialble in phylink_major_config.
> > > + */
> > > + if (ret == -EPROBE_DEFER) {
> > > + kfree(pl);
> > > + return ERR_PTR(ret);
> > > + }
> >
> > This does not solve the problem - what if the interface mode is
> > currently not one that requires a PCS that may not yet be probed?
>
> Mhhh but what are the actual real world scenario for this? If a MAC
> needs a dedicated PCS to handle multiple mode then it will probably
> follow this new implementation and register as a provider.
>
> An option to handle your corner case might be an OP that wait for each
> supported interface by the MAC and make sure there is a possible PCS for
> it. And Ideally place it in the codeflow of validate_pcs ?
I think you've fallen in to the trap of the stupid drivers that
implement mac_select_pcs() as:
static struct phylink_pcs *foo_mac_select_pcs(struct phylink_config *config,
phy_interface_t interface)
{
struct foo_private *priv = phylink_to_foo(config);
return priv->pcs;
}
but what drivers can (and should) be doing is looking at the interface
argument, and working out which interface to return.
Phylink is not designed to be single interface mode, single PCS driver
despite what many MAC drivers do. Checking the phylink_validate()
return code doesn't mean that all PCS exist for the MAC.
> > I don't like the idea that mac_select_pcs() might be doing a complex
> > lookup - that could make scanning the interface modes (as
> > phylink_validate_mask() does) quite slow and unreliable, and phylink
> > currently assumes that a PCS that is validated as present will remain
> > present.
>
> The assumption "will remain present" is already very fragile with the
> current PCS so I feel this should be changed or improved. Honestly every
> PCS currently implemented can be removed and phylink will stay in an
> undefined state.
The fragility is because of the way networking works - there's nothing
phylink can do about this.
I take issue with "every PCS currently implemented" because it's
actually not a correct statement.
XPCS as used by stmmac does not fall into this.
The PCS used by mvneta and mvpp2 do not fall into this.
The PCS used by the Marvell DSA driver do not fall into this.
It's only relatively recently with pcs-lynx and others that people have
wanted them to be separate driver-model devices that this problem has
occurred, and I've been pushing back on it saying we need to find a
proper solution to it. I really haven't liked that we've merged drivers
that cause this fragility without addressing that fragility.
I've got to the point where I'm now saying no to new drivers that fail
to address this, so we're at a crunch time when it needs to be
addressed.
We need to think about how to get around this fragility. The need to
pre-validate the link modes comes from the netdev ethtool user
interface itself - the need to tell userspace what link modes can be
supported _before_ they get used. This API hasn't been designed with
the idea that parts of a netdev might vanish at any particular time.
> > If it goes away by the time phylink_major_config() is called, then we
> > leave the phylink state no longer reflecting how the hardware is
> > programmed, but we still continue to call mac_link_up() - which should
> > probably be fixed.
>
> Again, the idea to prevent these kind of chicken-egg problem is to
> enforce correct removal on the PCS driver side.
>
> > Given that netdev is severely backlogged, I'm not inclined to add to
> > the netdev maintainers workloads by trying to fix this until after
> > the merge window - it looks like they're at least one week behind.
> > Consequently, I'm expecting that most patches that have been
> > submitted during this week will be dropped from patchwork, which
> > means submitting patches this week is likely not useful.
>
> Ok I will send next revision as RFC to not increase the "load" but IMHO
> it's worth to discuss this... I really feel we need to fix the PCS
> situation ASAP or more driver will come. (there are already 3 in queue
> as stressed in the cover letter)
Yes, we do need to fix it, but we need to recognise _all_ the issues
it creates by doing this, and how we handle it properly.
Right now, it's up to the MAC driver to get all the PCS it needs
during its probe function, and *not* in the mac_select_pcs() method
which has no way to propagate an error to anywhere sensible that
could handle an EPROBE_DEFER response.
My thoughts are that if a PCS goes away after a MAC driver has "got"
it, then:
1. we need to recognise that those PHY interfaces and/or link modes
are no longer available.
2. if the PCS was in-use, then the link needs to be taken down at
minimum and the .pcs_disable() method needs to be called to
release any resources that .pcs_enable() enabled (e.g. irq masks,
power enables, etc.)
3. the MAC driver needs to be notified that the PCS pointer it
stashed is no longer valid, so it doesn't return it for
mac_select_pcs().
There's probably a bunch more that needs to happen, and maybe need
to consider how to deal with "pcs came back".. but I haven't thought
that through yet.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver
2025-03-18 23:58 ` [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver Christian Marangi
` (2 preceding siblings ...)
2025-03-19 15:17 ` Russell King (Oracle)
@ 2025-03-19 17:05 ` kernel test robot
2025-04-01 20:59 ` Sean Anderson
4 siblings, 0 replies; 34+ messages in thread
From: kernel test robot @ 2025-03-19 17:05 UTC (permalink / raw)
To: Christian Marangi, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Russell King, Philipp Zabel,
Daniel Golle, devicetree, linux-kernel, upstream
Cc: oe-kbuild-all, netdev
Hi Christian,
kernel test robot noticed the following build warnings:
[auto build test WARNING on net-next/main]
url: https://github.com/intel-lab-lkp/linux/commits/Christian-Marangi/net-phylink-reset-PCS-Phylink-double-reference-on-phylink_stop/20250319-080303
base: net-next/main
patch link: https://lore.kernel.org/r/20250318235850.6411-3-ansuelsmth%40gmail.com
patch subject: [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver
config: i386-buildonly-randconfig-002-20250319 (https://download.01.org/0day-ci/archive/20250320/202503200045.AFf6buBJ-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250320/202503200045.AFf6buBJ-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503200045.AFf6buBJ-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/net/phy/phylink.c:989: warning: Function parameter or struct member 'pcs' not described in 'phylink_pcs_release'
>> drivers/net/phy/phylink.c:989: warning: Excess function parameter 'pl' description in 'phylink_pcs_release'
vim +989 drivers/net/phy/phylink.c
978
979 /**
980 * phylink_pcs_release() - release a PCS
981 * @pl: a pointer to &struct phylink_pcs
982 *
983 * PCS provider can use this to release a PCS from a phylink
984 * instance by stopping the attached netdev. This is only done
985 * if the PCS is actually attached to a phylink, otherwise is
986 * ignored.
987 */
988 void phylink_pcs_release(struct phylink_pcs *pcs)
> 989 {
990 struct phylink *pl = pcs->phylink;
991
992 if (pl) {
993 rtnl_lock();
994 dev_close(pl->netdev);
995 rtnl_unlock();
996 }
997 }
998 EXPORT_SYMBOL_GPL(phylink_pcs_release);
999
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF
2025-03-18 23:58 [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF Christian Marangi
` (5 preceding siblings ...)
2025-03-18 23:58 ` [net-next PATCH 6/6] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS Christian Marangi
@ 2025-03-19 17:29 ` Russell King (Oracle)
2025-03-19 17:44 ` Christian Marangi
2025-04-02 0:14 ` Sean Anderson
7 siblings, 1 reply; 34+ messages in thread
From: Russell King (Oracle) @ 2025-03-19 17:29 UTC (permalink / raw)
To: Christian Marangi
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Wed, Mar 19, 2025 at 12:58:36AM +0100, Christian Marangi wrote:
> A PCS provider have to implement and call of_pcs_add_provider() in
> probe function and define an xlate function to define how the PCS
> should be provided based on the requested interface and phandle spec
> defined in DT (based on the #pcs-cells)
>
> of_pcs_get() is provided to provide a specific PCS declared in DT
> an index.
>
> A simple xlate function is provided for simple single PCS
> implementation, of_pcs_simple_get.
>
> A PCS provider on driver removal should first call
> phylink_pcs_release() to release the PCS from phylink and then
> delete itself as a provider with of_pcs_del_provider() helper.
This is inherently racy.
phylink_pcs_release() may release the PCS from phylink, but there is a
window between calling this and of_pcs_del_provider() where it could
still be "got".
The sequence always has to be:
First, unpublish to prevent new uses.
Then remove from current uses.
Then disable hardware/remove resources.
It makes me exceedingly sad that we make keep implementing the same
mistakes time and time again - it was brought up at one of the OLS
conferences back in the 2000s, probably around the time that the
driver model was just becoming "a thing". At least I can pass on
this knowledge when I spot it and help others to improve!
Note that networking's unregister_netdev() recognises this pattern,
and unregister_netdev() will first unpublish the interface thereby
making it inaccessible to be brought up, then take the interface down
if it were up before returning - thus guaranteeing that when the
function returns, it is safe to dispose of any and all resources that
the driver was using.
Sorry as I seem to be labouring this point.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 3/6] net: phylink: Correctly handle PCS probe defer from PCS provider
2025-03-19 17:02 ` Russell King (Oracle)
@ 2025-03-19 17:35 ` Christian Marangi
2025-03-19 19:31 ` Russell King (Oracle)
0 siblings, 1 reply; 34+ messages in thread
From: Christian Marangi @ 2025-03-19 17:35 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Wed, Mar 19, 2025 at 05:02:50PM +0000, Russell King (Oracle) wrote:
> On Wed, Mar 19, 2025 at 05:18:50PM +0100, Christian Marangi wrote:
> > > > linkmode_fill(pl->supported);
> > > > linkmode_copy(pl->link_config.advertising, pl->supported);
> > > > - phylink_validate(pl, pl->supported, &pl->link_config);
> > > > + ret = phylink_validate(pl, pl->supported, &pl->link_config);
> > > > + /* The PCS might not available at the time phylink_create
> > > > + * is called. Check this and communicate to the MAC driver
> > > > + * that probe should be retried later.
> > > > + *
> > > > + * Notice that this can only happen in probe stage and PCS
> > > > + * is expected to be avaialble in phylink_major_config.
> > > > + */
> > > > + if (ret == -EPROBE_DEFER) {
> > > > + kfree(pl);
> > > > + return ERR_PTR(ret);
> > > > + }
> > >
> > > This does not solve the problem - what if the interface mode is
> > > currently not one that requires a PCS that may not yet be probed?
> >
> > Mhhh but what are the actual real world scenario for this? If a MAC
> > needs a dedicated PCS to handle multiple mode then it will probably
> > follow this new implementation and register as a provider.
> >
> > An option to handle your corner case might be an OP that wait for each
> > supported interface by the MAC and make sure there is a possible PCS for
> > it. And Ideally place it in the codeflow of validate_pcs ?
>
> I think you've fallen in to the trap of the stupid drivers that
> implement mac_select_pcs() as:
>
> static struct phylink_pcs *foo_mac_select_pcs(struct phylink_config *config,
> phy_interface_t interface)
> {
> struct foo_private *priv = phylink_to_foo(config);
>
> return priv->pcs;
> }
>
> but what drivers can (and should) be doing is looking at the interface
> argument, and working out which interface to return.
>
> Phylink is not designed to be single interface mode, single PCS driver
> despite what many MAC drivers do. Checking the phylink_validate()
> return code doesn't mean that all PCS exist for the MAC.
>
> > > I don't like the idea that mac_select_pcs() might be doing a complex
> > > lookup - that could make scanning the interface modes (as
> > > phylink_validate_mask() does) quite slow and unreliable, and phylink
> > > currently assumes that a PCS that is validated as present will remain
> > > present.
> >
> > The assumption "will remain present" is already very fragile with the
> > current PCS so I feel this should be changed or improved. Honestly every
> > PCS currently implemented can be removed and phylink will stay in an
> > undefined state.
>
> The fragility is because of the way networking works - there's nothing
> phylink can do about this.
>
> I take issue with "every PCS currently implemented" because it's
> actually not a correct statement.
>
> XPCS as used by stmmac does not fall into this.
> The PCS used by mvneta and mvpp2 do not fall into this.
> The PCS used by the Marvell DSA driver do not fall into this.
>
> It's only relatively recently with pcs-lynx and others that people have
> wanted them to be separate driver-model devices that this problem has
> occurred, and I've been pushing back on it saying we need to find a
> proper solution to it. I really haven't liked that we've merged drivers
> that cause this fragility without addressing that fragility.
>
> I've got to the point where I'm now saying no to new drivers that fail
> to address this, so we're at a crunch time when it needs to be
> addressed.
>
> We need to think about how to get around this fragility. The need to
> pre-validate the link modes comes from the netdev ethtool user
> interface itself - the need to tell userspace what link modes can be
> supported _before_ they get used. This API hasn't been designed with
> the idea that parts of a netdev might vanish at any particular time.
>
> > > If it goes away by the time phylink_major_config() is called, then we
> > > leave the phylink state no longer reflecting how the hardware is
> > > programmed, but we still continue to call mac_link_up() - which should
> > > probably be fixed.
> >
> > Again, the idea to prevent these kind of chicken-egg problem is to
> > enforce correct removal on the PCS driver side.
> >
> > > Given that netdev is severely backlogged, I'm not inclined to add to
> > > the netdev maintainers workloads by trying to fix this until after
> > > the merge window - it looks like they're at least one week behind.
> > > Consequently, I'm expecting that most patches that have been
> > > submitted during this week will be dropped from patchwork, which
> > > means submitting patches this week is likely not useful.
> >
> > Ok I will send next revision as RFC to not increase the "load" but IMHO
> > it's worth to discuss this... I really feel we need to fix the PCS
> > situation ASAP or more driver will come. (there are already 3 in queue
> > as stressed in the cover letter)
>
> Yes, we do need to fix it, but we need to recognise _all_ the issues
> it creates by doing this, and how we handle it properly.
>
> Right now, it's up to the MAC driver to get all the PCS it needs
> during its probe function, and *not* in the mac_select_pcs() method
> which has no way to propagate an error to anywhere sensible that
> could handle an EPROBE_DEFER response.
>
> My thoughts are that if a PCS goes away after a MAC driver has "got"
> it, then:
>
> 1. we need to recognise that those PHY interfaces and/or link modes
> are no longer available.
> 2. if the PCS was in-use, then the link needs to be taken down at
> minimum and the .pcs_disable() method needs to be called to
> release any resources that .pcs_enable() enabled (e.g. irq masks,
> power enables, etc.)
> 3. the MAC driver needs to be notified that the PCS pointer it
> stashed is no longer valid, so it doesn't return it for
> mac_select_pcs().
But why we need all these indirect handling and checks if we can
make use of .remove and shutdown the interface. A removal of a PCS
should cause the entire link to go down, isn't a dev_close enough to
propagate this? If and when the interface will came up checks are done
again and it will fail to go UP if PCS can't be found.
I know it's a drastic approach to call dev_close but link is down anyway
so lets reinit everything from scratch. It should handle point 2 and 3
right?
For point 1, additional entry like available_interface? And gets updated
once a PCS gets removed??? Or if we don't like the parsing hell we map
every interface to a PCS pointer? (not worth the wasted space IMHO)
>
> There's probably a bunch more that needs to happen, and maybe need
> to consider how to deal with "pcs came back".. but I haven't thought
> that through yet.
>
Current approach supports PCS came back as we check the global provider
list and the PCS is reachable again there.
(we tasted various scenario with unbind/bind while the interface was
up/down)
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
--
Ansuel
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF
2025-03-19 17:29 ` [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF Russell King (Oracle)
@ 2025-03-19 17:44 ` Christian Marangi
0 siblings, 0 replies; 34+ messages in thread
From: Christian Marangi @ 2025-03-19 17:44 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Wed, Mar 19, 2025 at 05:29:34PM +0000, Russell King (Oracle) wrote:
> On Wed, Mar 19, 2025 at 12:58:36AM +0100, Christian Marangi wrote:
> > A PCS provider have to implement and call of_pcs_add_provider() in
> > probe function and define an xlate function to define how the PCS
> > should be provided based on the requested interface and phandle spec
> > defined in DT (based on the #pcs-cells)
> >
> > of_pcs_get() is provided to provide a specific PCS declared in DT
> > an index.
> >
> > A simple xlate function is provided for simple single PCS
> > implementation, of_pcs_simple_get.
> >
> > A PCS provider on driver removal should first call
> > phylink_pcs_release() to release the PCS from phylink and then
> > delete itself as a provider with of_pcs_del_provider() helper.
>
> This is inherently racy.
>
> phylink_pcs_release() may release the PCS from phylink, but there is a
> window between calling this and of_pcs_del_provider() where it could
> still be "got".
Ah I hoped the rtnl lock would protect from this. I need to check if
unpublish first cause any harm, in theory no as phylink should still
have his pointer to the pcs struct and select_pcs should not be called
on interface removal.
But this can also be handled by flagging a PCS as "to-be-removed" so
that it gets ignored if in this window it gets parsed by the PCS
provider API.
>
> The sequence always has to be:
>
> First, unpublish to prevent new uses.
> Then remove from current uses.
> Then disable hardware/remove resources.
>
> It makes me exceedingly sad that we make keep implementing the same
> mistakes time and time again - it was brought up at one of the OLS
> conferences back in the 2000s, probably around the time that the
> driver model was just becoming "a thing". At least I can pass on
> this knowledge when I spot it and help others to improve!
>
> Note that networking's unregister_netdev() recognises this pattern,
> and unregister_netdev() will first unpublish the interface thereby
> making it inaccessible to be brought up, then take the interface down
> if it were up before returning - thus guaranteeing that when the
> function returns, it is safe to dispose of any and all resources that
> the driver was using.
>
> Sorry as I seem to be labouring this point.
>
No problem, some subsystem are so complex that these info are pure gold
and gets lots after years, especially with global lock in place where
someone can think they are enough to handle everything.
--
Ansuel
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 3/6] net: phylink: Correctly handle PCS probe defer from PCS provider
2025-03-19 17:35 ` Christian Marangi
@ 2025-03-19 19:31 ` Russell King (Oracle)
2025-03-27 17:37 ` Christian Marangi
0 siblings, 1 reply; 34+ messages in thread
From: Russell King (Oracle) @ 2025-03-19 19:31 UTC (permalink / raw)
To: Christian Marangi
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Wed, Mar 19, 2025 at 06:35:21PM +0100, Christian Marangi wrote:
> On Wed, Mar 19, 2025 at 05:02:50PM +0000, Russell King (Oracle) wrote:
> > My thoughts are that if a PCS goes away after a MAC driver has "got"
> > it, then:
> >
> > 1. we need to recognise that those PHY interfaces and/or link modes
> > are no longer available.
> > 2. if the PCS was in-use, then the link needs to be taken down at
> > minimum and the .pcs_disable() method needs to be called to
> > release any resources that .pcs_enable() enabled (e.g. irq masks,
> > power enables, etc.)
> > 3. the MAC driver needs to be notified that the PCS pointer it
> > stashed is no longer valid, so it doesn't return it for
> > mac_select_pcs().
>
> But why we need all these indirect handling and checks if we can
> make use of .remove and shutdown the interface. A removal of a PCS
> should cause the entire link to go down, isn't a dev_close enough to
> propagate this? If and when the interface will came up checks are done
> again and it will fail to go UP if PCS can't be found.
>
> I know it's a drastic approach to call dev_close but link is down anyway
> so lets reinit everything from scratch. It should handle point 2 and 3
> right?
Let's look at what dev_close() does. This is how it's documented:
* dev_close() - shutdown an interface
* @dev: device to shutdown
*
* This function moves an active device into down state. A
* %NETDEV_GOING_DOWN is sent to the netdev notifier chain. The device
* is then deactivated and finally a %NETDEV_DOWN is sent to the notifier
* chain.
So, this is equivalent to userspace doing:
# ip li set dev ethX down
and nothing prevents userspace doing:
# ip li set dev ethX up
after that call to dev_close() has returned.
If this happens, then the netdev driver's .ndo_open will be called,
which will then call phylink_start(), and that will attempt to bring
the link back up. That will call .mac_select_pcs(), which _if_ the
PCS is still "published" means it is _still_ accessible.
So your call that results in dev_close() with the PCS still being
published is ineffectual.
It's *no* different from this crap in the stmmac driver:
stmmac_stop_all_dma(priv);
stmmac_mac_set(priv, priv->ioaddr, false);
unregister_netdev(ndev);
because *until* that unregister_netdev() call has completed, _userspace_
still has control over the netdev, and can do whatever it damn well
pleases.
Look, this is very very very simple.
If something is published to another part of the code, it is
discoverable, and it can be used or manipulated by new users.
If we wish to take something away, then first, it must be
unpublished to prevent new users discovering the resource. Then
existing users need to be dealt with in a safe way. Only at that
point can we be certain that there are no users, and thus the
underlying device begin to be torn down.
It's entirely logical!
> For point 1, additional entry like available_interface? And gets updated
> once a PCS gets removed??? Or if we don't like the parsing hell we map
> every interface to a PCS pointer? (not worth the wasted space IMHO)
At the moment, MAC drivers that I've updated will do things like:
phy_interface_or(priv->phylink_config.supported_interfaces,
priv->phylink_config.supported_interfaces,
pcs->supported_interfaces);
phylink_config.supported_interfaces is the set of interface modes that
the MAC _and_ PCS subsystem supports. It's not just the MAC, it's both
together.
So, if a PCS is going away, then clearing the interface modes that the
PCS was providing would make sense - but there's a problem here. What
if the PCS is a bought-in bit of IP where the driver supports many modes
but the MAC doesn't use it for all those modes. So... which interface
modes get cleared is up to the MAC driver to decide.
> > There's probably a bunch more that needs to happen, and maybe need
> > to consider how to deal with "pcs came back".. but I haven't thought
> > that through yet.
>
> Current approach supports PCS came back as we check the global provider
> list and the PCS is reachable again there.
> (we tasted various scenario with unbind/bind while the interface was
> up/down)
... because you look up the PCS in the mac_select_pcs() callback which
leads to a different race to what we have today, this time inside the
phylink code which thankfully phylink prints an error which is *NEVER*
supposed to happen.
Just trading one problem for another problem.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC
2025-03-18 23:58 ` [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC Christian Marangi
2025-03-19 9:13 ` Christian Marangi
@ 2025-03-19 20:41 ` kernel test robot
2025-03-20 1:54 ` kernel test robot
2025-03-21 6:35 ` kernel test robot
3 siblings, 0 replies; 34+ messages in thread
From: kernel test robot @ 2025-03-19 20:41 UTC (permalink / raw)
To: Christian Marangi, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Russell King, Philipp Zabel,
Daniel Golle, devicetree, linux-kernel, upstream
Cc: llvm, oe-kbuild-all, netdev
Hi Christian,
kernel test robot noticed the following build warnings:
[auto build test WARNING on net-next/main]
url: https://github.com/intel-lab-lkp/linux/commits/Christian-Marangi/net-phylink-reset-PCS-Phylink-double-reference-on-phylink_stop/20250319-080303
base: net-next/main
patch link: https://lore.kernel.org/r/20250318235850.6411-6-ansuelsmth%40gmail.com
patch subject: [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC
config: x86_64-randconfig-001-20250320 (https://download.01.org/0day-ci/archive/20250320/202503200442.3vYzyScu-lkp@intel.com/config)
compiler: clang version 20.1.0 (https://github.com/llvm/llvm-project 24a30daaa559829ad079f2ff7f73eb4e18095f88)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250320/202503200442.3vYzyScu-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503200442.3vYzyScu-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/net/pcs/pcs-airoha.c:2542:2: warning: unannotated fall-through between switch labels [-Wimplicit-fallthrough]
2542 | default:
| ^
drivers/net/pcs/pcs-airoha.c:2542:2: note: insert '__attribute__((fallthrough));' to silence this warning
2542 | default:
| ^
| __attribute__((fallthrough));
drivers/net/pcs/pcs-airoha.c:2542:2: note: insert 'break;' to avoid fall-through
2542 | default:
| ^
| break;
1 warning generated.
vim +2542 drivers/net/pcs/pcs-airoha.c
2521
2522 static void airoha_pcs_an_restart(struct phylink_pcs *pcs)
2523 {
2524 struct airoha_pcs_priv *priv = phylink_pcs_to_airoha_pcs_port(pcs);
2525
2526 switch (priv->interface) {
2527 case PHY_INTERFACE_MODE_SGMII:
2528 case PHY_INTERFACE_MODE_1000BASEX:
2529 case PHY_INTERFACE_MODE_2500BASEX:
2530 regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
2531 AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
2532 udelay(3);
2533 regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
2534 AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART);
2535 break;
2536 case PHY_INTERFACE_MODE_USXGMII:
2537 regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
2538 AIROHA_PCS_USXGMII_AN_RESTART);
2539 udelay(3);
2540 regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0,
2541 AIROHA_PCS_USXGMII_AN_RESTART);
> 2542 default:
2543 return;
2544 }
2545 }
2546
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC
2025-03-18 23:58 ` [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC Christian Marangi
2025-03-19 9:13 ` Christian Marangi
2025-03-19 20:41 ` kernel test robot
@ 2025-03-20 1:54 ` kernel test robot
2025-03-21 6:35 ` kernel test robot
3 siblings, 0 replies; 34+ messages in thread
From: kernel test robot @ 2025-03-20 1:54 UTC (permalink / raw)
To: Christian Marangi, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Russell King, Philipp Zabel,
Daniel Golle, devicetree, linux-kernel, upstream
Cc: oe-kbuild-all, netdev
Hi Christian,
kernel test robot noticed the following build warnings:
[auto build test WARNING on net-next/main]
url: https://github.com/intel-lab-lkp/linux/commits/Christian-Marangi/net-phylink-reset-PCS-Phylink-double-reference-on-phylink_stop/20250319-080303
base: net-next/main
patch link: https://lore.kernel.org/r/20250318235850.6411-6-ansuelsmth%40gmail.com
patch subject: [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC
config: arm64-randconfig-r132-20250320 (https://download.01.org/0day-ci/archive/20250320/202503200928.j6AEMrdf-lkp@intel.com/config)
compiler: clang version 21.0.0git (https://github.com/llvm/llvm-project 87916f8c32ebd8e284091db9b70339df57fd1e90)
reproduce: (https://download.01.org/0day-ci/archive/20250320/202503200928.j6AEMrdf-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503200928.j6AEMrdf-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/net/pcs/pcs-airoha.c:2723:14: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected void *base @@ got void [noderef] __iomem * @@
drivers/net/pcs/pcs-airoha.c:2723:14: sparse: expected void *base
drivers/net/pcs/pcs-airoha.c:2723:14: sparse: got void [noderef] __iomem *
>> drivers/net/pcs/pcs-airoha.c:2728:25: sparse: sparse: incorrect type in argument 3 (different address spaces) @@ expected void [noderef] __iomem *regs @@ got void *base @@
drivers/net/pcs/pcs-airoha.c:2728:25: sparse: expected void [noderef] __iomem *regs
drivers/net/pcs/pcs-airoha.c:2728:25: sparse: got void *base
drivers/net/pcs/pcs-airoha.c:2732:14: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected void *base @@ got void [noderef] __iomem * @@
drivers/net/pcs/pcs-airoha.c:2732:14: sparse: expected void *base
drivers/net/pcs/pcs-airoha.c:2732:14: sparse: got void [noderef] __iomem *
drivers/net/pcs/pcs-airoha.c:2737:27: sparse: sparse: incorrect type in argument 3 (different address spaces) @@ expected void [noderef] __iomem *regs @@ got void *base @@
drivers/net/pcs/pcs-airoha.c:2737:27: sparse: expected void [noderef] __iomem *regs
drivers/net/pcs/pcs-airoha.c:2737:27: sparse: got void *base
drivers/net/pcs/pcs-airoha.c:2741:14: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected void *base @@ got void [noderef] __iomem * @@
drivers/net/pcs/pcs-airoha.c:2741:14: sparse: expected void *base
drivers/net/pcs/pcs-airoha.c:2741:14: sparse: got void [noderef] __iomem *
drivers/net/pcs/pcs-airoha.c:2746:28: sparse: sparse: incorrect type in argument 3 (different address spaces) @@ expected void [noderef] __iomem *regs @@ got void *base @@
drivers/net/pcs/pcs-airoha.c:2746:28: sparse: expected void [noderef] __iomem *regs
drivers/net/pcs/pcs-airoha.c:2746:28: sparse: got void *base
drivers/net/pcs/pcs-airoha.c:2750:14: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected void *base @@ got void [noderef] __iomem * @@
drivers/net/pcs/pcs-airoha.c:2750:14: sparse: expected void *base
drivers/net/pcs/pcs-airoha.c:2750:14: sparse: got void [noderef] __iomem *
drivers/net/pcs/pcs-airoha.c:2755:33: sparse: sparse: incorrect type in argument 3 (different address spaces) @@ expected void [noderef] __iomem *regs @@ got void *base @@
drivers/net/pcs/pcs-airoha.c:2755:33: sparse: expected void [noderef] __iomem *regs
drivers/net/pcs/pcs-airoha.c:2755:33: sparse: got void *base
drivers/net/pcs/pcs-airoha.c:2759:14: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected void *base @@ got void [noderef] __iomem * @@
drivers/net/pcs/pcs-airoha.c:2759:14: sparse: expected void *base
drivers/net/pcs/pcs-airoha.c:2759:14: sparse: got void [noderef] __iomem *
drivers/net/pcs/pcs-airoha.c:2764:29: sparse: sparse: incorrect type in argument 3 (different address spaces) @@ expected void [noderef] __iomem *regs @@ got void *base @@
drivers/net/pcs/pcs-airoha.c:2764:29: sparse: expected void [noderef] __iomem *regs
drivers/net/pcs/pcs-airoha.c:2764:29: sparse: got void *base
drivers/net/pcs/pcs-airoha.c:2768:14: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected void *base @@ got void [noderef] __iomem * @@
drivers/net/pcs/pcs-airoha.c:2768:14: sparse: expected void *base
drivers/net/pcs/pcs-airoha.c:2768:14: sparse: got void [noderef] __iomem *
drivers/net/pcs/pcs-airoha.c:2773:29: sparse: sparse: incorrect type in argument 3 (different address spaces) @@ expected void [noderef] __iomem *regs @@ got void *base @@
drivers/net/pcs/pcs-airoha.c:2773:29: sparse: expected void [noderef] __iomem *regs
drivers/net/pcs/pcs-airoha.c:2773:29: sparse: got void *base
drivers/net/pcs/pcs-airoha.c:2777:14: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected void *base @@ got void [noderef] __iomem * @@
drivers/net/pcs/pcs-airoha.c:2777:14: sparse: expected void *base
drivers/net/pcs/pcs-airoha.c:2777:14: sparse: got void [noderef] __iomem *
drivers/net/pcs/pcs-airoha.c:2782:25: sparse: sparse: incorrect type in argument 3 (different address spaces) @@ expected void [noderef] __iomem *regs @@ got void *base @@
drivers/net/pcs/pcs-airoha.c:2782:25: sparse: expected void [noderef] __iomem *regs
drivers/net/pcs/pcs-airoha.c:2782:25: sparse: got void *base
drivers/net/pcs/pcs-airoha.c:2786:14: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected void *base @@ got void [noderef] __iomem * @@
drivers/net/pcs/pcs-airoha.c:2786:14: sparse: expected void *base
drivers/net/pcs/pcs-airoha.c:2786:14: sparse: got void [noderef] __iomem *
drivers/net/pcs/pcs-airoha.c:2791:25: sparse: sparse: incorrect type in argument 3 (different address spaces) @@ expected void [noderef] __iomem *regs @@ got void *base @@
drivers/net/pcs/pcs-airoha.c:2791:25: sparse: expected void [noderef] __iomem *regs
drivers/net/pcs/pcs-airoha.c:2791:25: sparse: got void *base
vim +2723 drivers/net/pcs/pcs-airoha.c
2707
2708 static int airoha_pcs_probe(struct platform_device *pdev)
2709 {
2710 struct regmap_config syscon_config = airoha_pcs_regmap_config;
2711 struct device *dev = &pdev->dev;
2712 struct airoha_pcs_priv *priv;
2713 void *base;
2714 int ret;
2715
2716 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2717 if (!priv)
2718 return -ENOMEM;
2719
2720 priv->dev = dev;
2721 priv->data = of_device_get_match_data(dev);
2722
> 2723 base = devm_platform_ioremap_resource_byname(pdev, "xfi_mac");
2724 if (IS_ERR(base))
2725 return PTR_ERR(base);
2726
2727 syscon_config.name = "xfi_mac";
> 2728 priv->xfi_mac = devm_regmap_init_mmio(dev, base, &syscon_config);
2729 if (IS_ERR(priv->xfi_mac))
2730 return PTR_ERR(priv->xfi_mac);
2731
2732 base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_an");
2733 if (IS_ERR(base))
2734 return PTR_ERR(base);
2735
2736 syscon_config.name = "hsgmii_an";
2737 priv->hsgmii_an = devm_regmap_init_mmio(dev, base, &syscon_config);
2738 if (IS_ERR(priv->hsgmii_an))
2739 return PTR_ERR(priv->hsgmii_an);
2740
2741 base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_pcs");
2742 if (IS_ERR(base))
2743 return PTR_ERR(base);
2744
2745 syscon_config.name = "hsgmii_pcs";
2746 priv->hsgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
2747 if (IS_ERR(priv->hsgmii_pcs))
2748 return PTR_ERR(priv->hsgmii_pcs);
2749
2750 base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_rate_adp");
2751 if (IS_ERR(base))
2752 return PTR_ERR(base);
2753
2754 syscon_config.name = "hsgmii_rate_adp";
2755 priv->hsgmii_rate_adp = devm_regmap_init_mmio(dev, base, &syscon_config);
2756 if (IS_ERR(priv->hsgmii_rate_adp))
2757 return PTR_ERR(priv->hsgmii_rate_adp);
2758
2759 base = devm_platform_ioremap_resource_byname(pdev, "multi_sgmii");
2760 if (IS_ERR(base))
2761 return PTR_ERR(base);
2762
2763 syscon_config.name = "multi_sgmii";
2764 priv->multi_sgmii = devm_regmap_init_mmio(dev, base, &syscon_config);
2765 if (IS_ERR(priv->multi_sgmii))
2766 return PTR_ERR(priv->multi_sgmii);
2767
2768 base = devm_platform_ioremap_resource_byname(pdev, "usxgmii");
2769 if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
2770 return PTR_ERR(base);
2771
2772 syscon_config.name = "usxgmii";
2773 priv->usxgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
2774 if (IS_ERR(priv->usxgmii_pcs))
2775 return PTR_ERR(priv->usxgmii_pcs);
2776
2777 base = devm_platform_ioremap_resource_byname(pdev, "xfi_pma");
2778 if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
2779 return PTR_ERR(base);
2780
2781 syscon_config.name = "xfi_pma";
2782 priv->xfi_pma = devm_regmap_init_mmio(dev, base, &syscon_config);
2783 if (IS_ERR(priv->xfi_pma))
2784 return PTR_ERR(priv->xfi_pma);
2785
2786 base = devm_platform_ioremap_resource_byname(pdev, "xfi_ana");
2787 if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
2788 return PTR_ERR(base);
2789
2790 syscon_config.name = "xfi_ana";
2791 priv->xfi_ana = devm_regmap_init_mmio(dev, base, &syscon_config);
2792 if (IS_ERR(priv->xfi_ana))
2793 return PTR_ERR(priv->xfi_ana);
2794
2795 /* SCU is used to toggle XFI or HSGMII in global SoC registers */
2796 priv->scu = syscon_regmap_lookup_by_compatible("airoha,en7581-scu");
2797 if (IS_ERR(priv->scu))
2798 return PTR_ERR(priv->scu);
2799
2800 priv->rsts[0].id = "mac";
2801 priv->rsts[1].id = "phy";
2802 ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(priv->rsts),
2803 priv->rsts);
2804 if (ret)
2805 return dev_err_probe(dev, ret, "failed to get bulk reset lines\n");
2806
2807 platform_set_drvdata(pdev, priv);
2808
2809 priv->pcs.ops = &airoha_pcs_ops;
2810 priv->pcs.poll = true;
2811
2812 __set_bit(PHY_INTERFACE_MODE_SGMII, priv->pcs.supported_interfaces);
2813 __set_bit(PHY_INTERFACE_MODE_1000BASEX, priv->pcs.supported_interfaces);
2814 __set_bit(PHY_INTERFACE_MODE_2500BASEX, priv->pcs.supported_interfaces);
2815 __set_bit(PHY_INTERFACE_MODE_10GBASER, priv->pcs.supported_interfaces);
2816 __set_bit(PHY_INTERFACE_MODE_USXGMII, priv->pcs.supported_interfaces);
2817
2818 return of_pcs_add_provider(dev->of_node, of_pcs_simple_get,
2819 &priv->pcs);
2820 }
2821
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC
2025-03-18 23:58 ` [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC Christian Marangi
` (2 preceding siblings ...)
2025-03-20 1:54 ` kernel test robot
@ 2025-03-21 6:35 ` kernel test robot
3 siblings, 0 replies; 34+ messages in thread
From: kernel test robot @ 2025-03-21 6:35 UTC (permalink / raw)
To: Christian Marangi, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Russell King, Philipp Zabel,
Daniel Golle, devicetree, linux-kernel, upstream
Cc: llvm, oe-kbuild-all, netdev
Hi Christian,
kernel test robot noticed the following build errors:
[auto build test ERROR on net-next/main]
url: https://github.com/intel-lab-lkp/linux/commits/Christian-Marangi/net-phylink-reset-PCS-Phylink-double-reference-on-phylink_stop/20250319-080303
base: net-next/main
patch link: https://lore.kernel.org/r/20250318235850.6411-6-ansuelsmth%40gmail.com
patch subject: [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC
config: i386-randconfig-007-20250321 (https://download.01.org/0day-ci/archive/20250321/202503211416.eZCW1LF6-lkp@intel.com/config)
compiler: clang version 20.1.1 (https://github.com/llvm/llvm-project 424c2d9b7e4de40d0804dd374721e6411c27d1d1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250321/202503211416.eZCW1LF6-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503211416.eZCW1LF6-lkp@intel.com/
All errors (new ones prefixed by >>):
>> ld.lld: error: undefined symbol: of_pcs_simple_get
>>> referenced by pcs-airoha.c:2818 (drivers/net/pcs/pcs-airoha.c:2818)
>>> drivers/net/pcs/pcs-airoha.o:(airoha_pcs_probe) in archive vmlinux.a
--
>> ld.lld: error: undefined symbol: of_pcs_add_provider
>>> referenced by pcs-airoha.c:2818 (drivers/net/pcs/pcs-airoha.c:2818)
>>> drivers/net/pcs/pcs-airoha.o:(airoha_pcs_probe) in archive vmlinux.a
--
>> ld.lld: error: undefined symbol: of_pcs_del_provider
>>> referenced by pcs-airoha.c:2828 (drivers/net/pcs/pcs-airoha.c:2828)
>>> drivers/net/pcs/pcs-airoha.o:(airoha_pcs_remove) in archive vmlinux.a
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 4/6] dt-bindings: net: ethernet-controller: permit to define multiple PCS
2025-03-18 23:58 ` [net-next PATCH 4/6] dt-bindings: net: ethernet-controller: permit to define multiple PCS Christian Marangi
@ 2025-03-21 16:18 ` Rob Herring
2025-03-27 15:49 ` Christian Marangi
0 siblings, 1 reply; 34+ messages in thread
From: Rob Herring @ 2025-03-21 16:18 UTC (permalink / raw)
To: Christian Marangi
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Krzysztof Kozlowski, Conor Dooley, Heiner Kallweit,
Russell King, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Wed, Mar 19, 2025 at 12:58:40AM +0100, Christian Marangi wrote:
> Drop the limitation of a single PCS in pcs-handle property. Multiple PCS
> can be defined for an ethrnet-controller node to support various PHY
typo
> interface mode type.
What limitation? It already supports multiple PCS phandles. It doesn't
support arg cells. If you want that, either you have to fix the number
of cells or define a #pcs-handle-cells property. You've done neither
here.
Adding #pcs-handle-cells will also require some updates to the dtschema
tools.
>
> It's very common for SoCs to have a dedicated PCS for SGMII mode and one
> for USXGMII mode.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> Documentation/devicetree/bindings/net/ethernet-controller.yaml | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
> index 45819b235800..a260ab8e056e 100644
> --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
> +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
> @@ -110,8 +110,6 @@ properties:
>
> pcs-handle:
> $ref: /schemas/types.yaml#/definitions/phandle-array
> - items:
> - maxItems: 1
> description:
> Specifies a reference to a node representing a PCS PHY device on a MDIO
> bus to link with an external PHY (phy-handle) if exists.
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 6/6] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS
2025-03-18 23:58 ` [net-next PATCH 6/6] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS Christian Marangi
@ 2025-03-21 16:22 ` Rob Herring
0 siblings, 0 replies; 34+ messages in thread
From: Rob Herring @ 2025-03-21 16:22 UTC (permalink / raw)
To: Christian Marangi
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Krzysztof Kozlowski, Conor Dooley, Heiner Kallweit,
Russell King, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Wed, Mar 19, 2025 at 12:58:42AM +0100, Christian Marangi wrote:
> Document support for Airoha Ethernet PCS for AN7581 SoC.
>
> Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
> the various Serdes port supporting different Media Independent Interface
> (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
>
> This follow the new PCS provider with the use of #pcs-cells property.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> .../bindings/net/pcs/airoha,pcs.yaml | 112 ++++++++++++++++++
> 1 file changed, 112 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
> new file mode 100644
> index 000000000000..8bcf7757c728
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
> @@ -0,0 +1,112 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Airoha Ethernet PCS and Serdes
> +
> +maintainers:
> + - Christian Marangi <ansuelsmth@gmail.com>
> +
> +description:
> + Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
> + the various Serdes port supporting different Media Independent Interface
> + (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
> +
> +properties:
> + compatible:
> + enum:
> + - airoha,an7581-pcs-eth
> + - airoha,an7581-pcs-pon
> +
> + reg:
> + items:
> + - description: XFI MAC reg
> + - description: HSGMII AN reg
> + - description: HSGMII PCS reg
> + - description: MULTI SGMII reg
> + - description: USXGMII reg
> + - description: HSGMII rate adaption reg
> + - description: XFI Analog register
Is that just 1 register? Or should be 'registers'?
Please be consistent with reg and register.
> + - description: XFI PMA (Physical Medium Attachment) register
> +
> + reg-names:
> + items:
> + - const: xfi_mac
> + - const: hsgmii_an
> + - const: hsgmii_pcs
> + - const: multi_sgmii
> + - const: usxgmii
> + - const: hsgmii_rate_adp
> + - const: xfi_ana
> + - const: xfi_pma
> +
> + resets:
> + items:
> + - description: MAC reset
> + - description: PHY reset
> +
> + reset-names:
> + items:
> + - const: mac
> + - const: phy
> +
> + "#pcs-cells":
> + const: 0
So you did add something. But why if you only need 0 cells? That was
what was already supported.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - resets
> + - reset-names
> + - "#pcs-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/reset/airoha,en7581-reset.h>
> +
> + pcs@1fa08000 {
> + compatible = "airoha,an7581-pcs-pon";
> + reg = <0x1fa08000 0x1000>,
> + <0x1fa80000 0x60>,
> + <0x1fa80a00 0x164>,
> + <0x1fa84000 0x450>,
> + <0x1fa85900 0x338>,
> + <0x1fa86000 0x300>,
> + <0x1fa8a000 0x1000>,
> + <0x1fa8b000 0x1000>;
> + reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
> + "multi_sgmii", "usxgmii",
> + "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
> +
> + resets = <&scuclk EN7581_XPON_MAC_RST>,
> + <&scuclk EN7581_XPON_PHY_RST>;
> + reset-names = "mac", "phy";
> +
> + #pcs-cells = <0>;
> + };
> +
> + pcs@1fa09000 {
> + compatible = "airoha,an7581-pcs-eth";
> + reg = <0x1fa09000 0x1000>,
> + <0x1fa70000 0x60>,
> + <0x1fa70a00 0x164>,
> + <0x1fa74000 0x450>,
> + <0x1fa75900 0x338>,
> + <0x1fa76000 0x300>,
> + <0x1fa7a000 0x1000>,
> + <0x1fa7b000 0x1000>;
> + reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
> + "multi_sgmii", "usxgmii",
> + "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
> +
> + resets = <&scuclk EN7581_XSI_MAC_RST>,
> + <&scuclk EN7581_XSI_PHY_RST>;
> + reset-names = "mac", "phy";
> +
> + #pcs-cells = <0>;
> + };
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 4/6] dt-bindings: net: ethernet-controller: permit to define multiple PCS
2025-03-21 16:18 ` Rob Herring
@ 2025-03-27 15:49 ` Christian Marangi
2025-04-01 20:12 ` Sean Anderson
0 siblings, 1 reply; 34+ messages in thread
From: Christian Marangi @ 2025-03-27 15:49 UTC (permalink / raw)
To: Rob Herring
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Krzysztof Kozlowski, Conor Dooley, Heiner Kallweit,
Russell King, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Fri, Mar 21, 2025 at 11:18:12AM -0500, Rob Herring wrote:
> On Wed, Mar 19, 2025 at 12:58:40AM +0100, Christian Marangi wrote:
> > Drop the limitation of a single PCS in pcs-handle property. Multiple PCS
> > can be defined for an ethrnet-controller node to support various PHY
>
> typo
>
> > interface mode type.
>
> What limitation? It already supports multiple PCS phandles. It doesn't
> support arg cells. If you want that, either you have to fix the number
> of cells or define a #pcs-handle-cells property. You've done neither
> here.
>
> Adding #pcs-handle-cells will also require some updates to the dtschema
> tools.
>
I might be confused by doesn't
pcs-handle:
items:
maxItems: 1
limit it to
pcs-handle = <&foo>;
and make it not valid
pcs-handle = <&foo1>, <&foo2>;
?
The cells property will come but only when there will be an actual user
for it (I assume QCOM PCS will make use of it)
> >
> > It's very common for SoCs to have a dedicated PCS for SGMII mode and one
> > for USXGMII mode.
> >
> > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> > ---
> > Documentation/devicetree/bindings/net/ethernet-controller.yaml | 2 --
> > 1 file changed, 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
> > index 45819b235800..a260ab8e056e 100644
> > --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
> > +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
> > @@ -110,8 +110,6 @@ properties:
> >
> > pcs-handle:
> > $ref: /schemas/types.yaml#/definitions/phandle-array
> > - items:
> > - maxItems: 1
> > description:
> > Specifies a reference to a node representing a PCS PHY device on a MDIO
> > bus to link with an external PHY (phy-handle) if exists.
> > --
> > 2.48.1
> >
--
Ansuel
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 3/6] net: phylink: Correctly handle PCS probe defer from PCS provider
2025-03-19 19:31 ` Russell King (Oracle)
@ 2025-03-27 17:37 ` Christian Marangi
2025-03-27 18:08 ` Russell King (Oracle)
2025-03-28 8:59 ` Russell King (Oracle)
0 siblings, 2 replies; 34+ messages in thread
From: Christian Marangi @ 2025-03-27 17:37 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Wed, Mar 19, 2025 at 07:31:04PM +0000, Russell King (Oracle) wrote:
> On Wed, Mar 19, 2025 at 06:35:21PM +0100, Christian Marangi wrote:
> > On Wed, Mar 19, 2025 at 05:02:50PM +0000, Russell King (Oracle) wrote:
> > > My thoughts are that if a PCS goes away after a MAC driver has "got"
> > > it, then:
> > >
> > > 1. we need to recognise that those PHY interfaces and/or link modes
> > > are no longer available.
> > > 2. if the PCS was in-use, then the link needs to be taken down at
> > > minimum and the .pcs_disable() method needs to be called to
> > > release any resources that .pcs_enable() enabled (e.g. irq masks,
> > > power enables, etc.)
> > > 3. the MAC driver needs to be notified that the PCS pointer it
> > > stashed is no longer valid, so it doesn't return it for
> > > mac_select_pcs().
> >
> > But why we need all these indirect handling and checks if we can
> > make use of .remove and shutdown the interface. A removal of a PCS
> > should cause the entire link to go down, isn't a dev_close enough to
> > propagate this? If and when the interface will came up checks are done
> > again and it will fail to go UP if PCS can't be found.
> >
> > I know it's a drastic approach to call dev_close but link is down anyway
> > so lets reinit everything from scratch. It should handle point 2 and 3
> > right?
>
> Let's look at what dev_close() does. This is how it's documented:
>
> * dev_close() - shutdown an interface
> * @dev: device to shutdown
> *
> * This function moves an active device into down state. A
> * %NETDEV_GOING_DOWN is sent to the netdev notifier chain. The device
> * is then deactivated and finally a %NETDEV_DOWN is sent to the notifier
> * chain.
>
> So, this is equivalent to userspace doing:
>
> # ip li set dev ethX down
>
> and nothing prevents userspace doing:
>
> # ip li set dev ethX up
>
> after that call to dev_close() has returned.
>
> If this happens, then the netdev driver's .ndo_open will be called,
> which will then call phylink_start(), and that will attempt to bring
> the link back up. That will call .mac_select_pcs(), which _if_ the
> PCS is still "published" means it is _still_ accessible.
>
> So your call that results in dev_close() with the PCS still being
> published is ineffectual.
>
> It's *no* different from this crap in the stmmac driver:
>
> stmmac_stop_all_dma(priv);
> stmmac_mac_set(priv, priv->ioaddr, false);
> unregister_netdev(ndev);
>
> because *until* that unregister_netdev() call has completed, _userspace_
> still has control over the netdev, and can do whatever it damn well
> pleases.
>
> Look, this is very very very simple.
>
> If something is published to another part of the code, it is
> discoverable, and it can be used or manipulated by new users.
>
> If we wish to take something away, then first, it must be
> unpublished to prevent new users discovering the resource. Then
> existing users need to be dealt with in a safe way. Only at that
> point can we be certain that there are no users, and thus the
> underlying device begin to be torn down.
>
> It's entirely logical!
>
OK so (I think this was also suggested in the more specific PCS patch)
- 1. unpublish the PCS from the provider
- 2. put down the link...
I feel point 2 is the big effort here to solve. Mainly your problem is
the fact that phylink_major_config should not handle PROBE_DEFER and
should always have all the expected PCS available. (returned from
mac_select_pcs)
So the validation MUST ALWAYS be done before reaching that code path.
That means that when a PCS is removed, the entire phylink should be
refreshed and reevaluated. And at the same time lock userspace from
doing anything fancy (as there might be a possibility for
phylink_major_config)
Daniel at some point in the brainstorm process suggested that we might
need something like phylink_impair() to lock it while it's getting
""refreshed"". Do you think that might be a good path for this?
One of the first implementation of this called phylink_stop (not
dev_stop) so maybe I should reconsider keeping everything phylink
related. But that wouldn't put the interface down from userspace if I'm
not wrong.
It's point 3 (of the old list) "the MAC driver needs to be notified that
the PCS pointer it stashed is no longer valid, so it doesn't return it for
mac_select_pcs()." my problem. I still feel MAC should not track PCS but
only react on the presence (or absence) of them.
And this point is really connected to point 1 so I guess point 1 is the
first to handle, before this. (I also feel it will magically solved once
point 1 is handled)
> > For point 1, additional entry like available_interface? And gets updated
> > once a PCS gets removed??? Or if we don't like the parsing hell we map
> > every interface to a PCS pointer? (not worth the wasted space IMHO)
>
> At the moment, MAC drivers that I've updated will do things like:
>
> phy_interface_or(priv->phylink_config.supported_interfaces,
> priv->phylink_config.supported_interfaces,
> pcs->supported_interfaces);
>
> phylink_config.supported_interfaces is the set of interface modes that
> the MAC _and_ PCS subsystem supports. It's not just the MAC, it's both
> together.
>
> So, if a PCS is going away, then clearing the interface modes that the
> PCS was providing would make sense - but there's a problem here. What
> if the PCS is a bought-in bit of IP where the driver supports many modes
> but the MAC doesn't use it for all those modes. So... which interface
> modes get cleared is up to the MAC driver to decide.
>
Should we add an OP to handle removal of PCS from a MAC? Like
.mac_release_pcs ? I might be wrong but isn't that giving too much
freedom to the driver?
I need to recheck how the interface validation work and what values are
used but with this removal thing on the table, supported_interfaces OR
with the PCS supported_interface might be problematic and maybe the
original values should be stored somewhere.
> > > There's probably a bunch more that needs to happen, and maybe need
> > > to consider how to deal with "pcs came back".. but I haven't thought
> > > that through yet.
> >
> > Current approach supports PCS came back as we check the global provider
> > list and the PCS is reachable again there.
> > (we tasted various scenario with unbind/bind while the interface was
> > up/down)
>
> ... because you look up the PCS in the mac_select_pcs() callback which
> leads to a different race to what we have today, this time inside the
> phylink code which thankfully phylink prints an error which is *NEVER*
> supposed to happen.
>
I want to make sure tho you are ok with the usage of .mac_select_pcs
for re-evaluation task.
Maybe a better approach is to introduce .mac_get_pcs and enforce the
usage only on validation phase? (aka in phylink_validate_mac_and_pcs)
AFAIK in that phase .mac_select_pcs can return errors if the requested
interface is not possible for one reason or another.
What do you think? In short 2 additional OP that with the select one
result in:
- get
- select
- release
--
Ansuel
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 3/6] net: phylink: Correctly handle PCS probe defer from PCS provider
2025-03-27 17:37 ` Christian Marangi
@ 2025-03-27 18:08 ` Russell King (Oracle)
2025-03-28 8:59 ` Russell King (Oracle)
1 sibling, 0 replies; 34+ messages in thread
From: Russell King (Oracle) @ 2025-03-27 18:08 UTC (permalink / raw)
To: Christian Marangi
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Thu, Mar 27, 2025 at 06:37:19PM +0100, Christian Marangi wrote:
> OK so (I think this was also suggested in the more specific PCS patch)
> - 1. unpublish the PCS from the provider
> - 2. put down the link...
>
> I feel point 2 is the big effort here to solve. Mainly your problem is
> the fact that phylink_major_config should not handle PROBE_DEFER and
> should always have all the expected PCS available. (returned from
> mac_select_pcs)
I'm going to do a quick reply here, because I'm on a high latency LTE
connection right now (seems Three's backhaul network for downstream is
being overloaded.)
I mad ea comment previously, and implemented it:
https://lore.kernel.org/r/E1twkqO-0006FI-Gm@rmk-PC.armlinux.org.uk
Remainder too painful to try and reply to at the moment.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 3/6] net: phylink: Correctly handle PCS probe defer from PCS provider
2025-03-27 17:37 ` Christian Marangi
2025-03-27 18:08 ` Russell King (Oracle)
@ 2025-03-28 8:59 ` Russell King (Oracle)
1 sibling, 0 replies; 34+ messages in thread
From: Russell King (Oracle) @ 2025-03-28 8:59 UTC (permalink / raw)
To: Christian Marangi
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On Thu, Mar 27, 2025 at 06:37:19PM +0100, Christian Marangi wrote:
> On Wed, Mar 19, 2025 at 07:31:04PM +0000, Russell King (Oracle) wrote:
> > If we wish to take something away, then first, it must be
> > unpublished to prevent new users discovering the resource. Then
> > existing users need to be dealt with in a safe way. Only at that
> > point can we be certain that there are no users, and thus the
> > underlying device begin to be torn down.
> >
> > It's entirely logical!
>
> OK so (I think this was also suggested in the more specific PCS patch)
> - 1. unpublish the PCS from the provider
> - 2. put down the link...
>
> I feel point 2 is the big effort here to solve. Mainly your problem is
> the fact that phylink_major_config should not handle PROBE_DEFER and
> should always have all the expected PCS available. (returned from
> mac_select_pcs)
>
> So the validation MUST ALWAYS be done before reaching that code path.
Yes, but there's a sting in the tail - e.g. if we take away link modes
that are advertised on some media by a PCS going away.
Here's a theoretical situation:
- separate PCS for SGMII and 10GBASE-R with their own drivers, muxed
onto the same pins.
- PHY which switches its host interface between these two modes.
when both PCS are available, the PHY could be advertising 10base-T,
100base-Tx, 1000base-T and 10000base-T.
If one of these two PCS drivers becomes no longer available, then we
need to revalidate and update the PHY's advertisement.
> That means that when a PCS is removed, the entire phylink should be
> refreshed and reevaluated. And at the same time lock userspace from
> doing anything fancy (as there might be a possibility for
> phylink_major_config)
Taking the rtnl lock prevents userspace interfering with the interface
configuration.
> Daniel at some point in the brainstorm process suggested that we might
> need something like phylink_impair() to lock it while it's getting
> ""refreshed"". Do you think that might be a good path for this?
Taking the rtnl should be sufficient.
> One of the first implementation of this called phylink_stop (not
> dev_stop) so maybe I should reconsider keeping everything phylink
> related. But that wouldn't put the interface down from userspace if I'm
> not wrong.
>
> It's point 3 (of the old list) "the MAC driver needs to be notified that
> the PCS pointer it stashed is no longer valid, so it doesn't return it for
> mac_select_pcs()." my problem. I still feel MAC should not track PCS but
> only react on the presence (or absence) of them.
>
> And this point is really connected to point 1 so I guess point 1 is the
> first to handle, before this. (I also feel it will magically solved once
> point 1 is handled)
I'm wondering whether the mac_select_pcs() interface needs to be
revised - it's going to be difficult to do because there's many drivers
that blindly return a PCS irrespective of the interface mode.
I'm thinking that MAC drivers should register a PCS against a set of
interface modes that it wants to use it for (the interface modes that
a PCS supports is not necessarily the interface modes a MAC driver
wants to use it for.) That means we could handle mac_select_pcs()
entirely within phylink, which avoids storing PCS pointers in the MAC
driver.
I don't think this fully addresses the issues though.
However..
> > > For point 1, additional entry like available_interface? And gets updated
> > > once a PCS gets removed??? Or if we don't like the parsing hell we map
> > > every interface to a PCS pointer? (not worth the wasted space IMHO)
> >
> > At the moment, MAC drivers that I've updated will do things like:
> >
> > phy_interface_or(priv->phylink_config.supported_interfaces,
> > priv->phylink_config.supported_interfaces,
> > pcs->supported_interfaces);
> >
> > phylink_config.supported_interfaces is the set of interface modes that
> > the MAC _and_ PCS subsystem supports. It's not just the MAC, it's both
> > together.
> >
> > So, if a PCS is going away, then clearing the interface modes that the
> > PCS was providing would make sense - but there's a problem here. What
> > if the PCS is a bought-in bit of IP where the driver supports many modes
> > but the MAC doesn't use it for all those modes. So... which interface
> > modes get cleared is up to the MAC driver to decide.
.. we would then know which modes to clear from
phylink_config.supported_interfaces.
> Should we add an OP to handle removal of PCS from a MAC? Like
> .mac_release_pcs ? I might be wrong but isn't that giving too much
> freedom to the driver?
>
> I need to recheck how the interface validation work and what values are
> used but with this removal thing on the table, supported_interfaces OR
> with the PCS supported_interface might be problematic and maybe the
> original values should be stored somewhere.
That thought also crossed my mind too.
> > > > There's probably a bunch more that needs to happen, and maybe need
> > > > to consider how to deal with "pcs came back".. but I haven't thought
> > > > that through yet.
> > >
> > > Current approach supports PCS came back as we check the global provider
> > > list and the PCS is reachable again there.
> > > (we tasted various scenario with unbind/bind while the interface was
> > > up/down)
> >
> > ... because you look up the PCS in the mac_select_pcs() callback which
> > leads to a different race to what we have today, this time inside the
> > phylink code which thankfully phylink prints an error which is *NEVER*
> > supposed to happen.
> >
>
> I want to make sure tho you are ok with the usage of .mac_select_pcs
> for re-evaluation task.
>
> Maybe a better approach is to introduce .mac_get_pcs and enforce the
> usage only on validation phase? (aka in phylink_validate_mac_and_pcs)
>
> AFAIK in that phase .mac_select_pcs can return errors if the requested
> interface is not possible for one reason or another.
The problem is that the validation phase could happen in the distant
past in relation to when we actually use the results.
Consider the above case with SGMII + 10GBASE-R. We're running at
10G speeds, so we're using the 10GBASE-R PCS, and have been running for
a year. The cabling deteriorates, and the PHY renegotiates switching to
1G speed now wanting to use the SGMII PCS but someone's removed the
driver! The validation would've happened before the 10G link came up
but the use is now a significant time in the future.
In that scenario, if the SGMII PCS driver is available, then switching
to 1G speed is possible. If the driver isn't available, then the result
is that the link has gone down. That's the same result if we stop
advertising the slower speeds - the PHY basically wouldn't be able to
establish link at a slower speed, so the link has gone down.
So, maybe than re-evaluate phylink, maybe just keep track of which
PHY interface modes we can no longer support, and if we attempt to
switch to one of those, force the link down. However, with:
f1ae32a709e0 ("net: phylink: force link down on major_config failure")
we now have the mechanics to do this - if mac_select_pcs returns an
error for the interface mode at major_config time, we force the link
down until such time that we do have a successful major configuration.
Maybe we should just rely on that rather than trying to do a full
re-evaluation and reprogram things like PHY advertisements.
Maybe in this case, we need a way to inform phylib - if I remember
correctly, there is a way to get the PHY to signal "remote fault" to
the link partner, and this kind of situation seems an ideal use, but
I'd need to check 802.3.
Yes, the MAC driver still needs to be aware of a PCS going away so it
can properly respond to mac_select_pcs().
Part of the issue here is that phylink wasn't designed from the start
to cope with PCS as separate drivers - it always assumed that the MAC
was in control of the PCS and would ensure that the PCS would remain
available. E.g. through a PCS specific create() method causing a direct
module relationship without the involvement of the driver model, or the
PCS driver being built-in to the MAC driver.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 4/6] dt-bindings: net: ethernet-controller: permit to define multiple PCS
2025-03-27 15:49 ` Christian Marangi
@ 2025-04-01 20:12 ` Sean Anderson
0 siblings, 0 replies; 34+ messages in thread
From: Sean Anderson @ 2025-04-01 20:12 UTC (permalink / raw)
To: Christian Marangi, Rob Herring
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Krzysztof Kozlowski, Conor Dooley, Heiner Kallweit,
Russell King, Philipp Zabel, Daniel Golle, netdev, devicetree,
linux-kernel, upstream
On 3/27/25 11:49, Christian Marangi wrote:
> On Fri, Mar 21, 2025 at 11:18:12AM -0500, Rob Herring wrote:
>> On Wed, Mar 19, 2025 at 12:58:40AM +0100, Christian Marangi wrote:
>> > Drop the limitation of a single PCS in pcs-handle property. Multiple PCS
>> > can be defined for an ethrnet-controller node to support various PHY
>>
>> typo
>>
>> > interface mode type.
>>
>> What limitation? It already supports multiple PCS phandles. It doesn't
>> support arg cells. If you want that, either you have to fix the number
>> of cells or define a #pcs-handle-cells property. You've done neither
>> here.
>>
>> Adding #pcs-handle-cells will also require some updates to the dtschema
>> tools.
>>
>
> I might be confused by doesn't
>
> pcs-handle:
> items:
> maxItems: 1
>
> limit it to
>
> pcs-handle = <&foo>;
>
> and make it not valid
>
> pcs-handle = <&foo1>, <&foo2>;
>
> ?
You should modify this in the MAC's devicetree. See
Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml for an
example.
> The cells property will come but only when there will be an actual user
> for it (I assume QCOM PCS will make use of it)
I think it would be better to add this as necessary.
--Sean
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver
2025-03-18 23:58 ` [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver Christian Marangi
` (3 preceding siblings ...)
2025-03-19 17:05 ` kernel test robot
@ 2025-04-01 20:59 ` Sean Anderson
4 siblings, 0 replies; 34+ messages in thread
From: Sean Anderson @ 2025-04-01 20:59 UTC (permalink / raw)
To: Christian Marangi, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Russell King, Philipp Zabel,
Daniel Golle, netdev, devicetree, linux-kernel, upstream
On 3/18/25 19:58, Christian Marangi wrote:
> Implement the foundation of OF support for PCS driver.
>
> To support this, implement a simple Provider API where a PCS driver can
> expose multiple PCS with an xlate .get function.
>
> PCS driver will have to call of_pcs_add_provider() and pass the device
> node pointer and a xlate function to return the correct PCS for the
> requested interface and the passed #pcs-cells.
>
> This will register the PCS in a global list of providers so that
> consumer can access it.
>
> Consumer will then use of_pcs_get() to get the actual PCS by passing the
> device_node pointer, the index for #pcs-cells and the requested
> interface.
>
> For simple implementation where #pcs-cells is 0 and the PCS driver
> expose a single PCS, the xlate function of_pcs_simple_get() is
> provided. In such case the passed interface is ignored and is expected
> that the PCS supports any interface mode supported by the MAC.
>
> For advanced implementation a custom xlate function is required. Such
> function should return an error if the PCS is not supported for the
> requested interface type.
>
> This is needed for the correct function of of_phylink_mac_select_pcs()
> later described.
>
> PCS driver on removal should first call phylink_pcs_release() on every
> PCS the driver provides and then correctly delete as a provider with
> the usage of of_pcs_del_provider().
>
> A generic function for .mac_select_pcs is provided for any MAC driver
> that will declare PCS in DT, of_phylink_mac_select_pcs().
> This function will parse "pcs-handle" property and will try every PCS
> declared in DT until one that supports the requested interface type is
> found. This works by leveraging the return value of the xlate function
> returned by of_pcs_get() and checking if it's an ERROR or NULL, in such
> case the next PCS in the phandle array is tested.
>
> Some additional helper are provided for xlate functions,
> pcs_supports_interface() as a simple function to check if the requested
> interface is supported by the PCS and phylink_pcs_release() to release a
> PCS from a phylink instance.
>
> Co-developed-by: Daniel Golle <daniel@makrotopia.org>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> drivers/net/pcs/Kconfig | 7 ++
> drivers/net/pcs/Makefile | 1 +
> drivers/net/pcs/pcs.c | 185 +++++++++++++++++++++++++++++++
> drivers/net/phy/phylink.c | 21 ++++
> include/linux/pcs/pcs-provider.h | 46 ++++++++
> include/linux/pcs/pcs.h | 62 +++++++++++
> include/linux/phylink.h | 2 +
> 7 files changed, 324 insertions(+)
> create mode 100644 drivers/net/pcs/pcs.c
> create mode 100644 include/linux/pcs/pcs-provider.h
> create mode 100644 include/linux/pcs/pcs.h
>
> diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
> index f6aa437473de..8c3b720de6fd 100644
> --- a/drivers/net/pcs/Kconfig
> +++ b/drivers/net/pcs/Kconfig
> @@ -5,6 +5,13 @@
>
> menu "PCS device drivers"
>
> +config OF_PCS
> + tristate
> + depends on OF
> + depends on PHYLINK
> + help
> + OpenFirmware PCS accessors
More than this, please.
> +
> config PCS_XPCS
> tristate "Synopsys DesignWare Ethernet XPCS"
> select PHYLINK
> diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
> index 4f7920618b90..29881f0f981f 100644
> --- a/drivers/net/pcs/Makefile
> +++ b/drivers/net/pcs/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
> # Makefile for Linux PCS drivers
>
> +obj-$(CONFIG_OF_PCS) += pcs.o
> pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
> pcs-xpcs-nxp.o pcs-xpcs-wx.o
>
> diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
> new file mode 100644
> index 000000000000..af04a76ef825
> --- /dev/null
> +++ b/drivers/net/pcs/pcs.c
> @@ -0,0 +1,185 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +
> +#include <linux/mutex.h>
> +#include <linux/of.h>
> +#include <linux/phylink.h>
> +#include <linux/pcs/pcs.h>
> +#include <linux/pcs/pcs-provider.h>
> +
> +struct of_pcs_provider {
> + struct list_head link;
> +
> + struct device_node *node;
> + struct phylink_pcs *(*get)(struct of_phandle_args *pcsspec,
> + void *data,
> + phy_interface_t interface);
I think it is better to register each PCS explicitly, as no driver needs
cells (yet). It simplifies the lookup and registration code.
> +
> + void *data;
> +};
> +
> +static LIST_HEAD(of_pcs_providers);
> +static DEFINE_MUTEX(of_pcs_mutex);
> +
> +struct phylink_pcs *of_pcs_simple_get(struct of_phandle_args *pcsspec, void *data,
> + phy_interface_t interface)
> +{
> + struct phylink_pcs *pcs = data;
> +
> + if (!pcs_supports_interface(pcs, interface))
> + return ERR_PTR(-EOPNOTSUPP);
> +
> + return data;
> +}
> +EXPORT_SYMBOL_GPL(of_pcs_simple_get);
> +
> +int of_pcs_add_provider(struct device_node *np,
> + struct phylink_pcs *(*get)(struct of_phandle_args *pcsspec,
> + void *data,
> + phy_interface_t interface),
> + void *data)
> +{
> + struct of_pcs_provider *pp;
> +
> + if (!np)
> + return 0;
> +
> + pp = kzalloc(sizeof(*pp), GFP_KERNEL);
> + if (!pp)
> + return -ENOMEM;
> +
> + pp->node = of_node_get(np);
> + pp->data = data;
> + pp->get = get;
> +
> + mutex_lock(&of_pcs_mutex);
> + list_add(&pp->link, &of_pcs_providers);
> + mutex_unlock(&of_pcs_mutex);
> + pr_debug("Added pcs provider from %pOF\n", np);
> +
> + fwnode_dev_initialized(&np->fwnode, true);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(of_pcs_add_provider);
> +
> +void of_pcs_del_provider(struct device_node *np)
> +{
> + struct of_pcs_provider *pp;
> +
> + if (!np)
> + return;
> +
> + mutex_lock(&of_pcs_mutex);
> + list_for_each_entry(pp, &of_pcs_providers, link) {
> + if (pp->node == np) {
> + list_del(&pp->link);
> + fwnode_dev_initialized(&np->fwnode, false);
> + of_node_put(pp->node);
> + kfree(pp);
> + break;
> + }
> + }
> + mutex_unlock(&of_pcs_mutex);
> +}
> +EXPORT_SYMBOL_GPL(of_pcs_del_provider);
> +
> +static int of_parse_pcsspec(const struct device_node *np, int index,
> + const char *name, struct of_phandle_args *out_args)
> +{
> + int ret = -ENOENT;
> +
> + if (!np)
> + return -ENOENT;
> +
> + if (name)
> + index = of_property_match_string(np, "pcs-names", name);
> +
> + ret = of_parse_phandle_with_args(np, "pcs-handle", "#pcs-cells",
> + index, out_args);
> + if (ret || (name && index < 0))
> + return ret;
> +
> + return 0;
> +}
> +
> +static struct phylink_pcs *
> +of_pcs_get_from_pcsspec(struct of_phandle_args *pcsspec,
> + phy_interface_t interface)
> +{
> + struct of_pcs_provider *provider;
> + struct phylink_pcs *pcs = ERR_PTR(-EPROBE_DEFER);
> +
> + if (!pcsspec)
> + return ERR_PTR(-EINVAL);
> +
> + mutex_lock(&of_pcs_mutex);
> + list_for_each_entry(provider, &of_pcs_providers, link) {
> + if (provider->node == pcsspec->np) {
> + pcs = provider->get(pcsspec, provider->data,
> + interface);
> + if (!IS_ERR(pcs))
> + break;
> + }
> + }
> + mutex_unlock(&of_pcs_mutex);
> +
> + return pcs;
> +}
> +
> +static struct phylink_pcs *__of_pcs_get(struct device_node *np, int index,
> + const char *con_id,
> + phy_interface_t interface)
> +{
> + struct of_phandle_args pcsspec;
> + struct phylink_pcs *pcs;
> + int ret;
> +
> + ret = of_parse_pcsspec(np, index, con_id, &pcsspec);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + pcs = of_pcs_get_from_pcsspec(&pcsspec, interface);
> + of_node_put(pcsspec.np);
> +
> + return pcs;
> +}
> +
> +struct phylink_pcs *of_pcs_get(struct device_node *np, int index,
> + phy_interface_t interface)
> +{
> + return __of_pcs_get(np, index, NULL, interface);
> +}
> +EXPORT_SYMBOL_GPL(of_pcs_get);
> +
> +struct phylink_pcs *of_phylink_mac_select_pcs(struct phylink_config *config,
> + phy_interface_t interface)
> +{
> + int i, count;
> + struct device *dev = config->dev;
> + struct device_node *np = dev->of_node;
> + struct phylink_pcs *pcs = ERR_PTR(-ENODEV);
> +
> + /* To enable using_mac_select_pcs on phylink_create */
> + if (interface == PHY_INTERFACE_MODE_NA)
> + return NULL;
> +
> + /* Reject configuring PCS with Internal mode */
> + if (interface == PHY_INTERFACE_MODE_INTERNAL)
> + return ERR_PTR(-EINVAL);
> +
> + if (!of_property_present(np, "pcs-handle"))
> + return pcs;
> +
> + count = of_count_phandle_with_args(np, "pcs-handle", "#pcs-cells");
You need to have a way for the MAC to specify a different phandle for
backwards-compatibility. There are several MACs that have different
names in existing devicetrees.
> + if (count < 0)
> + return ERR_PTR(count);
> +
> + for (i = 0; i < count; i++) {
> + pcs = of_pcs_get(np, i, interface);
> + if (!IS_ERR_OR_NULL(pcs))
As commented by others, this is really a bit late to get the PCS
and it complicates the error-handling. It is easier for drivers to get
the pcs in probe() (or some other setup), and
> + return pcs;
> + }
> +
> + return pcs;
> +}
> +EXPORT_SYMBOL_GPL(of_phylink_mac_select_pcs);
> diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
> index eef1712ec22c..7f71547e89fe 100644
> --- a/drivers/net/phy/phylink.c
> +++ b/drivers/net/phy/phylink.c
> @@ -1130,6 +1130,27 @@ int phylink_pcs_pre_init(struct phylink *pl, struct phylink_pcs *pcs)
> }
> EXPORT_SYMBOL_GPL(phylink_pcs_pre_init);
>
> +/**
> + * phylink_pcs_release() - release a PCS
> + * @pl: a pointer to &struct phylink_pcs
> + *
> + * PCS provider can use this to release a PCS from a phylink
> + * instance by stopping the attached netdev. This is only done
> + * if the PCS is actually attached to a phylink, otherwise is
> + * ignored.
> + */
> +void phylink_pcs_release(struct phylink_pcs *pcs)
> +{
> + struct phylink *pl = pcs->phylink;
> +
> + if (pl) {
> + rtnl_lock();
> + dev_close(pl->netdev);
> + rtnl_unlock();
What about pl->type == PHYLINK_DEV?
And if you race with mac_select_pcs?
This approach is untenable IMO.
--Sean
> + }
> +}
> +EXPORT_SYMBOL_GPL(phylink_pcs_release);
> +
> static void phylink_mac_config(struct phylink *pl,
> const struct phylink_link_state *state)
> {
> diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
> new file mode 100644
> index 000000000000..0172d0286f07
> --- /dev/null
> +++ b/include/linux/pcs/pcs-provider.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +#ifndef __LINUX_PCS_PROVIDER_H
> +#define __LINUX_PCS_PROVIDER_H
> +
> +#include <linux/phy.h>
> +
> +/**
> + * of_pcs_simple_get - Simple xlate function to retrieve PCS
> + * @pcsspec: Phandle arguments
> + * @data: Context data (assumed assigned to the single PCS)
> + * @interface: requested PHY interface type for PCS
> + *
> + * Returns the PCS (pointed by data) or an -EOPNOTSUPP pointer
> + * if the PCS doesn't support the requested interface.
> + */
> +struct phylink_pcs *of_pcs_simple_get(struct of_phandle_args *pcsspec, void *data,
> + phy_interface_t interface);
> +
> +/**
> + * of_pcs_add_provider - Registers a new PCS provider
> + * @np: Device node
> + * @get: xlate function to retrieve the PCS
> + * @data: Context data
> + *
> + * Register and add a new PCS to the global providers list
> + * for the device node. A function to get the PCS from
> + * device node with the use of phandle args.
> + * To the get function is also passed the interface type
> + * requested for the PHY. PCS driver will use the passed
> + * interface to understand if the PCS can support it or not.
> + *
> + * Returns 0 on success or -ENOMEM on allocation failure.
> + */
> +int of_pcs_add_provider(struct device_node *np,
> + struct phylink_pcs *(*get)(struct of_phandle_args *pcsspec,
> + void *data,
> + phy_interface_t interface),
> + void *data);
> +
> +/**
> + * of_pcs_del_provider - Removes a PCS provider
> + * @np: Device node
> + */
> +void of_pcs_del_provider(struct device_node *np);
> +
> +#endif /* __LINUX_PCS_PROVIDER_H */
> diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
> new file mode 100644
> index 000000000000..b681bf05ac08
> --- /dev/null
> +++ b/include/linux/pcs/pcs.h
> @@ -0,0 +1,62 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +#ifndef __LINUX_PCS_H
> +#define __LINUX_PCS_H
> +
> +#include <linux/phy.h>
> +#include <linux/phylink.h>
> +
> +static inline bool pcs_supports_interface(struct phylink_pcs *pcs,
> + phy_interface_t interface)
> +{
> + return test_bit(interface, pcs->supported_interfaces);
> +}
> +
> +#ifdef CONFIG_OF_PCS
> +/**
> + * of_pcs_get - Retrieves a PCS from a device node
> + * @np: Device node
> + * @index: Index of PCS handle in Device Node
> + * @interface: requested PHY interface type for PCS
> + *
> + * Get a PCS for the requested PHY interface type from the
> + * device node at index.
> + *
> + * Returns a pointer to the phylink_pcs or a negative
> + * error pointer. Can return -EPROBE_DEFER if the PCS is not
> + * present in global providers list (either due to driver
> + * still needs to be probed or it failed to probe/removed)
> + */
> +struct phylink_pcs *of_pcs_get(struct device_node *np, int index,
> + phy_interface_t interface);
> +
> +/**
> + * of_phylink_mac_select_pcs - Generic MAC select pcs for OF PCS provider
> + * @config: phylink config pointer
> + * @interface: requested PHY interface type for PCS
> + *
> + * Generic helper function to get a PCS from a "pcs-handle" OF property
> + * defined in device tree. Each phandle defined in "pcs-handle" will be
> + * tested until a PCS that supports the requested PHY interface is found.
> + *
> + * Returns a pointer to the selected PCS or an error pointer.
> + * Return NULL for PHY_INTERFACE_MODE_NA and a -EINVAL error pointer
> + * for PHY_INTERFACE_MODE_INTERNAL. It can also return -EPROBE_DEFER,
> + * refer to of_pcs_get for details about it.
> + */
> +struct phylink_pcs *of_phylink_mac_select_pcs(struct phylink_config *config,
> + phy_interface_t interface);
> +#else
> +static inline struct phylink_pcs *of_pcs_get(struct device_node *np, int index,
> + phy_interface_t interface)
> +{
> + return PTR_ERR(-ENOENT);
> +}
> +
> +static inline struct phylink_pcs *of_phylink_mac_select_pcs(struct phylink_config *config,
> + phy_interface_t interface)
> +{
> + return PTR_ERR(-EOPNOTSUPP);
> +}
> +#endif
> +
> +#endif /* __LINUX_PCS_H */
> diff --git a/include/linux/phylink.h b/include/linux/phylink.h
> index c187267a15b6..80367d4fbad9 100644
> --- a/include/linux/phylink.h
> +++ b/include/linux/phylink.h
> @@ -695,6 +695,8 @@ void phylink_pcs_change(struct phylink_pcs *, bool up);
>
> int phylink_pcs_pre_init(struct phylink *pl, struct phylink_pcs *pcs);
>
> +void phylink_pcs_release(struct phylink_pcs *pcs);
> +
> void phylink_start(struct phylink *);
> void phylink_stop(struct phylink *);
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF
2025-03-18 23:58 [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF Christian Marangi
` (6 preceding siblings ...)
2025-03-19 17:29 ` [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF Russell King (Oracle)
@ 2025-04-02 0:14 ` Sean Anderson
2025-04-02 15:08 ` Christian Marangi (Ansuel)
7 siblings, 1 reply; 34+ messages in thread
From: Sean Anderson @ 2025-04-02 0:14 UTC (permalink / raw)
To: Christian Marangi, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Russell King, Philipp Zabel,
Daniel Golle, netdev, devicetree, linux-kernel, upstream
Hi Christian,
On 3/18/25 19:58, Christian Marangi wrote:
> This series introduce a most awaited feature that is correctly
> provide PCS with OF without having to use specific export symbol.
I've actually been working on the same problem on and off over the past
several years [1,2]. I saw your patch series and it inspired me to clean
it up a bit [3]. The merge window is closed, so I can't post it (and I
still need to test the lynx conversion a bit more), but please feel free
to have a look.
--Sean
[1] https://lore.kernel.org/netdev/20211004191527.1610759-1-sean.anderson@seco.com/
[2] https://lore.kernel.org/netdev/20221103210650.2325784-1-sean.anderson@seco.com/
[3] https://github.com/sean-anderson-seco/linux/tree/pcs
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF
2025-04-02 0:14 ` Sean Anderson
@ 2025-04-02 15:08 ` Christian Marangi (Ansuel)
0 siblings, 0 replies; 34+ messages in thread
From: Christian Marangi (Ansuel) @ 2025-04-02 15:08 UTC (permalink / raw)
To: Sean Anderson
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiner Kallweit, Russell King, Philipp Zabel, Daniel Golle,
netdev, devicetree, linux-kernel, upstream
Il giorno mer 2 apr 2025 alle ore 02:14 Sean Anderson
<sean.anderson@seco.com> ha scritto:
>
> Hi Christian,
>
> On 3/18/25 19:58, Christian Marangi wrote:
> > This series introduce a most awaited feature that is correctly
> > provide PCS with OF without having to use specific export symbol.
>
> I've actually been working on the same problem on and off over the past
> several years [1,2]. I saw your patch series and it inspired me to clean
> it up a bit [3]. The merge window is closed, so I can't post it (and I
> still need to test the lynx conversion a bit more), but please feel free
> to have a look.
>
I'm working hard on v2 of this and will have major change, so I feel it's better
to wait for v2 before adding more ideas on the table.
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2025-04-02 15:09 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-03-18 23:58 [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF Christian Marangi
2025-03-18 23:58 ` [net-next PATCH 1/6] net: phylink: reset PCS-Phylink double reference on phylink_stop Christian Marangi
2025-03-18 23:58 ` [net-next PATCH 2/6] net: pcs: Implement OF support for PCS driver Christian Marangi
2025-03-19 9:11 ` Christian Marangi
2025-03-19 9:25 ` Christian Marangi
2025-03-19 15:17 ` Russell King (Oracle)
2025-03-19 16:03 ` Christian Marangi
2025-03-19 16:26 ` Russell King (Oracle)
2025-03-19 17:05 ` kernel test robot
2025-04-01 20:59 ` Sean Anderson
2025-03-18 23:58 ` [net-next PATCH 3/6] net: phylink: Correctly handle PCS probe defer from PCS provider Christian Marangi
2025-03-19 15:58 ` Russell King (Oracle)
2025-03-19 16:18 ` Christian Marangi
2025-03-19 17:02 ` Russell King (Oracle)
2025-03-19 17:35 ` Christian Marangi
2025-03-19 19:31 ` Russell King (Oracle)
2025-03-27 17:37 ` Christian Marangi
2025-03-27 18:08 ` Russell King (Oracle)
2025-03-28 8:59 ` Russell King (Oracle)
2025-03-18 23:58 ` [net-next PATCH 4/6] dt-bindings: net: ethernet-controller: permit to define multiple PCS Christian Marangi
2025-03-21 16:18 ` Rob Herring
2025-03-27 15:49 ` Christian Marangi
2025-04-01 20:12 ` Sean Anderson
2025-03-18 23:58 ` [net-next PATCH 5/6] net: pcs: airoha: add PCS driver for Airoha SoC Christian Marangi
2025-03-19 9:13 ` Christian Marangi
2025-03-19 20:41 ` kernel test robot
2025-03-20 1:54 ` kernel test robot
2025-03-21 6:35 ` kernel test robot
2025-03-18 23:58 ` [net-next PATCH 6/6] dt-bindings: net: pcs: Document support for Airoha Ethernet PCS Christian Marangi
2025-03-21 16:22 ` Rob Herring
2025-03-19 17:29 ` [net-next PATCH 0/6] net: pcs: Introduce support for PCS OF Russell King (Oracle)
2025-03-19 17:44 ` Christian Marangi
2025-04-02 0:14 ` Sean Anderson
2025-04-02 15:08 ` Christian Marangi (Ansuel)
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