From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0631C64EC4 for ; Mon, 6 Mar 2023 16:50:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230304AbjCFQul (ORCPT ); Mon, 6 Mar 2023 11:50:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230315AbjCFQui (ORCPT ); Mon, 6 Mar 2023 11:50:38 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2747C20692; Mon, 6 Mar 2023 08:50:04 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 43DB0CE13BE; Mon, 6 Mar 2023 16:49:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 377D6C433D2; Mon, 6 Mar 2023 16:49:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1678121344; bh=iBKApfgP69TuqiYuJl4EoYVR8pMAhT0OCMK5XuShs24=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=K5dKb+o3w8SKk29OcBokO4VZ7vJezJAvCvn5Qup4SuvnrvpGYCQjos7aEFx7+7Zae y+cgUGf4pBanRndJwupF7M515vz3/KM5DLtwL9XUFnP/nLaUfMY53BFUB7iMXppOdu UFj3+h1bctZ/ArS0VFmRRk3OQ/YuPjM5Y2n0ITzPtpb3Yfg5H2yrMp63ztnLH9aS1v NTGIWh4AZZ7oBm8gvS3gqFQsv4kbYNqOXxp2GGhLWDR/Eb4MjHh/ufDxPDyEuBVfWd o6Zdq1r5B5snE0umVZdbnI3lwKBHC1c+ZOs7iq28CdHg6bsFd7PpTKuMT6trEdt3C3 p6H95KBe8djAw== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1pZE1w-0005kc-Tf; Mon, 06 Mar 2023 17:49:44 +0100 Date: Mon, 6 Mar 2023 17:49:44 +0100 From: Johan Hovold To: Manivannan Sadhasivam Cc: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com Subject: Re: [PATCH 15/19] dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs Message-ID: References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> <20230306153222.157667-16-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230306153222.157667-16-manivannan.sadhasivam@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Mar 06, 2023 at 09:02:18PM +0530, Manivannan Sadhasivam wrote: > "mhi" register region contains the MHI registers that could be used by > the PCIe controller drivers to get debug information like PCIe link > transition counts on newer SoCs. > > Signed-off-by: Manivannan Sadhasivam > --- > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index fb32c43dd12d..2de6e7154025 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -44,11 +44,11 @@ properties: > > reg: > minItems: 4 > - maxItems: 5 > + maxItems: 6 > > reg-names: > minItems: 4 > - maxItems: 5 > + maxItems: 6 > > interrupts: > minItems: 1 > @@ -185,10 +185,12 @@ allOf: > properties: > reg: > minItems: 4 > - maxItems: 4 > + maxItems: 5 > reg-names: > + minItems: 4 > items: > - const: parf # Qualcomm specific registers > + - const: mhi # MHI registers You need to add the new (optional) registers at the end. > - const: dbi # DesignWare PCIe registers > - const: elbi # External local bus interface registers > - const: config # PCIe configuration space Johan