Re: [PATCH 1/5] arm64: dts: qcom: sc8280xp: Add missing dwc3 quirks

[Johan Hovold <johan@kernel.org>]

On Wed, Mar 29, 2023 at 06:53:43PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Mar 29, 2023 at 10:34:56AM +0200, Johan Hovold wrote:
> > On Wed, Mar 29, 2023 at 10:56:00AM +0530, Manivannan Sadhasivam wrote:
> > > On Tue, Mar 28, 2023 at 03:09:03PM +0530, Manivannan Sadhasivam wrote:
> > > > On Tue, Mar 28, 2023 at 10:54:53AM +0200, Johan Hovold wrote:
> > > > > On Sat, Mar 25, 2023 at 10:22:13PM +0530, Manivannan Sadhasivam wrote:

> > > > > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > > > > > index 0d02599d8867..266a94c712aa 100644
> > > > > > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > > > > > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > > > > > @@ -3040,6 +3040,13 @@ usb_0_dwc3: usb@a600000 {
> > > > > >  				iommus = <&apps_smmu 0x820 0x0>;
> > > > > >  				phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
> > > > > >  				phy-names = "usb2-phy", "usb3-phy";
> > > > > > +				snps,hird-threshold = /bits/ 8 <0x0>;
> > > > > > +				snps,usb2-gadget-lpm-disable;
> > > > > 
> > > > > Here you are disabling LPM for gadget mode, which makes most of the
> > > > > other properties entirely pointless.
> > > 
> > > Checked with Qcom on these quirks. So this one is just disabling lpm for USB2
> > > and rest of the quirks below are for SS/SSP modes.
> > 
> > No, snps,hird-threshold is for USB2 LPM and so is
> > snps,is-utmi-l1-suspend and snps,has-lpm-erratum as you'll see if you
> > look at the implementation.
> > 
> 
> Correct me if I'm wrong. When I look into the code, "snps,is-utmi-l1-suspend"
> and "snps,hird-threshold" are used independently of the LPM mode atleast in one
> place:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/usb/dwc3/gadget.c#n2867
> 
> But I could be completely wrong here as my understanding of the usb stack is not
> that great.

Yeah, it's not that obvious from just looking at the code, but L1 (and
BESL) are USB2 LPM concepts and if you disable LPM then there is no need
to override these values in the BOS descriptor either (as is done in
dwc3_gadget_config_params() and bos_desc()).

> > > > > > +				snps,is-utmi-l1-suspend;
> > > > > > +				snps,dis-u1-entry-quirk;
> > > > > > +				snps,dis-u2-entry-quirk;
> > > > > 
> > > > > These appear to be used to optimise certain gadget application and
> > > > > likely not something that should be set in a dtsi.
> > > > > 
> > > > 
> > > > I will cross check these with Qcom and respin accordingly.
> > > > 
> > > 
> > > These quirks are needed as per the DWC IP integration with this SoC it seems.
> > > But I got the point that these don't add any values for host only
> > > configurations. At the same time, these quirks still hold true for the SoC even
> > > if not exercised.
> > > 
> > > So I think we should keep these in the dtsi itself.
> > 
> > Please take a closer look at the quirks you're enabling first. Commit
> > 729dcffd1ed3 ("usb: dwc3: gadget: Add support for disabling U1 and U2
> > entries") which added 
> > 
> > > > > > +				snps,dis-u1-entry-quirk;
> > > > > > +				snps,dis-u2-entry-quirk;
> > 
> > explicitly mentions
> > 
> > 	Gadget applications may have a requirement to disable the U1 and U2
> > 	entry based on the usecase.
> > 
> > which sounds like something that needs to be done in a per board dts at
> > least.
> > 
> 
> Going by this commit message it sounds like it. But...
> 
> > Perhaps keeping all of these in in the dtsi is correct, but that's going
> > to need some more motivation than simply that some vendor does so (as
> > they often do all sorts of things they should not).
> > 
> 
> If you read my last reply one more time, I didn't reason it based on the vendor
> code.

I was referring to the fact that these properties had been copied from
the vendor dtsi and seemingly so without further review or
justification in the commit message (e.g. to explain the
inconsistencies).

> But I hear a contradict reply from Qcom saying that these properties are
> required as a part of the DWC3 IP integration with the SoC. I need to recheck
> with them again tomorrow.
> 
> Also, if these properties are application specific then they shouldn't be in
> devicetree atleast :/

I fully agree with that.

Johan