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[2003:e4:1f05:3a00:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id qb37-20020a1709077ea500b0094ee0c9a6d0sm4820220ejc.184.2023.04.17.02.06.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 02:06:21 -0700 (PDT) Date: Mon, 17 Apr 2023 11:06:19 +0200 From: Thierry Reding To: Daniel Lezcano Cc: "Rafael J . Wysocki" , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Zhang Rui , Jon Hunter , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH 09/10] arm64: tegra: Rework SOCTHERM on Tegra132 and Tegra210 Message-ID: References: <20230414125721.1043589-1-thierry.reding@gmail.com> <20230414125721.1043589-10-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="xwrNWjN09bPXOM+0" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.10 (2023-03-25) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org --xwrNWjN09bPXOM+0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Apr 17, 2023 at 10:15:11AM +0200, Daniel Lezcano wrote: > On 14/04/2023 14:57, Thierry Reding wrote: > > From: Thierry Reding > >=20 > > The "heavy throttle" cooling device that SOCTHERM uses isn't a cooling > > device in the traditional sense. It's an automatic mechanism that cannot > > be actively controlled. Do not expose it as a cooling device and instead > > of tying it to a specific trip point, hard-code the temperature at which > > the automatic throttling will begin. > >=20 > > While at it, clean up the trip point names to reflect the names used by > > the thermal device tree bindings. > >=20 > > Signed-off-by: Thierry Reding > > --- > > arch/arm64/boot/dts/nvidia/tegra132.dtsi | 63 +++++------------- > > arch/arm64/boot/dts/nvidia/tegra210.dtsi | 83 +++++++----------------- > > 2 files changed, 39 insertions(+), 107 deletions(-) > >=20 > > diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot= /dts/nvidia/tegra132.dtsi > > index 8b78be8f4f9d..11ebf7517df1 100644 > > --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi > > +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi > > @@ -876,11 +876,10 @@ soctherm: thermal-sensor@700e2000 { > > #thermal-sensor-cells =3D <1>; > > throttle-cfgs { > > - throttle_heavy: heavy { > > + heavy { > > nvidia,priority =3D <100>; > > nvidia,cpu-throt-level =3D ; > > - > > - #cooling-cells =3D <2>; > > + temperature =3D <102000>; > > }; > > }; > > }; > > @@ -1136,114 +1135,84 @@ cpu-thermal { > > polling-delay-passive =3D <1000>; > > polling-delay =3D <0>; > > - thermal-sensors =3D > > - <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; > > + thermal-sensors =3D <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; > > trips { > > - cpu_shutdown_trip { > > + critical { > > temperature =3D <105000>; > > hysteresis =3D <1000>; > > type =3D "critical"; > > }; > > - cpu_throttle_trip: throttle-trip { > > + hot { > > temperature =3D <102000>; > > hysteresis =3D <1000>; > > type =3D "hot"; > > }; > > }; > > - > > - cooling-maps { > > - map0 { > > - trip =3D <&cpu_throttle_trip>; > > - cooling-device =3D <&throttle_heavy 1 1>; > > - }; > > - }; >=20 > If the hardware mitigation is 'heavy', don't you want to have DVFS acting > before hardware throttling ? The throttling here is in fact some form of DVFS, but yes, generally we would likely want to have additional forms of DVFS before we reach this state. We could add CPU cooling devices and there's also a mechanism to throttle the DRAM frequency on certain boards. But those are mostly orthogonal to this series. The goal here is to get rid of the throttling mechanism as a cooling device. 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