From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E038C77B7F for ; Mon, 8 May 2023 09:28:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232753AbjEHJ2H (ORCPT ); Mon, 8 May 2023 05:28:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233057AbjEHJ2F (ORCPT ); Mon, 8 May 2023 05:28:05 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7ADAA1A1F8; Mon, 8 May 2023 02:27:57 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C26326196E; Mon, 8 May 2023 09:27:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6AF88C4339B; Mon, 8 May 2023 09:27:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683538076; bh=xjtpkJFszM9BNKzTaTVwrSPwHtleGTIEPou2QwMYpds=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=oLA3fa/0kDp64fOT1Hd+PK81rCvKxAgPJtioHFS6K6/gX3qgdlddUzap/83sEaE2o pUeWDbV6MiWa67vSJlTSUnPW6cbvIcplh96TUwg7nrfxfGnmHABJMelSr4E4EuoMr8 h8IzaMoaIDwpwYIvFHta2sKD3Xi73Fj6CljsuVvJ3eGEGIQx/n3AzjnP9J6mkrNHIa CLBdAAIx1DMGQahTsrjfVzN8Q7rq/Ba603mX1kvd/FMj1XXyduxpirm7tlzHIqK8Um 7LNIU4XXlRAguFtmYi/f0XpaxNeZP/WO/gDeTGvitzQzAW7vTVyO3Oeccj51pTUkLJ Lt9um+WzS+C4g== Date: Mon, 8 May 2023 14:57:52 +0530 From: Vinod Koul To: Dmitry Rokosov Cc: gregkh@linuxfoundation.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, neil.armstrong@linaro.org, khilman@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com, mturquette@baylibre.com, kishon@kernel.org, hminas@synopsys.com, Thinh.Nguyen@synopsys.com, yue.wang@amlogic.com, hanjie.lin@amlogic.com, kernel@sberdevices.ru, rockosov@gmail.com, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-phy@lists.infradead.org Subject: Re: [PATCH v3 1/5] phy: amlogic: enable/disable clkin during Amlogic USB PHY init/exit Message-ID: References: <20230426102922.19705-1-ddrokosov@sberdevices.ru> <20230426102922.19705-2-ddrokosov@sberdevices.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230426102922.19705-2-ddrokosov@sberdevices.ru> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 26-04-23, 13:29, Dmitry Rokosov wrote: > Previously, all Amlogic boards used the XTAL clock as the default board > clock for the USB PHY input, so there was no need to enable it. > However, with the introduction of new Amlogic SoCs like the A1 family, > the USB PHY now uses a gated clock. Hence, it is necessary to enable > this gated clock during the PHY initialization sequence, or disable it > during the PHY exit, as appropriate. Applied to phy/next, thanks -- ~Vinod