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From: Jisheng Zhang <jszhang@kernel.org>
To: Conor Dooley <conor@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, Guo Ren <guoren@kernel.org>,
	heiko@sntech.de
Subject: Re: [PATCH 3/5] riscv: dts: add initial T-HEAD light SoC device tree
Date: Tue, 9 May 2023 00:26:10 +0800	[thread overview]
Message-ID: <ZFkiotPacIMUghDP@xhacker> (raw)
In-Reply-To: <20230507-calamari-gentleman-bbe62af06f92@spud>

On Sun, May 07, 2023 at 10:35:12PM +0100, Conor Dooley wrote:
> Hey Jisheng,
> 
> On Mon, May 08, 2023 at 02:23:02AM +0800, Jisheng Zhang wrote:
> 
> > +		c910_0: cpu@0 {
> > +			compatible = "thead,c910", "riscv";
> > +			device_type = "cpu";
> > +			riscv,isa = "rv64imafdc";
> 
> Does this support more than "rv64imafdc"?
> I assume there's some _xtheadfoo extensions that it does support,
> although I am not sure how we are proceeding with those - Heiko might
> have a more nuanced take.
> 
> > +		reset: reset-sample {
> > +			compatible = "thead,reset-sample";
> 
> What is a "reset-sample"?

This node is only for opensbi. The compatible string is already in
opensbi. Do we also need to add dt-binding for it in linux?

> 
> > +			entry-reg = <0xff 0xff019050>;
> > +			entry-cnt = <4>;
> > +			control-reg = <0xff 0xff015004>;
> > +			control-val = <0x1c>;
> > +			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
> > +		};
> > +
> > +		plic: interrupt-controller@ffd8000000 {
> > +			compatible = "thead,c910-plic";
> > +			reg = <0xff 0xd8000000 0x0 0x01000000>;
> > +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> > +					      <&cpu1_intc 11>, <&cpu1_intc 9>,
> > +					      <&cpu2_intc 11>, <&cpu2_intc 9>,
> > +					      <&cpu3_intc 11>, <&cpu3_intc 9>;
> > +			interrupt-controller;
> > +			#interrupt-cells = <1>;
> > +			riscv,ndev = <240>;
> > +		};
> > +
> > +		clint: timer@ffdc000000 {
> > +			compatible = "thead,c900-clint";
> 
> "c900"? That a typo or intentional. Hard to tell since this compatible
> is undocumented ;)

Per my understanding, this node is only for opensbi too. Add will add
dt-binding in v2.

> 
> > +			reg = <0xff 0xdc000000 0x0 0x00010000>;
> > +			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> > +					      <&cpu1_intc 3>, <&cpu1_intc 7>,
> > +					      <&cpu2_intc 3>, <&cpu2_intc 7>,
> > +					      <&cpu3_intc 3>, <&cpu3_intc 7>;
> > +		};
> > +
> > +		uart0: serial@ffe7014000 {
> > +			compatible = "snps,dw-apb-uart";
> > +			reg = <0xff 0xe7014000 0x0 0x4000>;
> > +			interrupts = <36>;
> > +			clocks = <&uart_sclk>;
> > +			clock-names = "baudclk";
> 
> dtbs_check complains about this clock name.
> > +
> > +		dmac0: dmac@ffefc00000 {
> 
> dma-controller@
> 
> As I mentioned in the other patch, please clean up the dtbs_check
> complaints for v2.
> 

Thanks for the reminding.

  parent reply	other threads:[~2023-05-08 16:37 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-07 18:22 [PATCH 0/5] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang
2023-05-07 18:23 ` [PATCH 1/5] irqchip/sifive-plic: Support T-HEAD's C910 PLIC Jisheng Zhang
2023-05-07 21:18   ` Conor Dooley
2023-05-08  3:14   ` Icenowy Zheng
2023-05-08  6:52   ` Guo Ren
2023-05-08  7:07     ` Conor Dooley
2023-05-08 16:09     ` Jisheng Zhang
2023-05-08  9:17   ` Krzysztof Kozlowski
2023-05-07 18:23 ` [PATCH 2/5] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang
2023-05-07 21:22   ` Conor Dooley
2023-05-08  6:42     ` Guo Ren
2023-05-08  6:52       ` Conor Dooley
2023-05-08  6:58         ` Guo Ren
2023-05-08  7:04           ` Conor Dooley
2023-05-07 18:23 ` [PATCH 3/5] riscv: dts: add initial T-HEAD light SoC device tree Jisheng Zhang
2023-05-07 21:35   ` Conor Dooley
2023-05-08  3:32     ` Icenowy Zheng
2023-05-08  7:01       ` Conor Dooley
2023-05-08  8:23       ` Heiko Stübner
2023-05-08  8:35         ` Conor Dooley
2023-05-08 15:56           ` Heiko Stübner
2023-05-08 16:26     ` Jisheng Zhang [this message]
2023-05-08 16:44       ` Conor Dooley
2023-05-08 17:09         ` Heiko Stübner
2023-05-21 15:37         ` Guo Ren
2023-05-21 17:08           ` Conor Dooley
2023-05-22  1:36             ` Guo Ren
2023-05-08  9:20   ` Krzysztof Kozlowski
2023-05-07 18:23 ` [PATCH 4/5] riscv: dts: thead: add sipeed Lichee Pi 4A board " Jisheng Zhang
2023-05-07 21:27   ` Conor Dooley
2023-05-08  6:44   ` Guo Ren
2023-05-07 18:23 ` [PATCH 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang
2023-05-07 21:21   ` Conor Dooley
2023-05-08 16:17     ` Jisheng Zhang
2023-05-08 17:23       ` Conor Dooley
2023-05-08  6:22   ` Guo Ren
2023-05-08  6:16 ` [PATCH 0/5] Add Sipeed Lichee Pi 4A RISC-V board support Guo Ren

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