[PATCH v4 0/6] phy: cadence: salvo: some fixes and workarounds

[PATCH v4 0/6] phy: cadence: salvo: some fixes and workarounds

[Frank Li]

Sorry I have not realized some patches were missed at upstream kernel.
Version number continue with previous
https://lore.kernel.org/imx/ZGOCT0Mdg3Jtar6c@matsya/T/#t

Peter's Fixes:
- Bist issue
- fix corrupt package from devices when start transferring less than 20us
- fix the FSM in controller seeing the disconnection at L1 use case.

Change from v3 to v4:
- Added missed dependent patches.

Change from v2 to v3:
- add cdns prefix
Change from v1 to v2
- remove empty change before #include 
- Remove dts change from patch
- fixed dt-binding-check warning


Frank Li (2):
  phy: cadence: salvo: Add cdns,usb2-disconnect-threshold-microvolt
    property
  dt-bindings: phy: cdns,salvo: add property
    cdns,usb2-disconnect-threshold-microvolt

Peter Chen (4):
  phy: cadence: salvo: add access for USB2PHY
  phy: cadence: salvo: decrease delay value to zero for txvalid
  phy: cadence: salvo: add bist fix
  phy: cadence: salvo: add .set_mode API

 .../bindings/phy/cdns,salvo-phy.yaml          |  6 ++
 drivers/phy/cadence/phy-cadence-salvo.c       | 96 +++++++++++++++++--
 2 files changed, 94 insertions(+), 8 deletions(-)

-- 
2.34.1

[PATCH v4 1/6] phy: cadence: salvo: add access for USB2PHY

[Frank Li]

From: Peter Chen <peter.chen@nxp.com>

There is an offset for USB2PHY in SALVO phy, add offset parameter for read
and write API to cover both USB2 and USB3 PHY control.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/phy/cadence/phy-cadence-salvo.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
index e569f5f67578..06c5dbdb700e 100644
--- a/drivers/phy/cadence/phy-cadence-salvo.c
+++ b/drivers/phy/cadence/phy-cadence-salvo.c
@@ -15,7 +15,9 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 
-/* PHY register definition */
+#define USB3_PHY_OFFSET			0x0
+#define USB2_PHY_OFFSET			0x38000
+/* USB3 PHY register definition */
 #define PHY_PMA_CMN_CTRL1			0xC800
 #define TB_ADDR_CMN_DIAG_HSCLK_SEL		0x01e0
 #define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR	0x0084
@@ -109,16 +111,16 @@ struct cdns_salvo_phy {
 };
 
 static const struct of_device_id cdns_salvo_phy_of_match[];
-static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 reg)
+static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 offset, u32 reg)
 {
-	return (u16)readl(salvo_phy->base +
+	return (u16)readl(salvo_phy->base + offset +
 		reg * (1 << salvo_phy->data->reg_offset_shift));
 }
 
-static void cdns_salvo_write(struct cdns_salvo_phy *salvo_phy,
+static void cdns_salvo_write(struct cdns_salvo_phy *salvo_phy, u32 offset,
 			     u32 reg, u16 val)
 {
-	writel(val, salvo_phy->base +
+	writel(val, salvo_phy->base + offset +
 		reg * (1 << salvo_phy->data->reg_offset_shift));
 }
 
@@ -219,13 +221,13 @@ static int cdns_salvo_phy_init(struct phy *phy)
 	for (i = 0; i < data->init_sequence_length; i++) {
 		const struct cdns_reg_pairs *reg_pair = data->init_sequence_val + i;
 
-		cdns_salvo_write(salvo_phy, reg_pair->off, reg_pair->val);
+		cdns_salvo_write(salvo_phy, USB3_PHY_OFFSET, reg_pair->off, reg_pair->val);
 	}
 
 	/* RXDET_IN_P3_32KHZ, Receiver detect slow clock enable */
-	value = cdns_salvo_read(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL);
+	value = cdns_salvo_read(salvo_phy, USB3_PHY_OFFSET, TB_ADDR_TX_RCVDETSC_CTRL);
 	value |= RXDET_IN_P3_32KHZ;
-	cdns_salvo_write(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL,
+	cdns_salvo_write(salvo_phy, USB3_PHY_OFFSET, TB_ADDR_TX_RCVDETSC_CTRL,
 			 RXDET_IN_P3_32KHZ);
 
 	udelay(10);
-- 
2.34.1

[PATCH v4 2/6] phy: cadence: salvo: decrease delay value to zero for txvalid

[Frank Li]

From: Peter Chen <peter.chen@nxp.com>

For USB2 L1 use cases, some hosts may start transferring less than 20us
after End of Resume, it causes the host seeing corrupt packet from the
device side. The reason is the delay time between PHY powers up and
txvalid is 20us. To fix it, we change the delay value as 0us.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/phy/cadence/phy-cadence-salvo.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
index 06c5dbdb700e..2e3d4d8fb8eb 100644
--- a/drivers/phy/cadence/phy-cadence-salvo.c
+++ b/drivers/phy/cadence/phy-cadence-salvo.c
@@ -89,8 +89,20 @@
 #define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR	0x40f2
 #define TB_ADDR_TX_RCVDETSC_CTRL	        0x4124
 
+/* USB2 PHY register definition */
+#define UTMI_REG15				0xaf
+
 /* TB_ADDR_TX_RCVDETSC_CTRL */
 #define RXDET_IN_P3_32KHZ			BIT(0)
+/*
+ * UTMI_REG15
+ *
+ * Gate how many us for the txvalid signal until analog
+ * HS/FS transmitters have powered up
+ */
+#define TXVALID_GATE_THRESHOLD_HS_MASK		(BIT(4) | BIT(5))
+/* 0us, txvalid is ready just after HS/FS transmitters have powered up */
+#define TXVALID_GATE_THRESHOLD_HS_0US		(BIT(4) | BIT(5))
 
 struct cdns_reg_pairs {
 	u16 val;
@@ -230,6 +242,11 @@ static int cdns_salvo_phy_init(struct phy *phy)
 	cdns_salvo_write(salvo_phy, USB3_PHY_OFFSET, TB_ADDR_TX_RCVDETSC_CTRL,
 			 RXDET_IN_P3_32KHZ);
 
+	value = cdns_salvo_read(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15);
+	value &= ~TXVALID_GATE_THRESHOLD_HS_MASK;
+	cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15,
+			 value | TXVALID_GATE_THRESHOLD_HS_0US);
+
 	udelay(10);
 
 	clk_disable_unprepare(salvo_phy->clk);
-- 
2.34.1

[PATCH v4 3/6] phy: cadence: salvo: add bist fix

[Frank Li]

From: Peter Chen <peter.chen@nxp.com>

Very limited parts may fail to work on full speed mode (both host and
device modes) for USB3 port due to higher threshold in full speed receiver
of USB2.0 PHY.

One example failure symptom is, the enumeration is failed when connecting
full speed USB mouse to USB3 port, especially under high temperature.

The workaround is to configure threshold voltage value of single ended
receiver by setting USB2.0 PHY register AFE_RX_REG5[2:0] to 3'b101.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
---
 drivers/phy/cadence/phy-cadence-salvo.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
index 2e3d4d8fb8eb..b9866dc146ce 100644
--- a/drivers/phy/cadence/phy-cadence-salvo.c
+++ b/drivers/phy/cadence/phy-cadence-salvo.c
@@ -91,6 +91,7 @@
 
 /* USB2 PHY register definition */
 #define UTMI_REG15				0xaf
+#define UTMI_AFE_RX_REG5			0x12
 
 /* TB_ADDR_TX_RCVDETSC_CTRL */
 #define RXDET_IN_P3_32KHZ			BIT(0)
@@ -247,6 +248,8 @@ static int cdns_salvo_phy_init(struct phy *phy)
 	cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15,
 			 value | TXVALID_GATE_THRESHOLD_HS_0US);
 
+	cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_RX_REG5,
+			 0x5);
 	udelay(10);
 
 	clk_disable_unprepare(salvo_phy->clk);
-- 
2.34.1

[PATCH v4 4/6] phy: cadence: salvo: add .set_mode API

[Frank Li]

From: Peter Chen <peter.chen@nxp.com>

For NXP platform design, the PHY can't know VBUS well, it causes the FSM
in controller seeing the disconnection at L1 use case. With .set_mode API
introduced, the controller driver could force PHY seeing B Session VALID
when it is at the device mode (VBUS is there), and keep FSM working well.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/phy/cadence/phy-cadence-salvo.c | 29 +++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
index b9866dc146ce..41616f786321 100644
--- a/drivers/phy/cadence/phy-cadence-salvo.c
+++ b/drivers/phy/cadence/phy-cadence-salvo.c
@@ -92,6 +92,7 @@
 /* USB2 PHY register definition */
 #define UTMI_REG15				0xaf
 #define UTMI_AFE_RX_REG5			0x12
+#define UTMI_AFE_BC_REG4			0x29
 
 /* TB_ADDR_TX_RCVDETSC_CTRL */
 #define RXDET_IN_P3_32KHZ			BIT(0)
@@ -105,6 +106,9 @@
 /* 0us, txvalid is ready just after HS/FS transmitters have powered up */
 #define TXVALID_GATE_THRESHOLD_HS_0US		(BIT(4) | BIT(5))
 
+#define SET_B_SESSION_VALID			(BIT(6) | BIT(5))
+#define CLR_B_SESSION_VALID			(BIT(6))
+
 struct cdns_reg_pairs {
 	u16 val;
 	u32 off;
@@ -124,6 +128,13 @@ struct cdns_salvo_phy {
 };
 
 static const struct of_device_id cdns_salvo_phy_of_match[];
+static const struct cdns_salvo_data cdns_nxp_salvo_data;
+
+static bool cdns_is_nxp_phy(struct cdns_salvo_phy *salvo_phy)
+{
+	return salvo_phy->data == &cdns_nxp_salvo_data;
+}
+
 static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 offset, u32 reg)
 {
 	return (u16)readl(salvo_phy->base + offset +
@@ -273,11 +284,29 @@ static int cdns_salvo_phy_power_off(struct phy *phy)
 	return 0;
 }
 
+static int cdns_salvo_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+	struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
+
+	if (!cdns_is_nxp_phy(salvo_phy))
+		return 0;
+
+	if (mode == PHY_MODE_INVALID)
+		cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_BC_REG4,
+			 CLR_B_SESSION_VALID);
+	else if (mode == PHY_MODE_USB_DEVICE)
+		cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_BC_REG4,
+			 SET_B_SESSION_VALID);
+
+	return 0;
+}
+
 static const struct phy_ops cdns_salvo_phy_ops = {
 	.init		= cdns_salvo_phy_init,
 	.power_on	= cdns_salvo_phy_power_on,
 	.power_off	= cdns_salvo_phy_power_off,
 	.owner		= THIS_MODULE,
+	.set_mode	= cdns_salvo_set_mode,
 };
 
 static int cdns_salvo_phy_probe(struct platform_device *pdev)
-- 
2.34.1

[PATCH v4 5/6] phy: cadence: salvo: Add cdns,usb2-disconnect-threshold-microvolt property

[Frank Li]

Add cdns,usb2-disconnect-threshold-microvolt property to address fake USB
disconnection issue during enumeration or suspend state for difference
platform.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/phy/cadence/phy-cadence-salvo.c | 29 +++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
index 41616f786321..881e122f93c2 100644
--- a/drivers/phy/cadence/phy-cadence-salvo.c
+++ b/drivers/phy/cadence/phy-cadence-salvo.c
@@ -6,6 +6,7 @@
  * Copyright (c) 2019-2020 NXP
  */
 
+#include <linux/bitfield.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -91,9 +92,19 @@
 
 /* USB2 PHY register definition */
 #define UTMI_REG15				0xaf
+#define UTMI_AFE_RX_REG0			0x0d
 #define UTMI_AFE_RX_REG5			0x12
 #define UTMI_AFE_BC_REG4			0x29
 
+/* Align UTMI_AFE_RX_REG0 bit[7:6] define */
+enum usb2_disconn_threshold {
+	USB2_DISCONN_THRESHOLD_575 = 0x0,
+	USB2_DISCONN_THRESHOLD_610 = 0x1,
+	USB2_DISCONN_THRESHOLD_645 = 0x3,
+};
+
+#define RX_USB2_DISCONN_MASK			GENMASK(7, 6)
+
 /* TB_ADDR_TX_RCVDETSC_CTRL */
 #define RXDET_IN_P3_32KHZ			BIT(0)
 /*
@@ -125,6 +136,7 @@ struct cdns_salvo_phy {
 	struct clk *clk;
 	void __iomem *base;
 	struct cdns_salvo_data *data;
+	enum usb2_disconn_threshold usb2_disconn;
 };
 
 static const struct of_device_id cdns_salvo_phy_of_match[];
@@ -261,6 +273,12 @@ static int cdns_salvo_phy_init(struct phy *phy)
 
 	cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_RX_REG5,
 			 0x5);
+
+	value = cdns_salvo_read(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_RX_REG0);
+	value &= ~RX_USB2_DISCONN_MASK;
+	value = FIELD_PREP(RX_USB2_DISCONN_MASK, salvo_phy->usb2_disconn);
+	cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_RX_REG0, value);
+
 	udelay(10);
 
 	clk_disable_unprepare(salvo_phy->clk);
@@ -315,6 +333,7 @@ static int cdns_salvo_phy_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct cdns_salvo_phy *salvo_phy;
 	struct cdns_salvo_data *data;
+	u32 val;
 
 	data = (struct cdns_salvo_data *)of_device_get_match_data(dev);
 	salvo_phy = devm_kzalloc(dev, sizeof(*salvo_phy), GFP_KERNEL);
@@ -326,6 +345,16 @@ static int cdns_salvo_phy_probe(struct platform_device *pdev)
 	if (IS_ERR(salvo_phy->clk))
 		return PTR_ERR(salvo_phy->clk);
 
+	if (of_property_read_u32(dev->of_node, "cdns,usb2-disconnect-threshold-microvolt", &val))
+		val = 575;
+
+	if (val < 610)
+		salvo_phy->usb2_disconn = USB2_DISCONN_THRESHOLD_575;
+	else if (val < 645)
+		salvo_phy->usb2_disconn = USB2_DISCONN_THRESHOLD_610;
+	else
+		salvo_phy->usb2_disconn = USB2_DISCONN_THRESHOLD_645;
+
 	salvo_phy->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(salvo_phy->base))
 		return PTR_ERR(salvo_phy->base);
-- 
2.34.1

[PATCH v4 6/6] dt-bindings: phy: cdns,salvo: add property cdns,usb2-disconnect-threshold-microvolt

[Frank Li]

Add cdns,usb2-disconnect-threshold-microvolt property to address fake USB
disconnection issue during enumeration or suspend state for difference
platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml b/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
index c9e65a2facd5..c7281a7c8244 100644
--- a/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
@@ -31,6 +31,12 @@ properties:
   "#phy-cells":
     const: 0
 
+  cdns,usb2-disconnect-threshold-microvolt:
+    description: The microvolt threshold value utilized for detecting
+      USB disconnection event.
+    enum: [575, 610, 645]
+    default: 575
+
 required:
   - compatible
   - reg
-- 
2.34.1

Re: [PATCH v4 3/6] phy: cadence: salvo: add bist fix

[Vinod Koul]

On 16-05-23, 11:43, Frank Li wrote:
> From: Peter Chen <peter.chen@nxp.com>
> 
> Very limited parts may fail to work on full speed mode (both host and
> device modes) for USB3 port due to higher threshold in full speed receiver
> of USB2.0 PHY.
> 
> One example failure symptom is, the enumeration is failed when connecting
> full speed USB mouse to USB3 port, especially under high temperature.
> 
> The workaround is to configure threshold voltage value of single ended
> receiver by setting USB2.0 PHY register AFE_RX_REG5[2:0] to 3'b101.
> 
> Signed-off-by: Peter Chen <peter.chen@nxp.com>

This needs senders S-o-b as well!

> ---
>  drivers/phy/cadence/phy-cadence-salvo.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
> index 2e3d4d8fb8eb..b9866dc146ce 100644
> --- a/drivers/phy/cadence/phy-cadence-salvo.c
> +++ b/drivers/phy/cadence/phy-cadence-salvo.c
> @@ -91,6 +91,7 @@
>  
>  /* USB2 PHY register definition */
>  #define UTMI_REG15				0xaf
> +#define UTMI_AFE_RX_REG5			0x12
>  
>  /* TB_ADDR_TX_RCVDETSC_CTRL */
>  #define RXDET_IN_P3_32KHZ			BIT(0)
> @@ -247,6 +248,8 @@ static int cdns_salvo_phy_init(struct phy *phy)
>  	cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15,
>  			 value | TXVALID_GATE_THRESHOLD_HS_0US);
>  
> +	cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_RX_REG5,
> +			 0x5);

single line reads better

>  	udelay(10);
>  
>  	clk_disable_unprepare(salvo_phy->clk);
> -- 
> 2.34.1

-- 
~Vinod

Re: [PATCH v4 4/6] phy: cadence: salvo: add .set_mode API

[Vinod Koul]

On 16-05-23, 11:43, Frank Li wrote:
> From: Peter Chen <peter.chen@nxp.com>
> 
> For NXP platform design, the PHY can't know VBUS well, it causes the FSM
> in controller seeing the disconnection at L1 use case. With .set_mode API
> introduced, the controller driver could force PHY seeing B Session VALID
> when it is at the device mode (VBUS is there), and keep FSM working well.
> 
> Signed-off-by: Peter Chen <peter.chen@nxp.com>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  drivers/phy/cadence/phy-cadence-salvo.c | 29 +++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
> index b9866dc146ce..41616f786321 100644
> --- a/drivers/phy/cadence/phy-cadence-salvo.c
> +++ b/drivers/phy/cadence/phy-cadence-salvo.c
> @@ -92,6 +92,7 @@
>  /* USB2 PHY register definition */
>  #define UTMI_REG15				0xaf
>  #define UTMI_AFE_RX_REG5			0x12
> +#define UTMI_AFE_BC_REG4			0x29
>  
>  /* TB_ADDR_TX_RCVDETSC_CTRL */
>  #define RXDET_IN_P3_32KHZ			BIT(0)
> @@ -105,6 +106,9 @@
>  /* 0us, txvalid is ready just after HS/FS transmitters have powered up */
>  #define TXVALID_GATE_THRESHOLD_HS_0US		(BIT(4) | BIT(5))
>  
> +#define SET_B_SESSION_VALID			(BIT(6) | BIT(5))
> +#define CLR_B_SESSION_VALID			(BIT(6))
> +
>  struct cdns_reg_pairs {
>  	u16 val;
>  	u32 off;
> @@ -124,6 +128,13 @@ struct cdns_salvo_phy {
>  };
>  
>  static const struct of_device_id cdns_salvo_phy_of_match[];
> +static const struct cdns_salvo_data cdns_nxp_salvo_data;
> +
> +static bool cdns_is_nxp_phy(struct cdns_salvo_phy *salvo_phy)
> +{
> +	return salvo_phy->data == &cdns_nxp_salvo_data;
> +}
> +
>  static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 offset, u32 reg)
>  {
>  	return (u16)readl(salvo_phy->base + offset +
> @@ -273,11 +284,29 @@ static int cdns_salvo_phy_power_off(struct phy *phy)
>  	return 0;
>  }
>  
> +static int cdns_salvo_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> +{
> +	struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
> +
> +	if (!cdns_is_nxp_phy(salvo_phy))
> +		return 0;
> +
> +	if (mode == PHY_MODE_INVALID)
> +		cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_BC_REG4,
> +			 CLR_B_SESSION_VALID);
> +	else if (mode == PHY_MODE_USB_DEVICE)
> +		cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_BC_REG4,
> +			 SET_B_SESSION_VALID);

no else?

> +
> +	return 0;

return success even when mode is not handled?

> +}
> +
>  static const struct phy_ops cdns_salvo_phy_ops = {
>  	.init		= cdns_salvo_phy_init,
>  	.power_on	= cdns_salvo_phy_power_on,
>  	.power_off	= cdns_salvo_phy_power_off,
>  	.owner		= THIS_MODULE,
> +	.set_mode	= cdns_salvo_set_mode,
>  };
>  
>  static int cdns_salvo_phy_probe(struct platform_device *pdev)
> -- 
> 2.34.1

-- 
~Vinod