From: Yixun Lan <dlan@gentoo.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>,
devicetree@vger.kernel.org, Yangtao Li <frank.li@vivo.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Wei Fu <wefu@redhat.com>
Subject: Re: [PATCH v2 0/9] Add Sipeed Lichee Pi 4A RISC-V board support
Date: Fri, 26 May 2023 10:19:10 +0800 [thread overview]
Message-ID: <ZHAXHs03kXNgp0QF@ofant> (raw)
In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org>
Hi Jisheng
On 02:45 Fri 19 May , Jisheng Zhang wrote:
> Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
> module which is powered by T-HEAD's TH1520 SoC. Add minimal device
> tree files for the core module and the development board.
>
> Support basic uart/gpio/dmac drivers, so supports booting to a basic
> shell.
>
> FWICT, one issue I'm not sure is the cpu reset dt-binding: IIUC, the
> secondary CPUs in T-HEAD SMP capable platforms need some special
> handling. The first one is to write the warm reset entry to entry
> register. The second one is write a SoC specific control value to
> a SoC specific control reg. The last one is to clone some CSRs for
> secondary CPUs to ensure these CSRs' values are the same as the
> main boot CPU. This DT node is mainly used by opensbi firmware.
> Any suggestion about this reset dt-binding is appreciated!
>
> Thanks
>
> Since v1:
> - add missing plic, clint, th1520 itself dt-bindings
> - use c900-plic
> - s/light/th1520
> - add dt-binding for T-HEAD CPU reset
> - enable ARCH_THEAD in defconfig
> - fix all dtbs_check error/warning except the CPU RESET, see above.
it would be nice to have a URL reference to v0
https://lore.kernel.org/all/20230507182304.2934-1-jszhang@kernel.org/
>
> Jisheng Zhang (9):
> dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC
> dt-bindings: timer: Add T-HEAD TH1520 clint
> dt-bindings: riscv: Add T-HEAD TH1520 board compatibles
> dt-binding: riscv: add T-HEAD CPU reset
> riscv: Add the T-HEAD SoC family Kconfig option
> riscv: dts: add initial T-HEAD TH1520 SoC device tree
> riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
> MAINTAINERS: add entry for T-HEAD RISC-V SoC
> riscv: defconfig: enable T-HEAD SoC
>
> .../sifive,plic-1.0.0.yaml | 1 +
> .../bindings/riscv/thead,cpu-reset.yaml | 69 +++
> .../devicetree/bindings/riscv/thead.yaml | 29 ++
> .../bindings/timer/sifive,clint.yaml | 1 +
> MAINTAINERS | 6 +
> arch/riscv/Kconfig.socs | 6 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/thead/Makefile | 2 +
> .../dts/thead/th1520-lichee-module-4a.dtsi | 38 ++
> .../boot/dts/thead/th1520-lichee-pi-4a.dts | 32 ++
> arch/riscv/boot/dts/thead/th1520.dtsi | 451 ++++++++++++++++++
> arch/riscv/configs/defconfig | 1 +
> 12 files changed, 637 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml
> create mode 100644 arch/riscv/boot/dts/thead/Makefile
> create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
> create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi
>
> --
> 2.40.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
prev parent reply other threads:[~2023-05-26 2:19 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-18 18:45 [PATCH v2 0/9] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang
2023-05-18 18:45 ` [PATCH v2 1/9] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Jisheng Zhang
2023-05-18 19:36 ` Conor Dooley
2023-05-21 13:14 ` Guo Ren
2023-05-18 18:45 ` [PATCH v2 2/9] dt-bindings: timer: Add T-HEAD TH1520 clint Jisheng Zhang
2023-05-18 19:37 ` Conor Dooley
2023-05-18 18:45 ` [PATCH v2 3/9] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Jisheng Zhang
2023-05-18 19:40 ` Conor Dooley
2023-05-19 15:50 ` Icenowy Zheng
2023-05-18 18:45 ` [PATCH v2 4/9] dt-binding: riscv: add T-HEAD CPU reset Jisheng Zhang
2023-05-18 19:39 ` Rob Herring
2023-05-18 19:53 ` Conor Dooley
2023-05-22 2:16 ` Guo Ren
2023-05-22 7:09 ` Conor Dooley
2023-05-22 7:42 ` Guo Ren
2023-05-30 12:55 ` Krzysztof Kozlowski
2023-05-18 18:45 ` [PATCH v2 5/9] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang
2023-05-18 19:42 ` Conor Dooley
2023-05-18 18:45 ` [PATCH v2 6/9] riscv: dts: add initial T-HEAD TH1520 SoC device tree Jisheng Zhang
2023-05-18 21:02 ` Conor Dooley
2023-05-26 2:21 ` Yixun Lan
2023-05-18 18:45 ` [PATCH v2 7/9] riscv: dts: thead: add sipeed Lichee Pi 4A board " Jisheng Zhang
2023-05-18 21:03 ` Conor Dooley
2023-05-18 18:45 ` [PATCH v2 8/9] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang
2023-05-18 20:57 ` Conor Dooley
2023-05-18 18:45 ` [PATCH v2 9/9] riscv: defconfig: enable T-HEAD SoC Jisheng Zhang
2023-05-18 20:58 ` Conor Dooley
2023-05-19 20:56 ` Palmer Dabbelt
2023-05-20 1:16 ` Guo Ren
2023-05-26 2:19 ` Yixun Lan [this message]
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