From: Sunil V L <sunilvl@ventanamicro.com>
To: Conor Dooley <conor@kernel.org>
Cc: palmer@dabbelt.com, Conor Dooley <conor.dooley@microchip.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Andrew Jones <ajones@ventanamicro.com>,
Yangyu Chen <cyy@cyyself.name>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 2/7] RISC-V: split early & late of_node to hartid mapping
Date: Mon, 12 Jun 2023 13:01:31 +0530 [thread overview]
Message-ID: <ZIbJ02v1c/dG3ywb@sunil-laptop> (raw)
In-Reply-To: <20230607-glade-pastel-d8cbd9d9f3c6@spud>
On Wed, Jun 07, 2023 at 09:28:26PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Some back and forth with Drew [1] about riscv_fill_hwcap() resulted in
> the realisation that it is not very useful to parse the DT & perform
> validation of riscv,isa every time we would like to get the id for a
> hart.
>
> Although it is no longer called in riscv_fill_hwcap(),
> riscv_of_processor_hartid() is called in several other places.
> Notably in setup_smp() it forms part of the logic for filling the mask
> of possible CPUs. Since a possible CPU must have passed this basic
> validation of riscv,isa, a repeat validation is not required.
>
> Rename riscv_of_processor_id() to riscv_early_of_processor_id(),
> which will be called from setup_smp() & introduce a new
> riscv_of_processor_id() which makes use of the pre-populated mask of
> possible cpus.
>
> Link: https://lore.kernel.org/linux-riscv/xvdswl3iyikwvamny7ikrxo2ncuixshtg3f6uucjahpe3xpc5c@ud4cz4fkg5dj/ [1]
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
next prev parent reply other threads:[~2023-06-12 7:38 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-07 20:28 [PATCH v3 0/7] ISA string parser cleanups Conor Dooley
2023-06-07 20:28 ` [PATCH v3 1/7] RISC-V: simplify register width check in ISA string parsing Conor Dooley
2023-06-12 7:07 ` Sunil V L
2023-06-07 20:28 ` [PATCH v3 2/7] RISC-V: split early & late of_node to hartid mapping Conor Dooley
2023-06-12 7:31 ` Sunil V L [this message]
2023-06-07 20:28 ` [PATCH v3 3/7] RISC-V: validate riscv,isa at boot, not during ISA string parsing Conor Dooley
2023-06-12 7:33 ` Sunil V L
2023-06-07 20:28 ` [PATCH v3 4/7] RISC-V: rework comments in ISA string parser Conor Dooley
2023-06-07 20:28 ` [PATCH v3 5/7] RISC-V: remove decrement/increment dance " Conor Dooley
2023-06-12 7:52 ` Sunil V L
2023-06-07 20:28 ` [PATCH v3 6/7] dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support Conor Dooley
2023-06-14 23:02 ` Rob Herring
2023-06-07 20:28 ` [PATCH v3 7/7] RISC-V: always report presence of extensions formerly part of the base ISA Conor Dooley
2023-06-25 23:17 ` [PATCH v3 0/7] ISA string parser cleanups Palmer Dabbelt
2023-06-25 23:20 ` patchwork-bot+linux-riscv
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