From: Jason Gunthorpe <jgg@ziepe.ca>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Frank Rowand <frowand.list@gmail.com>,
Atish Patra <atishp@atishpatra.org>,
Andrew Jones <ajones@ventanamicro.com>,
Conor Dooley <conor@kernel.org>,
Saravana Kannan <saravanak@google.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, iommu@lists.linux.dev,
Vincent Chen <vincent.chen@sifive.com>
Subject: Re: [PATCH v4 06/10] irqchip/riscv-imsic: Improve IOMMU DMA support
Date: Wed, 14 Jun 2023 11:46:00 -0300 [thread overview]
Message-ID: <ZInSqC6b7RPD1nzX@ziepe.ca> (raw)
In-Reply-To: <20230613153415.350528-7-apatel@ventanamicro.com>
On Tue, Jun 13, 2023 at 09:04:11PM +0530, Anup Patel wrote:
> We have a separate RISC-V IMSIC MSI address for each CPU so changing
> MSI (or IRQ) affinity results in re-programming of MSI address in
> the PCIe (or platform) device.
>
> Currently, the iommu_dma_prepare_msi() is called only once at the
> time of IRQ allocation so IOMMU DMA domain will only have mapping
> for one MSI page. This means iommu_dma_compose_msi_msg() called
> by imsic_irq_compose_msi_msg() will always use the same MSI page
> irrespective to target CPU MSI address. In other words, changing
> MSI (or IRQ) affinity for device using IOMMU DMA domain will not
> work.
You didn't answer my question from last time - there seems to be no
iommu driver here so why are you messing with iommu_dma_prepare_msi()?
This path is only for platforms that have IOMMU drivers that translate
the MSI window. You should add this code to link the interrupt
controller to the iommu driver when you introduce the iommu driver,
not in this series?
And, as I said before, I'd like to NOT see new users of
iommu_dma_prepare_msi() since it is a very problematic API.
This hacking of it here is not making it better :(
Jason
next prev parent reply other threads:[~2023-06-14 14:46 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-13 15:34 [PATCH v4 00/10] Linux RISC-V AIA Support Anup Patel
2023-06-13 15:34 ` [PATCH v4 01/10] RISC-V: Add riscv_fw_parent_hartid() function Anup Patel
2023-06-13 15:34 ` [PATCH v4 02/10] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-06-13 15:34 ` [PATCH v4 03/10] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-06-13 15:34 ` [PATCH v4 04/10] irqchip: Add RISC-V incoming MSI controller driver Anup Patel
2023-06-13 15:34 ` [PATCH v4 05/10] irqchip/riscv-imsic: Add support for PCI MSI irqdomain Anup Patel
2023-06-13 15:34 ` [PATCH v4 06/10] irqchip/riscv-imsic: Improve IOMMU DMA support Anup Patel
2023-06-14 14:46 ` Jason Gunthorpe [this message]
2023-06-14 16:17 ` Anup Patel
2023-06-14 16:50 ` Jason Gunthorpe
2023-06-15 5:46 ` Anup Patel
2023-06-13 15:34 ` [PATCH v4 07/10] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-06-14 19:27 ` Conor Dooley
2023-06-15 5:47 ` Anup Patel
2023-06-13 15:34 ` [PATCH v4 08/10] irqchip: Add RISC-V advanced PLIC driver Anup Patel
2023-06-15 19:17 ` Saravana Kannan
2023-06-15 19:31 ` Conor Dooley
2023-06-15 20:45 ` Saravana Kannan
2023-06-15 21:11 ` Conor Dooley
2023-06-16 2:01 ` Anup Patel
2023-06-16 22:05 ` Saravana Kannan
2023-06-19 6:13 ` Anup Patel
2023-06-22 20:56 ` Saravana Kannan
2023-06-23 11:47 ` Anup Patel
2023-06-23 12:49 ` Marc Zyngier
2023-06-23 13:52 ` Anup Patel
2023-06-13 15:34 ` [PATCH v4 09/10] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-06-13 15:34 ` [PATCH v4 10/10] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
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