From: Christoph Hellwig <hch@infradead.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Christoph Hellwig <hch@infradead.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Shuah Khan <shuah@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
Mayuresh Chitale <mchitale@ventanamicro.com>,
devicetree@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org
Subject: Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
Date: Wed, 4 Oct 2023 23:49:56 -0700 [thread overview]
Message-ID: <ZR5clPwviAN2SHVY@infradead.org> (raw)
In-Reply-To: <CAK9=C2XyQtHy3__i+fahbi49=j5Z3Z_Bv5s3Ptqjmuaa5q18LA@mail.gmail.com>
On Mon, Oct 02, 2023 at 09:06:08PM +0530, Anup Patel wrote:
> > extensions?
> >
>
> We already have few T-Head specific extensions so Linux RISC-V
> does allow vendor extensions.
Only for kernel internal operation and to actually boot the
chip. IMHO still the wrong tradeoff, but very different from actually
user visible extensions that will lead to fragmentation of the
ecoysystem.
next prev parent reply other threads:[~2023-10-05 6:50 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-19 3:53 [PATCH 0/7] KVM RISC-V Conditional Operations Anup Patel
2023-09-19 3:53 ` [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string Anup Patel
2023-09-19 7:26 ` Conor Dooley
2023-09-25 13:30 ` Anup Patel
2023-09-20 7:38 ` Andrew Jones
2023-10-02 6:27 ` Christoph Hellwig
2023-10-02 15:36 ` Anup Patel
2023-10-05 6:49 ` Christoph Hellwig [this message]
2023-09-19 3:53 ` [PATCH 2/7] RISC-V: Detect Zicond " Anup Patel
2023-09-19 7:27 ` Conor Dooley
2023-09-25 13:31 ` Anup Patel
2023-09-20 7:44 ` Andrew Jones
2023-09-25 13:31 ` Anup Patel
2023-09-19 3:53 ` [PATCH 3/7] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM Anup Patel
2023-09-20 7:46 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 4/7] RISC-V: KVM: Allow Zicond " Anup Patel
2023-09-20 7:46 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 5/7] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Anup Patel
2023-09-20 7:50 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 6/7] KVM: riscv: selftests: Add smstateen registers " Anup Patel
2023-09-20 8:13 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 7/7] KVM: riscv: selftests: Add condops extensions " Anup Patel
2023-09-20 8:18 ` Andrew Jones
2023-09-25 13:32 ` Anup Patel
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