[RFC PATCH v3 0/7] Add FS035VG158 panel

[RFC PATCH v3 0/7] Add FS035VG158 panel

[John Watts]

Hello there,

This RFC introduces support for the FS035VG158 LCD panel, cleaning up
the nv3052c driver on the way and documentating existing panel code.

John.

v2 -> v3:
- Dropped patches that add extra sleep time

v1 -> v2:
- Fixed a variable declaration style error
- Cleaned up device tree yaml

John Watts (7):
  drm/panel: nv3052c: Document known register names
  drm/panel: nv3052c: Add SPI device IDs
  drm/panel: nv3052c: Allow specifying registers per panel
  drm/panel: nv3052c: Add Fascontek FS035VG158 LCD display
  dt-bindings: display: panel: Clean up leadtek,ltk035c5444t properties
  dt-bindings: vendor-prefixes: Add fascontek
  dt-bindings: display: panel: add Fascontek FS035VG158 panel

 .../display/panel/fascontek,fs035vg158.yaml   |  56 ++
 .../display/panel/leadtek,ltk035c5444t.yaml   |   8 +-
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 .../gpu/drm/panel/panel-newvision-nv3052c.c   | 515 +++++++++++++-----
 4 files changed, 437 insertions(+), 144 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/panel/fascontek,fs035vg158.yaml

-- 
2.42.0

[RFC PATCH v3 1/7] drm/panel: nv3052c: Document known register names

[John Watts]

Many of these registers have a known name in the public datasheet.
Document them as comments for reference.

Signed-off-by: John Watts <contact@jookia.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
---
 .../gpu/drm/panel/panel-newvision-nv3052c.c   | 261 +++++++++---------
 1 file changed, 132 insertions(+), 129 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
index 71e57de6d8b2..589431523ce7 100644
--- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
+++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
@@ -42,9 +42,9 @@ struct nv3052c_reg {
 };
 
 static const struct nv3052c_reg nv3052c_panel_regs[] = {
-	{ 0xff, 0x30 },
-	{ 0xff, 0x52 },
-	{ 0xff, 0x01 },
+	// EXTC Command set enable, select page 1
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 },
+	// Mostly unknown registers
 	{ 0xe3, 0x00 },
 	{ 0x40, 0x00 },
 	{ 0x03, 0x40 },
@@ -62,15 +62,15 @@ static const struct nv3052c_reg nv3052c_panel_regs[] = {
 	{ 0x25, 0x06 },
 	{ 0x26, 0x14 },
 	{ 0x27, 0x14 },
-	{ 0x38, 0xcc },
-	{ 0x39, 0xd7 },
-	{ 0x3a, 0x4a },
+	{ 0x38, 0xcc }, // VCOM_ADJ1
+	{ 0x39, 0xd7 }, // VCOM_ADJ2
+	{ 0x3a, 0x4a }, // VCOM_ADJ3
 	{ 0x28, 0x40 },
 	{ 0x29, 0x01 },
 	{ 0x2a, 0xdf },
 	{ 0x49, 0x3c },
-	{ 0x91, 0x77 },
-	{ 0x92, 0x77 },
+	{ 0x91, 0x77 }, // EXTPW_CTRL2
+	{ 0x92, 0x77 }, // EXTPW_CTRL3
 	{ 0xa0, 0x55 },
 	{ 0xa1, 0x50 },
 	{ 0xa4, 0x9c },
@@ -94,123 +94,126 @@ static const struct nv3052c_reg nv3052c_panel_regs[] = {
 	{ 0xb8, 0x26 },
 	{ 0xf0, 0x00 },
 	{ 0xf6, 0xc0 },
-	{ 0xff, 0x30 },
-	{ 0xff, 0x52 },
-	{ 0xff, 0x02 },
-	{ 0xb0, 0x0b },
-	{ 0xb1, 0x16 },
-	{ 0xb2, 0x17 },
-	{ 0xb3, 0x2c },
-	{ 0xb4, 0x32 },
-	{ 0xb5, 0x3b },
-	{ 0xb6, 0x29 },
-	{ 0xb7, 0x40 },
-	{ 0xb8, 0x0d },
-	{ 0xb9, 0x05 },
-	{ 0xba, 0x12 },
-	{ 0xbb, 0x10 },
-	{ 0xbc, 0x12 },
-	{ 0xbd, 0x15 },
-	{ 0xbe, 0x19 },
-	{ 0xbf, 0x0e },
-	{ 0xc0, 0x16 },
-	{ 0xc1, 0x0a },
-	{ 0xd0, 0x0c },
-	{ 0xd1, 0x17 },
-	{ 0xd2, 0x14 },
-	{ 0xd3, 0x2e },
-	{ 0xd4, 0x32 },
-	{ 0xd5, 0x3c },
-	{ 0xd6, 0x22 },
-	{ 0xd7, 0x3d },
-	{ 0xd8, 0x0d },
-	{ 0xd9, 0x07 },
-	{ 0xda, 0x13 },
-	{ 0xdb, 0x13 },
-	{ 0xdc, 0x11 },
-	{ 0xdd, 0x15 },
-	{ 0xde, 0x19 },
-	{ 0xdf, 0x10 },
-	{ 0xe0, 0x17 },
-	{ 0xe1, 0x0a },
-	{ 0xff, 0x30 },
-	{ 0xff, 0x52 },
-	{ 0xff, 0x03 },
-	{ 0x00, 0x2a },
-	{ 0x01, 0x2a },
-	{ 0x02, 0x2a },
-	{ 0x03, 0x2a },
-	{ 0x04, 0x61 },
-	{ 0x05, 0x80 },
-	{ 0x06, 0xc7 },
-	{ 0x07, 0x01 },
-	{ 0x08, 0x03 },
-	{ 0x09, 0x04 },
-	{ 0x70, 0x22 },
-	{ 0x71, 0x80 },
-	{ 0x30, 0x2a },
-	{ 0x31, 0x2a },
-	{ 0x32, 0x2a },
-	{ 0x33, 0x2a },
-	{ 0x34, 0x61 },
-	{ 0x35, 0xc5 },
-	{ 0x36, 0x80 },
-	{ 0x37, 0x23 },
-	{ 0x40, 0x03 },
-	{ 0x41, 0x04 },
-	{ 0x42, 0x05 },
-	{ 0x43, 0x06 },
-	{ 0x44, 0x11 },
-	{ 0x45, 0xe8 },
-	{ 0x46, 0xe9 },
-	{ 0x47, 0x11 },
-	{ 0x48, 0xea },
-	{ 0x49, 0xeb },
-	{ 0x50, 0x07 },
-	{ 0x51, 0x08 },
-	{ 0x52, 0x09 },
-	{ 0x53, 0x0a },
-	{ 0x54, 0x11 },
-	{ 0x55, 0xec },
-	{ 0x56, 0xed },
-	{ 0x57, 0x11 },
-	{ 0x58, 0xef },
-	{ 0x59, 0xf0 },
-	{ 0xb1, 0x01 },
-	{ 0xb4, 0x15 },
-	{ 0xb5, 0x16 },
-	{ 0xb6, 0x09 },
-	{ 0xb7, 0x0f },
-	{ 0xb8, 0x0d },
-	{ 0xb9, 0x0b },
-	{ 0xba, 0x00 },
-	{ 0xc7, 0x02 },
-	{ 0xca, 0x17 },
-	{ 0xcb, 0x18 },
-	{ 0xcc, 0x0a },
-	{ 0xcd, 0x10 },
-	{ 0xce, 0x0e },
-	{ 0xcf, 0x0c },
-	{ 0xd0, 0x00 },
-	{ 0x81, 0x00 },
-	{ 0x84, 0x15 },
-	{ 0x85, 0x16 },
-	{ 0x86, 0x10 },
-	{ 0x87, 0x0a },
-	{ 0x88, 0x0c },
-	{ 0x89, 0x0e },
-	{ 0x8a, 0x02 },
-	{ 0x97, 0x00 },
-	{ 0x9a, 0x17 },
-	{ 0x9b, 0x18 },
-	{ 0x9c, 0x0f },
-	{ 0x9d, 0x09 },
-	{ 0x9e, 0x0b },
-	{ 0x9f, 0x0d },
-	{ 0xa0, 0x01 },
-	{ 0xff, 0x30 },
-	{ 0xff, 0x52 },
-	{ 0xff, 0x02 },
+	// EXTC Command set enable, select page 2
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
+	// Set gray scale voltage to adjust gamma
+	{ 0xb0, 0x0b }, // PGAMVR0
+	{ 0xb1, 0x16 }, // PGAMVR1
+	{ 0xb2, 0x17 }, // PGAMVR2
+	{ 0xb3, 0x2c }, // PGAMVR3
+	{ 0xb4, 0x32 }, // PGAMVR4
+	{ 0xb5, 0x3b }, // PGAMVR5
+	{ 0xb6, 0x29 }, // PGAMPR0
+	{ 0xb7, 0x40 }, // PGAMPR1
+	{ 0xb8, 0x0d }, // PGAMPK0
+	{ 0xb9, 0x05 }, // PGAMPK1
+	{ 0xba, 0x12 }, // PGAMPK2
+	{ 0xbb, 0x10 }, // PGAMPK3
+	{ 0xbc, 0x12 }, // PGAMPK4
+	{ 0xbd, 0x15 }, // PGAMPK5
+	{ 0xbe, 0x19 }, // PGAMPK6
+	{ 0xbf, 0x0e }, // PGAMPK7
+	{ 0xc0, 0x16 }, // PGAMPK8
+	{ 0xc1, 0x0a }, // PGAMPK9
+	// Set gray scale voltage to adjust gamma
+	{ 0xd0, 0x0c }, // NGAMVR0
+	{ 0xd1, 0x17 }, // NGAMVR0
+	{ 0xd2, 0x14 }, // NGAMVR1
+	{ 0xd3, 0x2e }, // NGAMVR2
+	{ 0xd4, 0x32 }, // NGAMVR3
+	{ 0xd5, 0x3c }, // NGAMVR4
+	{ 0xd6, 0x22 }, // NGAMPR0
+	{ 0xd7, 0x3d }, // NGAMPR1
+	{ 0xd8, 0x0d }, // NGAMPK0
+	{ 0xd9, 0x07 }, // NGAMPK1
+	{ 0xda, 0x13 }, // NGAMPK2
+	{ 0xdb, 0x13 }, // NGAMPK3
+	{ 0xdc, 0x11 }, // NGAMPK4
+	{ 0xdd, 0x15 }, // NGAMPK5
+	{ 0xde, 0x19 }, // NGAMPK6
+	{ 0xdf, 0x10 }, // NGAMPK7
+	{ 0xe0, 0x17 }, // NGAMPK8
+	{ 0xe1, 0x0a }, // NGAMPK9
+	// EXTC Command set enable, select page 3
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 },
+	// Set various timing settings
+	{ 0x00, 0x2a }, // GIP_VST_1
+	{ 0x01, 0x2a }, // GIP_VST_2
+	{ 0x02, 0x2a }, // GIP_VST_3
+	{ 0x03, 0x2a }, // GIP_VST_4
+	{ 0x04, 0x61 }, // GIP_VST_5
+	{ 0x05, 0x80 }, // GIP_VST_6
+	{ 0x06, 0xc7 }, // GIP_VST_7
+	{ 0x07, 0x01 }, // GIP_VST_8
+	{ 0x08, 0x03 }, // GIP_VST_9
+	{ 0x09, 0x04 }, // GIP_VST_10
+	{ 0x70, 0x22 }, // GIP_ECLK1
+	{ 0x71, 0x80 }, // GIP_ECLK2
+	{ 0x30, 0x2a }, // GIP_CLK_1
+	{ 0x31, 0x2a }, // GIP_CLK_2
+	{ 0x32, 0x2a }, // GIP_CLK_3
+	{ 0x33, 0x2a }, // GIP_CLK_4
+	{ 0x34, 0x61 }, // GIP_CLK_5
+	{ 0x35, 0xc5 }, // GIP_CLK_6
+	{ 0x36, 0x80 }, // GIP_CLK_7
+	{ 0x37, 0x23 }, // GIP_CLK_8
+	{ 0x40, 0x03 }, // GIP_CLKA_1
+	{ 0x41, 0x04 }, // GIP_CLKA_2
+	{ 0x42, 0x05 }, // GIP_CLKA_3
+	{ 0x43, 0x06 }, // GIP_CLKA_4
+	{ 0x44, 0x11 }, // GIP_CLKA_5
+	{ 0x45, 0xe8 }, // GIP_CLKA_6
+	{ 0x46, 0xe9 }, // GIP_CLKA_7
+	{ 0x47, 0x11 }, // GIP_CLKA_8
+	{ 0x48, 0xea }, // GIP_CLKA_9
+	{ 0x49, 0xeb }, // GIP_CLKA_10
+	{ 0x50, 0x07 }, // GIP_CLKB_1
+	{ 0x51, 0x08 }, // GIP_CLKB_2
+	{ 0x52, 0x09 }, // GIP_CLKB_3
+	{ 0x53, 0x0a }, // GIP_CLKB_4
+	{ 0x54, 0x11 }, // GIP_CLKB_5
+	{ 0x55, 0xec }, // GIP_CLKB_6
+	{ 0x56, 0xed }, // GIP_CLKB_7
+	{ 0x57, 0x11 }, // GIP_CLKB_8
+	{ 0x58, 0xef }, // GIP_CLKB_9
+	{ 0x59, 0xf0 }, // GIP_CLKB_10
+	// Map internal GOA signals to GOA output pad
+	{ 0xb1, 0x01 }, // PANELD2U2
+	{ 0xb4, 0x15 }, // PANELD2U5
+	{ 0xb5, 0x16 }, // PANELD2U6
+	{ 0xb6, 0x09 }, // PANELD2U7
+	{ 0xb7, 0x0f }, // PANELD2U8
+	{ 0xb8, 0x0d }, // PANELD2U9
+	{ 0xb9, 0x0b }, // PANELD2U10
+	{ 0xba, 0x00 }, // PANELD2U11
+	{ 0xc7, 0x02 }, // PANELD2U24
+	{ 0xca, 0x17 }, // PANELD2U27
+	{ 0xcb, 0x18 }, // PANELD2U28
+	{ 0xcc, 0x0a }, // PANELD2U29
+	{ 0xcd, 0x10 }, // PANELD2U30
+	{ 0xce, 0x0e }, // PANELD2U31
+	{ 0xcf, 0x0c }, // PANELD2U32
+	{ 0xd0, 0x00 }, // PANELD2U33
+	// Map internal GOA signals to GOA output pad
+	{ 0x81, 0x00 }, // PANELU2D2
+	{ 0x84, 0x15 }, // PANELU2D5
+	{ 0x85, 0x16 }, // PANELU2D6
+	{ 0x86, 0x10 }, // PANELU2D7
+	{ 0x87, 0x0a }, // PANELU2D8
+	{ 0x88, 0x0c }, // PANELU2D9
+	{ 0x89, 0x0e }, // PANELU2D10
+	{ 0x8a, 0x02 }, // PANELU2D11
+	{ 0x97, 0x00 }, // PANELU2D24
+	{ 0x9a, 0x17 }, // PANELU2D27
+	{ 0x9b, 0x18 }, // PANELU2D28
+	{ 0x9c, 0x0f }, // PANELU2D29
+	{ 0x9d, 0x09 }, // PANELU2D30
+	{ 0x9e, 0x0b }, // PANELU2D31
+	{ 0x9f, 0x0d }, // PANELU2D32
+	{ 0xa0, 0x01 }, // PANELU2D33
+	// EXTC Command set enable, select page 2
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
+	// Unknown registers
 	{ 0x01, 0x01 },
 	{ 0x02, 0xda },
 	{ 0x03, 0xba },
@@ -227,10 +230,10 @@ static const struct nv3052c_reg nv3052c_panel_regs[] = {
 	{ 0x0e, 0x48 },
 	{ 0x0f, 0x38 },
 	{ 0x10, 0x2b },
-	{ 0xff, 0x30 },
-	{ 0xff, 0x52 },
-	{ 0xff, 0x00 },
-	{ 0x36, 0x0a },
+	// EXTC Command set enable, select page 0
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 },
+	// Display Access Control
+	{ 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
 };
 
 static inline struct nv3052c *to_nv3052c(struct drm_panel *panel)
-- 
2.42.0

[RFC PATCH v3 2/7] drm/panel: nv3052c: Add SPI device IDs

[John Watts]

SPI drivers needs their own list of compatible device IDs in order
for automatic module loading to work. Add those for this driver.

Signed-off-by: John Watts <contact@jookia.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
---
 drivers/gpu/drm/panel/panel-newvision-nv3052c.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
index 589431523ce7..90dea21f9856 100644
--- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
+++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
@@ -465,6 +465,12 @@ static const struct nv3052c_panel_info ltk035c5444t_panel_info = {
 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
 };
 
+static const struct spi_device_id nv3052c_ids[] = {
+	{ "ltk035c5444t", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(spi, nv3052c_ids);
+
 static const struct of_device_id nv3052c_of_match[] = {
 	{ .compatible = "leadtek,ltk035c5444t", .data = &ltk035c5444t_panel_info },
 	{ /* sentinel */ }
@@ -476,6 +482,7 @@ static struct spi_driver nv3052c_driver = {
 		.name = "nv3052c",
 		.of_match_table = nv3052c_of_match,
 	},
+	.id_table = nv3052c_ids,
 	.probe = nv3052c_probe,
 	.remove = nv3052c_remove,
 };
-- 
2.42.0

[RFC PATCH v3 3/7] drm/panel: nv3052c: Allow specifying registers per panel

[John Watts]

Panel initialization registers are per-display and not tied to the
controller itself. Different panels will specify their own registers.
Attach the sequences to the panel info struct so future panels
can specify their own sequences.

Signed-off-by: John Watts <contact@jookia.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
---
 .../gpu/drm/panel/panel-newvision-nv3052c.c   | 24 ++++++++++++-------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
index 90dea21f9856..382062a79ba8 100644
--- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
+++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
@@ -20,11 +20,18 @@
 #include <drm/drm_modes.h>
 #include <drm/drm_panel.h>
 
+struct nv3052c_reg {
+	u8 cmd;
+	u8 val;
+};
+
 struct nv3052c_panel_info {
 	const struct drm_display_mode *display_modes;
 	unsigned int num_modes;
 	u16 width_mm, height_mm;
 	u32 bus_format, bus_flags;
+	const struct nv3052c_reg *panel_regs;
+	int panel_regs_len;
 };
 
 struct nv3052c {
@@ -36,12 +43,7 @@ struct nv3052c {
 	struct gpio_desc *reset_gpio;
 };
 
-struct nv3052c_reg {
-	u8 cmd;
-	u8 val;
-};
-
-static const struct nv3052c_reg nv3052c_panel_regs[] = {
+static const struct nv3052c_reg ltk035c5444t_panel_regs[] = {
 	// EXTC Command set enable, select page 1
 	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 },
 	// Mostly unknown registers
@@ -244,6 +246,8 @@ static inline struct nv3052c *to_nv3052c(struct drm_panel *panel)
 static int nv3052c_prepare(struct drm_panel *panel)
 {
 	struct nv3052c *priv = to_nv3052c(panel);
+	const struct nv3052c_reg *panel_regs = priv->panel_info->panel_regs;
+	int panel_regs_len = priv->panel_info->panel_regs_len;
 	struct mipi_dbi *dbi = &priv->dbi;
 	unsigned int i;
 	int err;
@@ -260,9 +264,9 @@ static int nv3052c_prepare(struct drm_panel *panel)
 	gpiod_set_value_cansleep(priv->reset_gpio, 0);
 	usleep_range(5000, 20000);
 
-	for (i = 0; i < ARRAY_SIZE(nv3052c_panel_regs); i++) {
-		err = mipi_dbi_command(dbi, nv3052c_panel_regs[i].cmd,
-				       nv3052c_panel_regs[i].val);
+	for (i = 0; i < panel_regs_len; i++) {
+		err = mipi_dbi_command(dbi, panel_regs[i].cmd,
+				       panel_regs[i].val);
 
 		if (err) {
 			dev_err(priv->dev, "Unable to set register: %d\n", err);
@@ -463,6 +467,8 @@ static const struct nv3052c_panel_info ltk035c5444t_panel_info = {
 	.height_mm = 64,
 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+	.panel_regs = ltk035c5444t_panel_regs,
+	.panel_regs_len = ARRAY_SIZE(ltk035c5444t_panel_regs),
 };
 
 static const struct spi_device_id nv3052c_ids[] = {
-- 
2.42.0

[RFC PATCH v3 4/7] drm/panel: nv3052c: Add Fascontek FS035VG158 LCD display

[John Watts]

This display is extremely similar to the LTK035C5444T, but still has
some minor variations in panel initialization.

Signed-off-by: John Watts <contact@jookia.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
---
 .../gpu/drm/panel/panel-newvision-nv3052c.c   | 223 ++++++++++++++++++
 1 file changed, 223 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
index 382062a79ba8..79f1f67df13c 100644
--- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
+++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
@@ -238,6 +238,201 @@ static const struct nv3052c_reg ltk035c5444t_panel_regs[] = {
 	{ 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
 };
 
+static const struct nv3052c_reg fs035vg158_panel_regs[] = {
+	// EXTC Command set enable, select page 1
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 },
+	// Mostly unknown registers
+	{ 0xe3, 0x00 },
+	{ 0x40, 0x00 },
+	{ 0x03, 0x40 },
+	{ 0x04, 0x00 },
+	{ 0x05, 0x03 },
+	{ 0x08, 0x00 },
+	{ 0x09, 0x07 },
+	{ 0x0a, 0x01 },
+	{ 0x0b, 0x32 },
+	{ 0x0c, 0x32 },
+	{ 0x0d, 0x0b },
+	{ 0x0e, 0x00 },
+	{ 0x23, 0x20 }, // RGB interface control: DE MODE PCLK-N
+	{ 0x24, 0x0c },
+	{ 0x25, 0x06 },
+	{ 0x26, 0x14 },
+	{ 0x27, 0x14 },
+	{ 0x38, 0x9c }, //VCOM_ADJ1, different to ltk035c5444t
+	{ 0x39, 0xa7 }, //VCOM_ADJ2, different to ltk035c5444t
+	{ 0x3a, 0x50 }, //VCOM_ADJ3, different to ltk035c5444t
+	{ 0x28, 0x40 },
+	{ 0x29, 0x01 },
+	{ 0x2a, 0xdf },
+	{ 0x49, 0x3c },
+	{ 0x91, 0x57 }, //EXTPW_CTRL2, different to ltk035c5444t
+	{ 0x92, 0x57 }, //EXTPW_CTRL3, different to ltk035c5444t
+	{ 0xa0, 0x55 },
+	{ 0xa1, 0x50 },
+	{ 0xa4, 0x9c },
+	{ 0xa7, 0x02 },
+	{ 0xa8, 0x01 },
+	{ 0xa9, 0x01 },
+	{ 0xaa, 0xfc },
+	{ 0xab, 0x28 },
+	{ 0xac, 0x06 },
+	{ 0xad, 0x06 },
+	{ 0xae, 0x06 },
+	{ 0xaf, 0x03 },
+	{ 0xb0, 0x08 },
+	{ 0xb1, 0x26 },
+	{ 0xb2, 0x28 },
+	{ 0xb3, 0x28 },
+	{ 0xb4, 0x03 }, // Unknown, different to ltk035c5444
+	{ 0xb5, 0x08 },
+	{ 0xb6, 0x26 },
+	{ 0xb7, 0x08 },
+	{ 0xb8, 0x26 },
+	{ 0xf0, 0x00 },
+	{ 0xf6, 0xc0 },
+	// EXTC Command set enable, select page 0
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
+	// Set gray scale voltage to adjust gamma
+	{ 0xb0, 0x0b }, // PGAMVR0
+	{ 0xb1, 0x16 }, // PGAMVR1
+	{ 0xb2, 0x17 }, // PGAMVR2
+	{ 0xb3, 0x2c }, // PGAMVR3
+	{ 0xb4, 0x32 }, // PGAMVR4
+	{ 0xb5, 0x3b }, // PGAMVR5
+	{ 0xb6, 0x29 }, // PGAMPR0
+	{ 0xb7, 0x40 }, // PGAMPR1
+	{ 0xb8, 0x0d }, // PGAMPK0
+	{ 0xb9, 0x05 }, // PGAMPK1
+	{ 0xba, 0x12 }, // PGAMPK2
+	{ 0xbb, 0x10 }, // PGAMPK3
+	{ 0xbc, 0x12 }, // PGAMPK4
+	{ 0xbd, 0x15 }, // PGAMPK5
+	{ 0xbe, 0x19 }, // PGAMPK6
+	{ 0xbf, 0x0e }, // PGAMPK7
+	{ 0xc0, 0x16 }, // PGAMPK8
+	{ 0xc1, 0x0a }, // PGAMPK9
+	// Set gray scale voltage to adjust gamma
+	{ 0xd0, 0x0c }, // NGAMVR0
+	{ 0xd1, 0x17 }, // NGAMVR0
+	{ 0xd2, 0x14 }, // NGAMVR1
+	{ 0xd3, 0x2e }, // NGAMVR2
+	{ 0xd4, 0x32 }, // NGAMVR3
+	{ 0xd5, 0x3c }, // NGAMVR4
+	{ 0xd6, 0x22 }, // NGAMPR0
+	{ 0xd7, 0x3d }, // NGAMPR1
+	{ 0xd8, 0x0d }, // NGAMPK0
+	{ 0xd9, 0x07 }, // NGAMPK1
+	{ 0xda, 0x13 }, // NGAMPK2
+	{ 0xdb, 0x13 }, // NGAMPK3
+	{ 0xdc, 0x11 }, // NGAMPK4
+	{ 0xdd, 0x15 }, // NGAMPK5
+	{ 0xde, 0x19 }, // NGAMPK6
+	{ 0xdf, 0x10 }, // NGAMPK7
+	{ 0xe0, 0x17 }, // NGAMPK8
+	{ 0xe1, 0x0a }, // NGAMPK9
+	// EXTC Command set enable, select page 3
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 },
+	// Set various timing settings
+	{ 0x00, 0x2a }, // GIP_VST_1
+	{ 0x01, 0x2a }, // GIP_VST_2
+	{ 0x02, 0x2a }, // GIP_VST_3
+	{ 0x03, 0x2a }, // GIP_VST_4
+	{ 0x04, 0x61 }, // GIP_VST_5
+	{ 0x05, 0x80 }, // GIP_VST_6
+	{ 0x06, 0xc7 }, // GIP_VST_7
+	{ 0x07, 0x01 }, // GIP_VST_8
+	{ 0x08, 0x03 }, // GIP_VST_9
+	{ 0x09, 0x04 }, // GIP_VST_10
+	{ 0x70, 0x22 }, // GIP_ECLK1
+	{ 0x71, 0x80 }, // GIP_ECLK2
+	{ 0x30, 0x2a }, // GIP_CLK_1
+	{ 0x31, 0x2a }, // GIP_CLK_2
+	{ 0x32, 0x2a }, // GIP_CLK_3
+	{ 0x33, 0x2a }, // GIP_CLK_4
+	{ 0x34, 0x61 }, // GIP_CLK_5
+	{ 0x35, 0xc5 }, // GIP_CLK_6
+	{ 0x36, 0x80 }, // GIP_CLK_7
+	{ 0x37, 0x23 }, // GIP_CLK_8
+	{ 0x40, 0x03 }, // GIP_CLKA_1
+	{ 0x41, 0x04 }, // GIP_CLKA_2
+	{ 0x42, 0x05 }, // GIP_CLKA_3
+	{ 0x43, 0x06 }, // GIP_CLKA_4
+	{ 0x44, 0x11 }, // GIP_CLKA_5
+	{ 0x45, 0xe8 }, // GIP_CLKA_6
+	{ 0x46, 0xe9 }, // GIP_CLKA_7
+	{ 0x47, 0x11 }, // GIP_CLKA_8
+	{ 0x48, 0xea }, // GIP_CLKA_9
+	{ 0x49, 0xeb }, // GIP_CLKA_10
+	{ 0x50, 0x07 }, // GIP_CLKB_1
+	{ 0x51, 0x08 }, // GIP_CLKB_2
+	{ 0x52, 0x09 }, // GIP_CLKB_3
+	{ 0x53, 0x0a }, // GIP_CLKB_4
+	{ 0x54, 0x11 }, // GIP_CLKB_5
+	{ 0x55, 0xec }, // GIP_CLKB_6
+	{ 0x56, 0xed }, // GIP_CLKB_7
+	{ 0x57, 0x11 }, // GIP_CLKB_8
+	{ 0x58, 0xef }, // GIP_CLKB_9
+	{ 0x59, 0xf0 }, // GIP_CLKB_10
+	// Map internal GOA signals to GOA output pad
+	{ 0xb1, 0x01 }, // PANELD2U2
+	{ 0xb4, 0x15 }, // PANELD2U5
+	{ 0xb5, 0x16 }, // PANELD2U6
+	{ 0xb6, 0x09 }, // PANELD2U7
+	{ 0xb7, 0x0f }, // PANELD2U8
+	{ 0xb8, 0x0d }, // PANELD2U9
+	{ 0xb9, 0x0b }, // PANELD2U10
+	{ 0xba, 0x00 }, // PANELD2U11
+	{ 0xc7, 0x02 }, // PANELD2U24
+	{ 0xca, 0x17 }, // PANELD2U27
+	{ 0xcb, 0x18 }, // PANELD2U28
+	{ 0xcc, 0x0a }, // PANELD2U29
+	{ 0xcd, 0x10 }, // PANELD2U30
+	{ 0xce, 0x0e }, // PANELD2U31
+	{ 0xcf, 0x0c }, // PANELD2U32
+	{ 0xd0, 0x00 }, // PANELD2U33
+	// Map internal GOA signals to GOA output pad
+	{ 0x81, 0x00 }, // PANELU2D2
+	{ 0x84, 0x15 }, // PANELU2D5
+	{ 0x85, 0x16 }, // PANELU2D6
+	{ 0x86, 0x10 }, // PANELU2D7
+	{ 0x87, 0x0a }, // PANELU2D8
+	{ 0x88, 0x0c }, // PANELU2D9
+	{ 0x89, 0x0e }, // PANELU2D10
+	{ 0x8a, 0x02 }, // PANELU2D11
+	{ 0x97, 0x00 }, // PANELU2D24
+	{ 0x9a, 0x17 }, // PANELU2D27
+	{ 0x9b, 0x18 }, // PANELU2D28
+	{ 0x9c, 0x0f }, // PANELU2D29
+	{ 0x9d, 0x09 }, // PANELU2D30
+	{ 0x9e, 0x0b }, // PANELU2D31
+	{ 0x9f, 0x0d }, // PANELU2D32
+	{ 0xa0, 0x01 }, // PANELU2D33
+	// EXTC Command set enable, select page 2
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
+	// Unknown registers
+	{ 0x01, 0x01 },
+	{ 0x02, 0xda },
+	{ 0x03, 0xba },
+	{ 0x04, 0xa8 },
+	{ 0x05, 0x9a },
+	{ 0x06, 0x70 },
+	{ 0x07, 0xff },
+	{ 0x08, 0x91 },
+	{ 0x09, 0x90 },
+	{ 0x0a, 0xff },
+	{ 0x0b, 0x8f },
+	{ 0x0c, 0x60 },
+	{ 0x0d, 0x58 },
+	{ 0x0e, 0x48 },
+	{ 0x0f, 0x38 },
+	{ 0x10, 0x2b },
+	// EXTC Command set enable, select page 0
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 },
+	// Display Access Control
+	{ 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
+};
+
 static inline struct nv3052c *to_nv3052c(struct drm_panel *panel)
 {
 	return container_of(panel, struct nv3052c, panel);
@@ -460,6 +655,21 @@ static const struct drm_display_mode ltk035c5444t_modes[] = {
 	},
 };
 
+static const struct drm_display_mode fs035vg158_modes[] = {
+	{ /* 60 Hz */
+		.clock = 21000,
+		.hdisplay = 640,
+		.hsync_start = 640 + 34,
+		.hsync_end = 640 + 34 + 4,
+		.htotal = 640 + 34 + 4 + 20,
+		.vdisplay = 480,
+		.vsync_start = 480 + 12,
+		.vsync_end = 480 + 12 + 4,
+		.vtotal = 480 + 12 + 4 + 6,
+		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+	},
+};
+
 static const struct nv3052c_panel_info ltk035c5444t_panel_info = {
 	.display_modes = ltk035c5444t_modes,
 	.num_modes = ARRAY_SIZE(ltk035c5444t_modes),
@@ -471,14 +681,27 @@ static const struct nv3052c_panel_info ltk035c5444t_panel_info = {
 	.panel_regs_len = ARRAY_SIZE(ltk035c5444t_panel_regs),
 };
 
+static const struct nv3052c_panel_info fs035vg158_panel_info = {
+	.display_modes = fs035vg158_modes,
+	.num_modes = ARRAY_SIZE(fs035vg158_modes),
+	.width_mm = 70,
+	.height_mm = 53,
+	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+	.panel_regs = fs035vg158_panel_regs,
+	.panel_regs_len = ARRAY_SIZE(fs035vg158_panel_regs),
+};
+
 static const struct spi_device_id nv3052c_ids[] = {
 	{ "ltk035c5444t", },
+	{ "fs035vg158", },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(spi, nv3052c_ids);
 
 static const struct of_device_id nv3052c_of_match[] = {
 	{ .compatible = "leadtek,ltk035c5444t", .data = &ltk035c5444t_panel_info },
+	{ .compatible = "fascontek,fs035vg158", .data = &fs035vg158_panel_info },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, nv3052c_of_match);
-- 
2.42.0

[RFC PATCH v3 5/7] dt-bindings: display: panel: Clean up leadtek,ltk035c5444t properties

[John Watts]

Remove common properties listed in common yaml files.
Add required properties needed to describe the panel.

Signed-off-by: John Watts <contact@jookia.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/display/panel/leadtek,ltk035c5444t.yaml      | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/panel/leadtek,ltk035c5444t.yaml b/Documentation/devicetree/bindings/display/panel/leadtek,ltk035c5444t.yaml
index ebdca5f5a001..7a55961e1a3d 100644
--- a/Documentation/devicetree/bindings/display/panel/leadtek,ltk035c5444t.yaml
+++ b/Documentation/devicetree/bindings/display/panel/leadtek,ltk035c5444t.yaml
@@ -18,16 +18,12 @@ properties:
   compatible:
     const: leadtek,ltk035c5444t
 
-  backlight: true
-  port: true
-  power-supply: true
-  reg: true
-  reset-gpios: true
-
   spi-3wire: true
 
 required:
   - compatible
+  - reg
+  - port
   - power-supply
   - reset-gpios
 
-- 
2.42.0

[RFC PATCH v3 6/7] dt-bindings: vendor-prefixes: Add fascontek

[John Watts]

Fascontek manufactures LCD panels such as the FS035VG158.

Signed-off-by: John Watts <contact@jookia.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 565b13fb429d..744317e2a7cb 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -468,6 +468,8 @@ patternProperties:
     description: Fairphone B.V.
   "^faraday,.*":
     description: Faraday Technology Corporation
+  "^fascontek,.*":
+    description: Fascontek
   "^fastrax,.*":
     description: Fastrax Oy
   "^fcs,.*":
-- 
2.42.0

[RFC PATCH v3 7/7] dt-bindings: display: panel: add Fascontek FS035VG158 panel

[John Watts]

This is a small 3.5" 640x480 IPS LCD panel.

Signed-off-by: John Watts <contact@jookia.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../display/panel/fascontek,fs035vg158.yaml   | 56 +++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/panel/fascontek,fs035vg158.yaml

diff --git a/Documentation/devicetree/bindings/display/panel/fascontek,fs035vg158.yaml b/Documentation/devicetree/bindings/display/panel/fascontek,fs035vg158.yaml
new file mode 100644
index 000000000000..d13c4bd26de4
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/fascontek,fs035vg158.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/fascontek,fs035vg158.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Fascontek FS035VG158 3.5" (640x480 pixels) 24-bit IPS LCD panel
+
+maintainers:
+  - John Watts <contact@jookia.org>
+
+allOf:
+  - $ref: panel-common.yaml#
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+  compatible:
+    const: fascontek,fs035vg158
+
+  spi-3wire: true
+
+required:
+  - compatible
+  - reg
+  - port
+  - power-supply
+  - reset-gpios
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        panel@0 {
+            compatible = "fascontek,fs035vg158";
+            reg = <0>;
+
+            spi-3wire;
+            spi-max-frequency = <3125000>;
+
+            reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>;
+
+            backlight = <&backlight>;
+            power-supply = <&vcc>;
+
+            port {
+                panel_input: endpoint {
+                    remote-endpoint = <&panel_output>;
+                };
+            };
+        };
+    };
-- 
2.42.0

Re: [RFC PATCH v3 3/7] drm/panel: nv3052c: Allow specifying registers per panel

[Paul Cercueil]

Hi John,

Le lundi 25 septembre 2023 à 12:10 +1000, John Watts a écrit :
> Panel initialization registers are per-display and not tied to the
> controller itself. Different panels will specify their own registers.
> Attach the sequences to the panel info struct so future panels
> can specify their own sequences.
> 
> Signed-off-by: John Watts <contact@jookia.org>
> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
> ---
>  .../gpu/drm/panel/panel-newvision-nv3052c.c   | 24 ++++++++++++-----
> --
>  1 file changed, 15 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> index 90dea21f9856..382062a79ba8 100644
> --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> @@ -20,11 +20,18 @@
>  #include <drm/drm_modes.h>
>  #include <drm/drm_panel.h>
>  
> +struct nv3052c_reg {
> +       u8 cmd;
> +       u8 val;
> +};
> +
>  struct nv3052c_panel_info {
>         const struct drm_display_mode *display_modes;
>         unsigned int num_modes;
>         u16 width_mm, height_mm;
>         u32 bus_format, bus_flags;
> +       const struct nv3052c_reg *panel_regs;
> +       int panel_regs_len;

This can be unsigned.

>  };
>  
>  struct nv3052c {
> @@ -36,12 +43,7 @@ struct nv3052c {
>         struct gpio_desc *reset_gpio;
>  };
>  
> -struct nv3052c_reg {
> -       u8 cmd;
> -       u8 val;
> -};
> -
> -static const struct nv3052c_reg nv3052c_panel_regs[] = {
> +static const struct nv3052c_reg ltk035c5444t_panel_regs[] = {
>         // EXTC Command set enable, select page 1
>         { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 },
>         // Mostly unknown registers
> @@ -244,6 +246,8 @@ static inline struct nv3052c *to_nv3052c(struct
> drm_panel *panel)
>  static int nv3052c_prepare(struct drm_panel *panel)
>  {
>         struct nv3052c *priv = to_nv3052c(panel);
> +       const struct nv3052c_reg *panel_regs = priv->panel_info-
> >panel_regs;
> +       int panel_regs_len = priv->panel_info->panel_regs_len;

Same here.

With this fixed I'm happy with the patch.

Cheers,
-Paul

>         struct mipi_dbi *dbi = &priv->dbi;
>         unsigned int i;
>         int err;
> @@ -260,9 +264,9 @@ static int nv3052c_prepare(struct drm_panel
> *panel)
>         gpiod_set_value_cansleep(priv->reset_gpio, 0);
>         usleep_range(5000, 20000);
>  
> -       for (i = 0; i < ARRAY_SIZE(nv3052c_panel_regs); i++) {
> -               err = mipi_dbi_command(dbi,
> nv3052c_panel_regs[i].cmd,
> -                                      nv3052c_panel_regs[i].val);
> +       for (i = 0; i < panel_regs_len; i++) {
> +               err = mipi_dbi_command(dbi, panel_regs[i].cmd,
> +                                      panel_regs[i].val);
>  
>                 if (err) {
>                         dev_err(priv->dev, "Unable to set register:
> %d\n", err);
> @@ -463,6 +467,8 @@ static const struct nv3052c_panel_info
> ltk035c5444t_panel_info = {
>         .height_mm = 64,
>         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
>         .bus_flags = DRM_BUS_FLAG_DE_HIGH |
> DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
> +       .panel_regs = ltk035c5444t_panel_regs,
> +       .panel_regs_len = ARRAY_SIZE(ltk035c5444t_panel_regs),
>  };
>  
>  static const struct spi_device_id nv3052c_ids[] = {

Re: [RFC PATCH v3 4/7] drm/panel: nv3052c: Add Fascontek FS035VG158 LCD display

[Paul Cercueil]

Hi John,

Le lundi 25 septembre 2023 à 12:10 +1000, John Watts a écrit :
> This display is extremely similar to the LTK035C5444T, but still has
> some minor variations in panel initialization.
> 
> Signed-off-by: John Watts <contact@jookia.org>
> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
> ---
>  .../gpu/drm/panel/panel-newvision-nv3052c.c   | 223
> ++++++++++++++++++
>  1 file changed, 223 insertions(+)
> 
> diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> index 382062a79ba8..79f1f67df13c 100644
> --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> @@ -238,6 +238,201 @@ static const struct nv3052c_reg
> ltk035c5444t_panel_regs[] = {
>         { 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
>  };
>  
> +static const struct nv3052c_reg fs035vg158_panel_regs[] = {
> +       // EXTC Command set enable, select page 1
> +       { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 },
> +       // Mostly unknown registers
> +       { 0xe3, 0x00 },
> +       { 0x40, 0x00 },
> +       { 0x03, 0x40 },
> +       { 0x04, 0x00 },
> +       { 0x05, 0x03 },
> +       { 0x08, 0x00 },
> +       { 0x09, 0x07 },
> +       { 0x0a, 0x01 },
> +       { 0x0b, 0x32 },
> +       { 0x0c, 0x32 },
> +       { 0x0d, 0x0b },
> +       { 0x0e, 0x00 },
> +       { 0x23, 0x20 }, // RGB interface control: DE MODE PCLK-N
> +       { 0x24, 0x0c },
> +       { 0x25, 0x06 },
> +       { 0x26, 0x14 },
> +       { 0x27, 0x14 },
> +       { 0x38, 0x9c }, //VCOM_ADJ1, different to ltk035c5444t
> +       { 0x39, 0xa7 }, //VCOM_ADJ2, different to ltk035c5444t
> +       { 0x3a, 0x50 }, //VCOM_ADJ3, different to ltk035c5444t

Just to be sure, your fascontek panel won't work with the
initialization sequence of the leadtek panel?

> +       { 0x28, 0x40 },
> +       { 0x29, 0x01 },
> +       { 0x2a, 0xdf },
> +       { 0x49, 0x3c },
> +       { 0x91, 0x57 }, //EXTPW_CTRL2, different to ltk035c5444t
> +       { 0x92, 0x57 }, //EXTPW_CTRL3, different to ltk035c5444t
> +       { 0xa0, 0x55 },
> +       { 0xa1, 0x50 },
> +       { 0xa4, 0x9c },
> +       { 0xa7, 0x02 },
> +       { 0xa8, 0x01 },
> +       { 0xa9, 0x01 },
> +       { 0xaa, 0xfc },
> +       { 0xab, 0x28 },
> +       { 0xac, 0x06 },
> +       { 0xad, 0x06 },
> +       { 0xae, 0x06 },
> +       { 0xaf, 0x03 },
> +       { 0xb0, 0x08 },
> +       { 0xb1, 0x26 },
> +       { 0xb2, 0x28 },
> +       { 0xb3, 0x28 },
> +       { 0xb4, 0x03 }, // Unknown, different to ltk035c5444
> +       { 0xb5, 0x08 },
> +       { 0xb6, 0x26 },
> +       { 0xb7, 0x08 },
> +       { 0xb8, 0x26 },
> +       { 0xf0, 0x00 },
> +       { 0xf6, 0xc0 },
> +       // EXTC Command set enable, select page 0
> +       { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
> +       // Set gray scale voltage to adjust gamma
> +       { 0xb0, 0x0b }, // PGAMVR0
> +       { 0xb1, 0x16 }, // PGAMVR1
> +       { 0xb2, 0x17 }, // PGAMVR2
> +       { 0xb3, 0x2c }, // PGAMVR3
> +       { 0xb4, 0x32 }, // PGAMVR4
> +       { 0xb5, 0x3b }, // PGAMVR5
> +       { 0xb6, 0x29 }, // PGAMPR0
> +       { 0xb7, 0x40 }, // PGAMPR1
> +       { 0xb8, 0x0d }, // PGAMPK0
> +       { 0xb9, 0x05 }, // PGAMPK1
> +       { 0xba, 0x12 }, // PGAMPK2
> +       { 0xbb, 0x10 }, // PGAMPK3
> +       { 0xbc, 0x12 }, // PGAMPK4
> +       { 0xbd, 0x15 }, // PGAMPK5
> +       { 0xbe, 0x19 }, // PGAMPK6
> +       { 0xbf, 0x0e }, // PGAMPK7
> +       { 0xc0, 0x16 }, // PGAMPK8
> +       { 0xc1, 0x0a }, // PGAMPK9
> +       // Set gray scale voltage to adjust gamma
> +       { 0xd0, 0x0c }, // NGAMVR0
> +       { 0xd1, 0x17 }, // NGAMVR0
> +       { 0xd2, 0x14 }, // NGAMVR1
> +       { 0xd3, 0x2e }, // NGAMVR2
> +       { 0xd4, 0x32 }, // NGAMVR3
> +       { 0xd5, 0x3c }, // NGAMVR4
> +       { 0xd6, 0x22 }, // NGAMPR0
> +       { 0xd7, 0x3d }, // NGAMPR1
> +       { 0xd8, 0x0d }, // NGAMPK0
> +       { 0xd9, 0x07 }, // NGAMPK1
> +       { 0xda, 0x13 }, // NGAMPK2
> +       { 0xdb, 0x13 }, // NGAMPK3
> +       { 0xdc, 0x11 }, // NGAMPK4
> +       { 0xdd, 0x15 }, // NGAMPK5
> +       { 0xde, 0x19 }, // NGAMPK6
> +       { 0xdf, 0x10 }, // NGAMPK7
> +       { 0xe0, 0x17 }, // NGAMPK8
> +       { 0xe1, 0x0a }, // NGAMPK9
> +       // EXTC Command set enable, select page 3
> +       { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 },
> +       // Set various timing settings
> +       { 0x00, 0x2a }, // GIP_VST_1
> +       { 0x01, 0x2a }, // GIP_VST_2
> +       { 0x02, 0x2a }, // GIP_VST_3
> +       { 0x03, 0x2a }, // GIP_VST_4
> +       { 0x04, 0x61 }, // GIP_VST_5
> +       { 0x05, 0x80 }, // GIP_VST_6
> +       { 0x06, 0xc7 }, // GIP_VST_7
> +       { 0x07, 0x01 }, // GIP_VST_8
> +       { 0x08, 0x03 }, // GIP_VST_9
> +       { 0x09, 0x04 }, // GIP_VST_10
> +       { 0x70, 0x22 }, // GIP_ECLK1
> +       { 0x71, 0x80 }, // GIP_ECLK2
> +       { 0x30, 0x2a }, // GIP_CLK_1
> +       { 0x31, 0x2a }, // GIP_CLK_2
> +       { 0x32, 0x2a }, // GIP_CLK_3
> +       { 0x33, 0x2a }, // GIP_CLK_4
> +       { 0x34, 0x61 }, // GIP_CLK_5
> +       { 0x35, 0xc5 }, // GIP_CLK_6
> +       { 0x36, 0x80 }, // GIP_CLK_7
> +       { 0x37, 0x23 }, // GIP_CLK_8
> +       { 0x40, 0x03 }, // GIP_CLKA_1
> +       { 0x41, 0x04 }, // GIP_CLKA_2
> +       { 0x42, 0x05 }, // GIP_CLKA_3
> +       { 0x43, 0x06 }, // GIP_CLKA_4
> +       { 0x44, 0x11 }, // GIP_CLKA_5
> +       { 0x45, 0xe8 }, // GIP_CLKA_6
> +       { 0x46, 0xe9 }, // GIP_CLKA_7
> +       { 0x47, 0x11 }, // GIP_CLKA_8
> +       { 0x48, 0xea }, // GIP_CLKA_9
> +       { 0x49, 0xeb }, // GIP_CLKA_10
> +       { 0x50, 0x07 }, // GIP_CLKB_1
> +       { 0x51, 0x08 }, // GIP_CLKB_2
> +       { 0x52, 0x09 }, // GIP_CLKB_3
> +       { 0x53, 0x0a }, // GIP_CLKB_4
> +       { 0x54, 0x11 }, // GIP_CLKB_5
> +       { 0x55, 0xec }, // GIP_CLKB_6
> +       { 0x56, 0xed }, // GIP_CLKB_7
> +       { 0x57, 0x11 }, // GIP_CLKB_8
> +       { 0x58, 0xef }, // GIP_CLKB_9
> +       { 0x59, 0xf0 }, // GIP_CLKB_10
> +       // Map internal GOA signals to GOA output pad
> +       { 0xb1, 0x01 }, // PANELD2U2
> +       { 0xb4, 0x15 }, // PANELD2U5
> +       { 0xb5, 0x16 }, // PANELD2U6
> +       { 0xb6, 0x09 }, // PANELD2U7
> +       { 0xb7, 0x0f }, // PANELD2U8
> +       { 0xb8, 0x0d }, // PANELD2U9
> +       { 0xb9, 0x0b }, // PANELD2U10
> +       { 0xba, 0x00 }, // PANELD2U11
> +       { 0xc7, 0x02 }, // PANELD2U24
> +       { 0xca, 0x17 }, // PANELD2U27
> +       { 0xcb, 0x18 }, // PANELD2U28
> +       { 0xcc, 0x0a }, // PANELD2U29
> +       { 0xcd, 0x10 }, // PANELD2U30
> +       { 0xce, 0x0e }, // PANELD2U31
> +       { 0xcf, 0x0c }, // PANELD2U32
> +       { 0xd0, 0x00 }, // PANELD2U33
> +       // Map internal GOA signals to GOA output pad
> +       { 0x81, 0x00 }, // PANELU2D2
> +       { 0x84, 0x15 }, // PANELU2D5
> +       { 0x85, 0x16 }, // PANELU2D6
> +       { 0x86, 0x10 }, // PANELU2D7
> +       { 0x87, 0x0a }, // PANELU2D8
> +       { 0x88, 0x0c }, // PANELU2D9
> +       { 0x89, 0x0e }, // PANELU2D10
> +       { 0x8a, 0x02 }, // PANELU2D11
> +       { 0x97, 0x00 }, // PANELU2D24
> +       { 0x9a, 0x17 }, // PANELU2D27
> +       { 0x9b, 0x18 }, // PANELU2D28
> +       { 0x9c, 0x0f }, // PANELU2D29
> +       { 0x9d, 0x09 }, // PANELU2D30
> +       { 0x9e, 0x0b }, // PANELU2D31
> +       { 0x9f, 0x0d }, // PANELU2D32
> +       { 0xa0, 0x01 }, // PANELU2D33
> +       // EXTC Command set enable, select page 2
> +       { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
> +       // Unknown registers
> +       { 0x01, 0x01 },
> +       { 0x02, 0xda },
> +       { 0x03, 0xba },
> +       { 0x04, 0xa8 },
> +       { 0x05, 0x9a },
> +       { 0x06, 0x70 },
> +       { 0x07, 0xff },
> +       { 0x08, 0x91 },
> +       { 0x09, 0x90 },
> +       { 0x0a, 0xff },
> +       { 0x0b, 0x8f },
> +       { 0x0c, 0x60 },
> +       { 0x0d, 0x58 },
> +       { 0x0e, 0x48 },
> +       { 0x0f, 0x38 },
> +       { 0x10, 0x2b },
> +       // EXTC Command set enable, select page 0
> +       { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 },
> +       // Display Access Control
> +       { 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
> +};
> +
>  static inline struct nv3052c *to_nv3052c(struct drm_panel *panel)
>  {
>         return container_of(panel, struct nv3052c, panel);
> @@ -460,6 +655,21 @@ static const struct drm_display_mode
> ltk035c5444t_modes[] = {
>         },
>  };
>  
> +static const struct drm_display_mode fs035vg158_modes[] = {
> +       { /* 60 Hz */
> +               .clock = 21000,
> +               .hdisplay = 640,
> +               .hsync_start = 640 + 34,
> +               .hsync_end = 640 + 34 + 4,
> +               .htotal = 640 + 34 + 4 + 20,
> +               .vdisplay = 480,
> +               .vsync_start = 480 + 12,
> +               .vsync_end = 480 + 12 + 4,
> +               .vtotal = 480 + 12 + 4 + 6,
> +               .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
> +       },
> +};

Did you try with the existing display modes? If you can afford the 24
MHz clock (and if it works with your panel) it will give you a perfect
60.0 Hz refresh rate, while this mode above will give you above 59.93
Hz (which is not that bad though).

Otherwise LGTM.

Cheers,
-Paul

> +
>  static const struct nv3052c_panel_info ltk035c5444t_panel_info = {
>         .display_modes = ltk035c5444t_modes,
>         .num_modes = ARRAY_SIZE(ltk035c5444t_modes),
> @@ -471,14 +681,27 @@ static const struct nv3052c_panel_info
> ltk035c5444t_panel_info = {
>         .panel_regs_len = ARRAY_SIZE(ltk035c5444t_panel_regs),
>  };
>  
> +static const struct nv3052c_panel_info fs035vg158_panel_info = {
> +       .display_modes = fs035vg158_modes,
> +       .num_modes = ARRAY_SIZE(fs035vg158_modes),
> +       .width_mm = 70,
> +       .height_mm = 53,
> +       .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
> +       .bus_flags = DRM_BUS_FLAG_DE_HIGH |
> DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
> +       .panel_regs = fs035vg158_panel_regs,
> +       .panel_regs_len = ARRAY_SIZE(fs035vg158_panel_regs),
> +};
> +
>  static const struct spi_device_id nv3052c_ids[] = {
>         { "ltk035c5444t", },
> +       { "fs035vg158", },
>         { /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(spi, nv3052c_ids);
>  
>  static const struct of_device_id nv3052c_of_match[] = {
>         { .compatible = "leadtek,ltk035c5444t", .data =
> &ltk035c5444t_panel_info },
> +       { .compatible = "fascontek,fs035vg158", .data =
> &fs035vg158_panel_info },
>         { /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, nv3052c_of_match);

Re: [RFC PATCH v3 4/7] drm/panel: nv3052c: Add Fascontek FS035VG158 LCD display

[John Watts]

On Mon, Sep 25, 2023 at 11:12:29AM +0200, Paul Cercueil wrote:
> Hi John,
> 
> Just to be sure, your fascontek panel won't work with the
> initialization sequence of the leadtek panel?

Yes, it does work.

> Did you try with the existing display modes? If you can afford the 24
> MHz clock (and if it works with your panel) it will give you a perfect
> 60.0 Hz refresh rate, while this mode above will give you above 59.93
> Hz (which is not that bad though).

No I didn't test with this.

In general I don't feel comfortable submitting code that strays from what is
recommended by the manufacturer.

> Otherwise LGTM.
> 
> Cheers,
> -Paul

John.

Re: [RFC PATCH v3 4/7] drm/panel: nv3052c: Add Fascontek FS035VG158 LCD display

[Paul Cercueil]

Le lundi 25 septembre 2023 à 19:21 +1000, John Watts a écrit :
> On Mon, Sep 25, 2023 at 11:12:29AM +0200, Paul Cercueil wrote:
> > Hi John,
> > 
> > Just to be sure, your fascontek panel won't work with the
> > initialization sequence of the leadtek panel?
> 
> Yes, it does work.

OK, why not use the leadtek's initialization sequence then?

From what I can see, you have a panel with a NV3052C chip, so the
existing initialization sequence should already work.

> 
> > Did you try with the existing display modes? If you can afford the
> > 24
> > MHz clock (and if it works with your panel) it will give you a
> > perfect
> > 60.0 Hz refresh rate, while this mode above will give you above
> > 59.93
> > Hz (which is not that bad though).
> 
> No I didn't test with this.
> 
> In general I don't feel comfortable submitting code that strays from
> what is
> recommended by the manufacturer.

The NV3052C datasheet does not give any settings for a 640x480 panel, I
only see suggested settings for a 720x1280 vertical panel.

Unless you have a min/max range specified, the values you see in there
are only suggestions for a working setup, that doesn't mean they are
the only recommended ones.

Cheers,
-Paul

Re: [RFC PATCH v3 4/7] drm/panel: nv3052c: Add Fascontek FS035VG158 LCD display

[John Watts]

On Mon, Sep 25, 2023 at 11:43:26AM +0200, Paul Cercueil wrote:
> From what I can see, you have a panel with a NV3052C chip, so the
> existing initialization sequence should already work.

It has some differences that I don't know if are important.

> The NV3052C datasheet does not give any settings for a 640x480 panel, I
> only see suggested settings for a 720x1280 vertical panel.
> 
> Unless you have a min/max range specified, the values you see in there
> are only suggestions for a working setup, that doesn't mean they are
> the only recommended ones.

The panel datasheet has these values.

> 
> Cheers,
> -Paul

John.

Re: [RFC PATCH v3 4/7] drm/panel: nv3052c: Add Fascontek FS035VG158 LCD display

[Paul Cercueil]

Le lundi 25 septembre 2023 à 19:48 +1000, John Watts a écrit :
> On Mon, Sep 25, 2023 at 11:43:26AM +0200, Paul Cercueil wrote:
> > From what I can see, you have a panel with a NV3052C chip, so the
> > existing initialization sequence should already work.
> 
> It has some differences that I don't know if are important.

Unless you can explain what they do and why they are needed, I'd say
they are not important :)

> 
> > The NV3052C datasheet does not give any settings for a 640x480
> > panel, I
> > only see suggested settings for a 720x1280 vertical panel.
> > 
> > Unless you have a min/max range specified, the values you see in
> > there
> > are only suggestions for a working setup, that doesn't mean they
> > are
> > the only recommended ones.
> 
> The panel datasheet has these values.

Again, doesn't mean that you have to use these.

From what I can see, all you need to support your Fascontek panel with
the nv3052c driver, is to add the SPI ID and compatible strings.

Cheers,
-Paul

Re: [RFC PATCH v3 4/7] drm/panel: nv3052c: Add Fascontek FS035VG158 LCD display

[John Watts]

On Mon, Sep 25, 2023 at 12:34:55PM +0200, Paul Cercueil wrote:
> Unless you can explain what they do and why they are needed, I'd say
> they are not important :)
> 
> ...
>
> Again, doesn't mean that you have to use these.
> 
> From what I can see, all you need to support your Fascontek panel with
> the nv3052c driver, is to add the SPI ID and compatible strings.

This is not a patch I would be willing to submit. Sorry.

> 
> Cheers,
> -Paul

John.