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* [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension
@ 2023-10-19 14:02 Yu Chien Peter Lin
  2023-10-20  7:32 ` Geert Uytterhoeven
  0 siblings, 1 reply; 3+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 14:02 UTC (permalink / raw)
  To: geert+renesas, magnus.damm, robh+dt, krzysztof.kozlowski+dt,
	conor+dt, paul.walmsley, palmer, aou, linux-renesas-soc,
	devicetree, linux-riscv, linux-kernel
  Cc: prabhakar.mahadev-lad.rj, tim609, dylan, locus84, dminus,
	Yu Chien Peter Lin

Add "xandespmu" to ISA extensions, the SBI PMU driver will
probe the extension and use the non-standard irq source.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2:
  - New patch
---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index a6345469e8c9..73c572056a04 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -26,7 +26,7 @@ cpu0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xandespmu";
 			mmu-type = "riscv,sv39";
 			i-cache-size = <0x8000>;
 			i-cache-line-size = <0x40>;
-- 
2.34.1


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2023-10-19 14:02 [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension Yu Chien Peter Lin
2023-10-20  7:32 ` Geert Uytterhoeven
2023-10-20  8:20   ` Yu-Chien Peter Lin

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