* [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension
@ 2023-10-19 14:02 Yu Chien Peter Lin
2023-10-20 7:32 ` Geert Uytterhoeven
0 siblings, 1 reply; 3+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 14:02 UTC (permalink / raw)
To: geert+renesas, magnus.damm, robh+dt, krzysztof.kozlowski+dt,
conor+dt, paul.walmsley, palmer, aou, linux-renesas-soc,
devicetree, linux-riscv, linux-kernel
Cc: prabhakar.mahadev-lad.rj, tim609, dylan, locus84, dminus,
Yu Chien Peter Lin
Add "xandespmu" to ISA extensions, the SBI PMU driver will
probe the extension and use the non-standard irq source.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2:
- New patch
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index a6345469e8c9..73c572056a04 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -26,7 +26,7 @@ cpu0: cpu@0 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm";
+ "zifencei", "zihpm", "xandespmu";
mmu-type = "riscv,sv39";
i-cache-size = <0x8000>;
i-cache-line-size = <0x40>;
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension
2023-10-19 14:02 [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension Yu Chien Peter Lin
@ 2023-10-20 7:32 ` Geert Uytterhoeven
2023-10-20 8:20 ` Yu-Chien Peter Lin
0 siblings, 1 reply; 3+ messages in thread
From: Geert Uytterhoeven @ 2023-10-20 7:32 UTC (permalink / raw)
To: Yu Chien Peter Lin
Cc: magnus.damm, robh+dt, krzysztof.kozlowski+dt, conor+dt,
paul.walmsley, palmer, aou, linux-renesas-soc, devicetree,
linux-riscv, linux-kernel, prabhakar.mahadev-lad.rj, tim609,
dylan, locus84, dminus
Hi Peter,
On Thu, Oct 19, 2023 at 4:05 PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
> Add "xandespmu" to ISA extensions, the SBI PMU driver will
> probe the extension and use the non-standard irq source.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v1 -> v2:
> - New patch
Thanks for your patch!
> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -26,7 +26,7 @@ cpu0: cpu@0 {
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm";
> + "zifencei", "zihpm", "xandespmu";
> mmu-type = "riscv,sv39";
> i-cache-size = <0x8000>;
> i-cache-line-size = <0x40>;
This extension is not documented in
Documentation/devicetree/bindings/riscv/extensions.yaml. Perhaps it was
introduced in an earlier patch in the series, to which I was not CCed?
Threading is broken, so I can't easily find the whole series in lore:
https://lore.kernel.org/all/20231019140232.3660375-1-peterlin@andestech.com/
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension
2023-10-20 7:32 ` Geert Uytterhoeven
@ 2023-10-20 8:20 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 3+ messages in thread
From: Yu-Chien Peter Lin @ 2023-10-20 8:20 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: magnus.damm, robh+dt, krzysztof.kozlowski+dt, conor+dt,
paul.walmsley, palmer, aou, linux-renesas-soc, devicetree,
linux-riscv, linux-kernel, prabhakar.mahadev-lad.rj, tim609,
dylan, locus84, dminus
Hi Geert,
On Fri, Oct 20, 2023 at 09:32:45AM +0200, Geert Uytterhoeven wrote:
> Hi Peter,
>
> On Thu, Oct 19, 2023 at 4:05 PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> > Add "xandespmu" to ISA extensions, the SBI PMU driver will
> > probe the extension and use the non-standard irq source.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > ---
> > Changes v1 -> v2:
> > - New patch
>
> Thanks for your patch!
>
> > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > @@ -26,7 +26,7 @@ cpu0: cpu@0 {
> > riscv,isa = "rv64imafdc";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > - "zifencei", "zihpm";
> > + "zifencei", "zihpm", "xandespmu";
> > mmu-type = "riscv,sv39";
> > i-cache-size = <0x8000>;
> > i-cache-line-size = <0x40>;
>
> This extension is not documented in
> Documentation/devicetree/bindings/riscv/extensions.yaml. Perhaps it was
> introduced in an earlier patch in the series, to which I was not CCed?
Yes, I missed adding the extension to dt bindings.
Thanks for the pointer.
Best regards,
Peter Lin
>
> Threading is broken, so I can't easily find the whole series in lore:
> https://lore.kernel.org/all/20231019140232.3660375-1-peterlin@andestech.com/
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-10-19 14:02 [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension Yu Chien Peter Lin
2023-10-20 7:32 ` Geert Uytterhoeven
2023-10-20 8:20 ` Yu-Chien Peter Lin
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