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Mon, 23 Oct 2023 22:31:54 -0700 (PDT) Received: from sunil-laptop ([2409:4071:6e9d:1e7:259:d68d:db3b:3cc]) by smtp.gmail.com with ESMTPSA id y15-20020aa79aef000000b0068883728c16sm7216982pfp.144.2023.10.23.22.31.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 22:31:53 -0700 (PDT) Date: Tue, 24 Oct 2023 11:01:37 +0530 From: Sunil V L To: Anup Patel Cc: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley , Marc Zyngier , =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= , Atish Patra , Andrew Jones , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v11 12/14] irqchip/riscv-aplic: Add support for MSI-mode Message-ID: References: <20231023172800.315343-1-apatel@ventanamicro.com> <20231023172800.315343-13-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231023172800.315343-13-apatel@ventanamicro.com> Hi Anup, On Mon, Oct 23, 2023 at 10:57:58PM +0530, Anup Patel wrote: > The RISC-V advanced platform-level interrupt controller (APLIC) has > two modes of operation: 1) Direct mode and 2) MSI mode. > (For more details, refer https://github.com/riscv/riscv-aia) > > In APLIC MSI-mode, wired interrupts are forwared as message signaled > interrupts (MSIs) to CPUs via IMSIC. > > We extend the existing APLIC irqchip driver to support MSI-mode for > RISC-V platforms having both wired interrupts and MSIs. > > Signed-off-by: Anup Patel > --- [...] > +int aplic_msi_setup(struct device *dev, void __iomem *regs) > +{ > + const struct imsic_global_config *imsic_global; > + struct irq_domain *irqdomain; > + struct aplic_priv *priv; > + struct aplic_msicfg *mc; > + phys_addr_t pa; > + int rc; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + rc = aplic_setup_priv(priv, dev, regs); > + if (!priv) { This should check rc instead of priv. > + dev_err(dev, "failed to create APLIC context\n"); > + return rc; > + } > + mc = &priv->msicfg; > + > + /* > + * The APLIC outgoing MSI config registers assume target MSI > + * controller to be RISC-V AIA IMSIC controller. > + */ > + imsic_global = imsic_get_global_config(); > + if (!imsic_global) { > + dev_err(dev, "IMSIC global config not found\n"); > + return -ENODEV; For all error return paths, priv should be freed. Thanks, Sunil