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charset="iso-8859-2" Content-ID: <51A81C7F5C88364188E891478E0531DD@namprd04.prod.outlook.com> Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: =?iso-8859-2?Q?gt3HuiZJCoYHbVselh94JeIYCVn5UXZQMJDRROzNkF0vISvlGpjQ41e+sk?= =?iso-8859-2?Q?Dkc+lt92n0FE8nyyUqok1fIj7RffmZKvWjIMGvwU6h74vBMRrus/AdfXMo?= =?iso-8859-2?Q?GqOXZUDB2Q9nRUkPuVkHrIFPJLHt1siFjJwMgBTHcnqEY1oSAUkR8YwGRK?= =?iso-8859-2?Q?RbxLjRsRPvtfdaKyVAcL/K5VzddPxd0hutm23af8oWldbw5P+umTrxDxRM?= =?iso-8859-2?Q?1HzS9gBHYf2SBrV5Rjs1nPsKM/xaZWrsQvfmQG3J0Bshfh6oEL3gVPNTdp?= =?iso-8859-2?Q?4uoqF+FS0PWJL4LRQXV6LBSE2BV6GId7buCsoFsRFbB9moXrrtu5fwu0Wh?= =?iso-8859-2?Q?8Nxofmjmrq1OgfTalmwhNVMgZDTij6joFIf3keTq327Nl6G2GTivI4RS+u?= =?iso-8859-2?Q?6TerRlv8v7hI/pkHC0VialU81/DBXDghiJGWIIfC9s7FKR164Fxe8FZg34?= =?iso-8859-2?Q?msBh3gEOQiZEoFJZc6pGliLwzgtdn6vJ4nSuWCcehO+A5R/KGywo4iWdqq?= =?iso-8859-2?Q?sXKLscjK/Dk0M7nRf6gcg2Ou3LioM71ZcNCGgEx/5i5awwGXKB/8MbU3eI?= =?iso-8859-2?Q?sQp1fNBqFl3hieGyP9/ipE3jHM2WFdwuxv9REcTI87B1jon+LhoPRcAeOL?= =?iso-8859-2?Q?iMTPY8DD4GAOtfnI17ChVbHQt8irGjwDFBLS5bw3cl0aWmZ0A8qIsvFSCV?= =?iso-8859-2?Q?Tk0lvfd2WEQ6gc2/ShaSrAANrA0no+sSKxsZzWXcAKMLqqNkENEmA+hbZQ?= =?iso-8859-2?Q?mxftC/S4u/Z3WVRB1eRFa8hiRmBD+AamSUVsNMjhvFwvZrsiPgjWLv6Ip+?= =?iso-8859-2?Q?Nwgf/QLIkUcgZprYCNkv/dGXCbLUeqPbfwkn6BW9SGMWsaBrOTjvMOGmGp?= =?iso-8859-2?Q?o0M+L4ZDpSKptIMviPFx56o+dXtwRAaXJubV8PmjJ0oGuerxVFtqEe2LAp?= =?iso-8859-2?Q?6pPBf9M7dM/IzLw4HF4ur/AvO8hDQefF5m4fl7YQcDTTST+iAFdY5ulnCv?= =?iso-8859-2?Q?fsUScIggYTanQ9zIu+Jx6qQjB1cLrCBkOvQ5Ln/Q/P3ttalJAGKhRIFPjR?= =?iso-8859-2?Q?X8grzFRg7qTbZOxivKHitTbw+hwILhhxfHOabQ7PJD6S8bLYWyCkfvO5Xk?= =?iso-8859-2?Q?nNdU94LqNhebg5ibrIr6xeK8lvkEc=3D?= X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR04MB6272.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 67dba90a-d126-448c-fb4a-08dbd6fc2652 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Oct 2023 14:51:06.5998 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XI+EyYqN7DOpjtG/RaOUOuukhYpI/jAnir2t+iOLl9VDMAaNhaO0/b8WzrMANlMTGfwP+cODtZqZj9kyOdyjmg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR04MB6597 On Thu, Oct 26, 2023 at 05:32:44PM +0300, Serge Semin wrote: > On Tue, Oct 24, 2023 at 05:10:10PM +0200, Niklas Cassel wrote: > > From: Niklas Cassel > >=20 > > Even though rockchip-dw-pcie.yaml inherits snps,dw-pcie.yaml > > using: > >=20 > > allOf: > > - $ref: /schemas/pci/snps,dw-pcie.yaml# > >=20 > > and snps,dw-pcie.yaml does have the dma properties defined, in order to= be > > able to use these properties, while still making sure 'make CHECK_DTBS= =3Dy' > > pass, we need to add these properties to rockchip-dw-pcie.yaml. > >=20 > > Signed-off-by: Niklas Cassel > > --- > > .../bindings/pci/rockchip-dw-pcie.yaml | 20 +++++++++++++++++++ > > 1 file changed, 20 insertions(+) > >=20 > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yam= l b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > index 229f8608c535..633f8e0e884f 100644 > > --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml > > @@ -35,6 +35,7 @@ properties: > > - description: Rockchip designed configuration registers > > - description: Config registers > > - description: iATU registers > > + - description: eDMA registers > > =20 > > reg-names: > > minItems: 3 > > @@ -43,6 +44,7 @@ properties: > > - const: apb > > - const: config > > - const: atu > > + - const: dma > > =20 > > clocks: > > minItems: 5 > > @@ -65,6 +67,7 @@ properties: > > - const: pipe > > =20 > > interrupts: > > + minItems: 5 > > items: > > - description: > > Combined system interrupt, which is used to signal the follo= wing > > @@ -88,14 +91,31 @@ properties: > > interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, > > tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_e= rr_rx, > > nf_err_rx, f_err_rx, radm_qoverflow >=20 > > + - description: > > + Indicates that the eDMA Tx/Rx transfer is complete or that a= n > > + error has occurred on the corresponding channel. > > + - description: > > + Indicates that the eDMA Tx/Rx transfer is complete or that a= n > > + error has occurred on the corresponding channel. > > + - description: > > + Indicates that the eDMA Tx/Rx transfer is complete or that a= n > > + error has occurred on the corresponding channel. > > + - description: > > + Indicates that the eDMA Tx/Rx transfer is complete or that a= n > > + error has occurred on the corresponding channel. >=20 > They aren't identical. Some IRQs indicate events on the write eDMA > channels, some - read eDMA channels. The respective channel ID would > be also useful to have in the description. Hello Serge, As you know, the IRQs for the write channels have to be specified before the IRQs for the read channels in "interrupts". So for rk3588, it will be: dma0: wr0 dma1: wr1 dma2: rd0 dma3: rd1 However, e.g. rk3568 only has one channel for reads and one for writes. (Now this SoC doesn't have dedicated IRQs for the eDMA, but let's pretend that it did.) So for rk3568, it would then instead be: dma0: wr0 dma1: rd0 dma2: dma3: So I would rather not add read/write or channel number to the descriptions, as both the channel number and read/write will depend on how the eDMA in th= e specific controller was synthesized. So I'd rather have no description rath= er than a description that will be wrong for all rockchip SoCs other than rk35= 88. Kind regards, Niklas=