From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 666B6DDB2; Fri, 10 Nov 2023 10:44:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qSLHNlzm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C6182C433C7; Fri, 10 Nov 2023 10:44:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699613054; bh=yViYqOJVdcBEk5fwPiwK27bzW7FkRKcbTn6zst1rjt8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=qSLHNlzm4RnBkdR24TluN7Dng6mOBC3pzmQzkUClpylay3CL16NwjJ4Alj7CX5f9F f80FulVCDie4nGya1NifjrM6e1++EFxYSeROku/SICA4BjLLyLTmIF1HM8/9JdEsTP 0+V2tqprbkPF+dNDMKlgOHfiq1Swk4V5j7J6eYKrF1aipAA6F33s5wP34O7pnwzeQt Jox5DBmzqhJzsaslk6mATLVU6HIlMivBY5xCcCWj4GG7xmQ0SraDM8cRLywLjECZ9/ I8TdDIOkFhDlXm/5suafwLqc6rwkcUS5i5c01ugOYrykmTRFJvO5Ji7Ul7EcMOpP59 itVv9KhxpAHrg== Received: from johan by theta with local (Exim 4.96.2) (envelope-from ) id 1r1Ozh-0004rg-14; Fri, 10 Nov 2023 11:44:09 +0100 Date: Fri, 10 Nov 2023 11:44:09 +0100 From: Johan Hovold To: Krishna Kurapati PSSNV Cc: Thinh Nguyen , Bjorn Andersson , Greg Kroah-Hartman , Philipp Zabel , Andy Gross , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Felipe Balbi , Wesley Cheng , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, quic_pkondeti@quicinc.com, quic_ppratap@quicinc.com, quic_jackp@quicinc.com, ahalaney@redhat.com, quic_shazhuss@quicinc.com Subject: Re: [PATCH v13 05/10] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver Message-ID: References: <04615205-e380-4719-aff1-f32c26004b14@quicinc.com> <2b19b5e2-5eb0-49e0-8c47-8aff3d48f34e@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Nov 10, 2023 at 03:31:15PM +0530, Krishna Kurapati PSSNV wrote: > Controller-1: > u_usb31_prim_mvs_wrapper_usb31_hs_phy_irq SYS_apcsQgicSPI[806] > Controller-2: > u_usb31_prim_mvs_wrapper_usb31_hs_phy_irq SYS_apcsQgicSPI[791] Thanks. > > Yes, but, again, you never enabled them in the PHY (cf. QUSB2) so it's > > hardly surprising that they do not fire. > > > There is no register in femto phy address space of sc8280 (which I am > currently testing) where we can configure these registers like qusb2 phy's. Right, so they are not enabled (and possibly cannot be enabled). > > So then including the hs_phy_irq for most of these SoCs was a mistake > > and we should drop it from the bindings? > > > > What about the QUSB2 SoCs that also define DP/DM, are both useable > > there? > > > > And if so, is there any reason to prefer one mechanism over the other? > > No. I didn't ask this question to hw team whether dp/dm are used in qusb2 > phy targets. Let me ask them. > > While I do so, since there are no qusb2 targets present on femto phy's, do > you suggest we still add them to port structure in dwc3-qcom ? I am inclined > to add it because it would make implementation look cleaner w.r.t code and > also spurious interrupts are not getting triggered (which was my primary > concern as it was never tested). Yes, that's what I've been suggesting all along. It's a per-port interrupt so that's where it belongs. We should still try to determine when each interrupt should be enabled and how best to implement that (hence all my questions). For example, if there is no use for hs interrupts on SoCs using femto PHYs we should fix the bindings. If we can use dp/dm on SoCs using QUSB2 PHYs, we should probably just ignore the hs interrupt when all three are defined (especially since that functionality has never worked anyway). Johan