[PATCH v3 0/6] add qca8084 ethernet phy driver

[PATCH v3 0/6] add qca8084 ethernet phy driver

[Luo Jie]

QCA8084 is four-port PHY with maximum link capability 2.5G,
which supports the interface mode qusgmii and sgmii mode,
there are two PCSs available to connected with ethernet port.

QCA8084 can work in switch mode or PHY mode.
For switch mode, both PCS0 and PCS1 work on sgmii mode.
For PHY mode, PCS1 works on qusgmii mode, the last port
(the fourth port) works on sgmii mode.

Besides this PHY driver patches, the PCS driver is also needed
to bring up the qca8084 device, which mainly configurs PCS
and clocks.

Changes in v3:
	1. pick the two patches to introduce the interface mode
	10g-qxgmii from Vladimir Oltean(olteanv@gmail.com).

	2. add the function phydev_id_is_qca808x to identify the
	PHY qca8081 and qca8084.

	3. update the interface mode name PHY_INTERFACE_MODE_QUSGMII
	to PHY_INTERFACE_MODE_10G_QXGMII.

Luo Jie (4):
  net: phy: at803x: add QCA8084 ethernet phy support
  net: phy: at803x: add the function phydev_id_is_qca808x
  net: phy: at803x: Add qca8084_config_init function
  net: phy: qca8084: add qca8084_link_change_notify

Vladimir Oltean (2):
  net: phylink: move phylink_pcs_neg_mode() to phylink.c
  net: phy: introduce core support for phy-mode = "10g-qxgmii"

 .../bindings/net/ethernet-controller.yaml     |   1 +
 Documentation/networking/phy.rst              |   6 +
 drivers/net/phy/at803x.c                      | 130 +++++++++++++++++-
 drivers/net/phy/phy-core.c                    |   1 +
 drivers/net/phy/phylink.c                     |  77 ++++++++++-
 include/linux/phy.h                           |   4 +
 include/linux/phylink.h                       |  67 +--------
 7 files changed, 212 insertions(+), 74 deletions(-)


base-commit: bc962b35b139dd52319e6fc0f4bab00593bf38c9
-- 
2.42.0

[PATCH v3 1/6] net: phylink: move phylink_pcs_neg_mode() to phylink.c

[Luo Jie]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

Russell points out that there is no user of phylink_pcs_neg_mode()
outside of phylink.c, nor is there planned to be any, so we can just
move it there.

Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 drivers/net/phy/phylink.c | 65 ++++++++++++++++++++++++++++++++++++++
 include/linux/phylink.h   | 66 ---------------------------------------
 2 files changed, 65 insertions(+), 66 deletions(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 25c19496a336..162f51b0986a 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -162,6 +162,71 @@ static const char *phylink_an_mode_str(unsigned int mode)
 	return mode < ARRAY_SIZE(modestr) ? modestr[mode] : "unknown";
 }
 
+/**
+ * phylink_pcs_neg_mode() - helper to determine PCS inband mode
+ * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
+ * @interface: interface mode to be used
+ * @advertising: adertisement ethtool link mode mask
+ *
+ * Determines the negotiation mode to be used by the PCS, and returns
+ * one of:
+ *
+ * - %PHYLINK_PCS_NEG_NONE: interface mode does not support inband
+ * - %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY)
+ *   will be used.
+ * - %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg
+ *   disabled
+ * - %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled
+ *
+ * Note: this is for cases where the PCS itself is involved in negotiation
+ * (e.g. Clause 37, SGMII and similar) not Clause 73.
+ */
+static unsigned int phylink_pcs_neg_mode(unsigned int mode, phy_interface_t interface,
+					 const unsigned long *advertising)
+{
+	unsigned int neg_mode;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_QSGMII:
+	case PHY_INTERFACE_MODE_QUSGMII:
+	case PHY_INTERFACE_MODE_USXGMII:
+		/* These protocols are designed for use with a PHY which
+		 * communicates its negotiation result back to the MAC via
+		 * inband communication. Note: there exist PHYs that run
+		 * with SGMII but do not send the inband data.
+		 */
+		if (!phylink_autoneg_inband(mode))
+			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
+		else
+			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
+		break;
+
+	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		/* 1000base-X is designed for use media-side for Fibre
+		 * connections, and thus the Autoneg bit needs to be
+		 * taken into account. We also do this for 2500base-X
+		 * as well, but drivers may not support this, so may
+		 * need to override this.
+		 */
+		if (!phylink_autoneg_inband(mode))
+			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
+		else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+					   advertising))
+			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
+		else
+			neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;
+		break;
+
+	default:
+		neg_mode = PHYLINK_PCS_NEG_NONE;
+		break;
+	}
+
+	return neg_mode;
+}
+
 static unsigned int phylink_interface_signal_rate(phy_interface_t interface)
 {
 	switch (interface) {
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index 875439ab45de..d589f89c612c 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -98,72 +98,6 @@ static inline bool phylink_autoneg_inband(unsigned int mode)
 	return mode == MLO_AN_INBAND;
 }
 
-/**
- * phylink_pcs_neg_mode() - helper to determine PCS inband mode
- * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
- * @interface: interface mode to be used
- * @advertising: adertisement ethtool link mode mask
- *
- * Determines the negotiation mode to be used by the PCS, and returns
- * one of:
- *
- * - %PHYLINK_PCS_NEG_NONE: interface mode does not support inband
- * - %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY)
- *   will be used.
- * - %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg
- *   disabled
- * - %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled
- *
- * Note: this is for cases where the PCS itself is involved in negotiation
- * (e.g. Clause 37, SGMII and similar) not Clause 73.
- */
-static inline unsigned int phylink_pcs_neg_mode(unsigned int mode,
-						phy_interface_t interface,
-						const unsigned long *advertising)
-{
-	unsigned int neg_mode;
-
-	switch (interface) {
-	case PHY_INTERFACE_MODE_SGMII:
-	case PHY_INTERFACE_MODE_QSGMII:
-	case PHY_INTERFACE_MODE_QUSGMII:
-	case PHY_INTERFACE_MODE_USXGMII:
-		/* These protocols are designed for use with a PHY which
-		 * communicates its negotiation result back to the MAC via
-		 * inband communication. Note: there exist PHYs that run
-		 * with SGMII but do not send the inband data.
-		 */
-		if (!phylink_autoneg_inband(mode))
-			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
-		else
-			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
-		break;
-
-	case PHY_INTERFACE_MODE_1000BASEX:
-	case PHY_INTERFACE_MODE_2500BASEX:
-		/* 1000base-X is designed for use media-side for Fibre
-		 * connections, and thus the Autoneg bit needs to be
-		 * taken into account. We also do this for 2500base-X
-		 * as well, but drivers may not support this, so may
-		 * need to override this.
-		 */
-		if (!phylink_autoneg_inband(mode))
-			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
-		else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
-					   advertising))
-			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
-		else
-			neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;
-		break;
-
-	default:
-		neg_mode = PHYLINK_PCS_NEG_NONE;
-		break;
-	}
-
-	return neg_mode;
-}
-
 /**
  * struct phylink_link_state - link state structure
  * @advertising: ethtool bitmask containing advertised link modes
-- 
2.42.0

Re: [PATCH v3 1/6] net: phylink: move phylink_pcs_neg_mode() to phylink.c

[Russell King (Oracle)]

Hi,

You don't need this patch for your series, and you're bypassing my
ability to decide when this patch should be merged (which is not yet,
I want things to remain as-is for another cycle.)

In theory, looking at past history, 6.7 will probably be a LTS kernel,
but until that is known for certain, I don't want to commit to moving
this function in case LTS gets delayed by a cycle.

Please drop it from your series.

Thanks.

On Wed, Nov 15, 2023 at 10:06:25PM +0800, Luo Jie wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> Russell points out that there is no user of phylink_pcs_neg_mode()
> outside of phylink.c, nor is there planned to be any, so we can just
> move it there.
> 
> Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
> ---
>  drivers/net/phy/phylink.c | 65 ++++++++++++++++++++++++++++++++++++++
>  include/linux/phylink.h   | 66 ---------------------------------------
>  2 files changed, 65 insertions(+), 66 deletions(-)
> 
> diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
> index 25c19496a336..162f51b0986a 100644
> --- a/drivers/net/phy/phylink.c
> +++ b/drivers/net/phy/phylink.c
> @@ -162,6 +162,71 @@ static const char *phylink_an_mode_str(unsigned int mode)
>  	return mode < ARRAY_SIZE(modestr) ? modestr[mode] : "unknown";
>  }
>  
> +/**
> + * phylink_pcs_neg_mode() - helper to determine PCS inband mode
> + * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
> + * @interface: interface mode to be used
> + * @advertising: adertisement ethtool link mode mask
> + *
> + * Determines the negotiation mode to be used by the PCS, and returns
> + * one of:
> + *
> + * - %PHYLINK_PCS_NEG_NONE: interface mode does not support inband
> + * - %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY)
> + *   will be used.
> + * - %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg
> + *   disabled
> + * - %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled
> + *
> + * Note: this is for cases where the PCS itself is involved in negotiation
> + * (e.g. Clause 37, SGMII and similar) not Clause 73.
> + */
> +static unsigned int phylink_pcs_neg_mode(unsigned int mode, phy_interface_t interface,
> +					 const unsigned long *advertising)
> +{
> +	unsigned int neg_mode;
> +
> +	switch (interface) {
> +	case PHY_INTERFACE_MODE_SGMII:
> +	case PHY_INTERFACE_MODE_QSGMII:
> +	case PHY_INTERFACE_MODE_QUSGMII:
> +	case PHY_INTERFACE_MODE_USXGMII:
> +		/* These protocols are designed for use with a PHY which
> +		 * communicates its negotiation result back to the MAC via
> +		 * inband communication. Note: there exist PHYs that run
> +		 * with SGMII but do not send the inband data.
> +		 */
> +		if (!phylink_autoneg_inband(mode))
> +			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
> +		else
> +			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
> +		break;
> +
> +	case PHY_INTERFACE_MODE_1000BASEX:
> +	case PHY_INTERFACE_MODE_2500BASEX:
> +		/* 1000base-X is designed for use media-side for Fibre
> +		 * connections, and thus the Autoneg bit needs to be
> +		 * taken into account. We also do this for 2500base-X
> +		 * as well, but drivers may not support this, so may
> +		 * need to override this.
> +		 */
> +		if (!phylink_autoneg_inband(mode))
> +			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
> +		else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
> +					   advertising))
> +			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
> +		else
> +			neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;
> +		break;
> +
> +	default:
> +		neg_mode = PHYLINK_PCS_NEG_NONE;
> +		break;
> +	}
> +
> +	return neg_mode;
> +}
> +
>  static unsigned int phylink_interface_signal_rate(phy_interface_t interface)
>  {
>  	switch (interface) {
> diff --git a/include/linux/phylink.h b/include/linux/phylink.h
> index 875439ab45de..d589f89c612c 100644
> --- a/include/linux/phylink.h
> +++ b/include/linux/phylink.h
> @@ -98,72 +98,6 @@ static inline bool phylink_autoneg_inband(unsigned int mode)
>  	return mode == MLO_AN_INBAND;
>  }
>  
> -/**
> - * phylink_pcs_neg_mode() - helper to determine PCS inband mode
> - * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
> - * @interface: interface mode to be used
> - * @advertising: adertisement ethtool link mode mask
> - *
> - * Determines the negotiation mode to be used by the PCS, and returns
> - * one of:
> - *
> - * - %PHYLINK_PCS_NEG_NONE: interface mode does not support inband
> - * - %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY)
> - *   will be used.
> - * - %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg
> - *   disabled
> - * - %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled
> - *
> - * Note: this is for cases where the PCS itself is involved in negotiation
> - * (e.g. Clause 37, SGMII and similar) not Clause 73.
> - */
> -static inline unsigned int phylink_pcs_neg_mode(unsigned int mode,
> -						phy_interface_t interface,
> -						const unsigned long *advertising)
> -{
> -	unsigned int neg_mode;
> -
> -	switch (interface) {
> -	case PHY_INTERFACE_MODE_SGMII:
> -	case PHY_INTERFACE_MODE_QSGMII:
> -	case PHY_INTERFACE_MODE_QUSGMII:
> -	case PHY_INTERFACE_MODE_USXGMII:
> -		/* These protocols are designed for use with a PHY which
> -		 * communicates its negotiation result back to the MAC via
> -		 * inband communication. Note: there exist PHYs that run
> -		 * with SGMII but do not send the inband data.
> -		 */
> -		if (!phylink_autoneg_inband(mode))
> -			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
> -		else
> -			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
> -		break;
> -
> -	case PHY_INTERFACE_MODE_1000BASEX:
> -	case PHY_INTERFACE_MODE_2500BASEX:
> -		/* 1000base-X is designed for use media-side for Fibre
> -		 * connections, and thus the Autoneg bit needs to be
> -		 * taken into account. We also do this for 2500base-X
> -		 * as well, but drivers may not support this, so may
> -		 * need to override this.
> -		 */
> -		if (!phylink_autoneg_inband(mode))
> -			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
> -		else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
> -					   advertising))
> -			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
> -		else
> -			neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;
> -		break;
> -
> -	default:
> -		neg_mode = PHYLINK_PCS_NEG_NONE;
> -		break;
> -	}
> -
> -	return neg_mode;
> -}
> -
>  /**
>   * struct phylink_link_state - link state structure
>   * @advertising: ethtool bitmask containing advertised link modes
> -- 
> 2.42.0
> 
> 

-- 
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Re: [PATCH v3 1/6] net: phylink: move phylink_pcs_neg_mode() to phylink.c

[Jie Luo]

On 11/15/2023 10:14 PM, Russell King (Oracle) wrote:
> Hi,
> 
> You don't need this patch for your series, and you're bypassing my
> ability to decide when this patch should be merged (which is not yet,
> I want things to remain as-is for another cycle.)
> 
> In theory, looking at past history, 6.7 will probably be a LTS kernel,
> but until that is known for certain, I don't want to commit to moving
> this function in case LTS gets delayed by a cycle.
> 
> Please drop it from your series.
> 
> Thanks.

Got it, Russell.
I will drop this patch in the next patch set, Thanks.

> 
> On Wed, Nov 15, 2023 at 10:06:25PM +0800, Luo Jie wrote:
>> From: Vladimir Oltean <vladimir.oltean@nxp.com>
>>
>> Russell points out that there is no user of phylink_pcs_neg_mode()
>> outside of phylink.c, nor is there planned to be any, so we can just
>> move it there.
>>
>> Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
>> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
>> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
>> ---
>>   drivers/net/phy/phylink.c | 65 ++++++++++++++++++++++++++++++++++++++
>>   include/linux/phylink.h   | 66 ---------------------------------------
>>   2 files changed, 65 insertions(+), 66 deletions(-)
>>
>> diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
>> index 25c19496a336..162f51b0986a 100644
>> --- a/drivers/net/phy/phylink.c
>> +++ b/drivers/net/phy/phylink.c
>> @@ -162,6 +162,71 @@ static const char *phylink_an_mode_str(unsigned int mode)
>>   	return mode < ARRAY_SIZE(modestr) ? modestr[mode] : "unknown";
>>   }
>>   
>> +/**
>> + * phylink_pcs_neg_mode() - helper to determine PCS inband mode
>> + * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
>> + * @interface: interface mode to be used
>> + * @advertising: adertisement ethtool link mode mask
>> + *
>> + * Determines the negotiation mode to be used by the PCS, and returns
>> + * one of:
>> + *
>> + * - %PHYLINK_PCS_NEG_NONE: interface mode does not support inband
>> + * - %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY)
>> + *   will be used.
>> + * - %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg
>> + *   disabled
>> + * - %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled
>> + *
>> + * Note: this is for cases where the PCS itself is involved in negotiation
>> + * (e.g. Clause 37, SGMII and similar) not Clause 73.
>> + */
>> +static unsigned int phylink_pcs_neg_mode(unsigned int mode, phy_interface_t interface,
>> +					 const unsigned long *advertising)
>> +{
>> +	unsigned int neg_mode;
>> +
>> +	switch (interface) {
>> +	case PHY_INTERFACE_MODE_SGMII:
>> +	case PHY_INTERFACE_MODE_QSGMII:
>> +	case PHY_INTERFACE_MODE_QUSGMII:
>> +	case PHY_INTERFACE_MODE_USXGMII:
>> +		/* These protocols are designed for use with a PHY which
>> +		 * communicates its negotiation result back to the MAC via
>> +		 * inband communication. Note: there exist PHYs that run
>> +		 * with SGMII but do not send the inband data.
>> +		 */
>> +		if (!phylink_autoneg_inband(mode))
>> +			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
>> +		else
>> +			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
>> +		break;
>> +
>> +	case PHY_INTERFACE_MODE_1000BASEX:
>> +	case PHY_INTERFACE_MODE_2500BASEX:
>> +		/* 1000base-X is designed for use media-side for Fibre
>> +		 * connections, and thus the Autoneg bit needs to be
>> +		 * taken into account. We also do this for 2500base-X
>> +		 * as well, but drivers may not support this, so may
>> +		 * need to override this.
>> +		 */
>> +		if (!phylink_autoneg_inband(mode))
>> +			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
>> +		else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
>> +					   advertising))
>> +			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
>> +		else
>> +			neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;
>> +		break;
>> +
>> +	default:
>> +		neg_mode = PHYLINK_PCS_NEG_NONE;
>> +		break;
>> +	}
>> +
>> +	return neg_mode;
>> +}
>> +
>>   static unsigned int phylink_interface_signal_rate(phy_interface_t interface)
>>   {
>>   	switch (interface) {
>> diff --git a/include/linux/phylink.h b/include/linux/phylink.h
>> index 875439ab45de..d589f89c612c 100644
>> --- a/include/linux/phylink.h
>> +++ b/include/linux/phylink.h
>> @@ -98,72 +98,6 @@ static inline bool phylink_autoneg_inband(unsigned int mode)
>>   	return mode == MLO_AN_INBAND;
>>   }
>>   
>> -/**
>> - * phylink_pcs_neg_mode() - helper to determine PCS inband mode
>> - * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
>> - * @interface: interface mode to be used
>> - * @advertising: adertisement ethtool link mode mask
>> - *
>> - * Determines the negotiation mode to be used by the PCS, and returns
>> - * one of:
>> - *
>> - * - %PHYLINK_PCS_NEG_NONE: interface mode does not support inband
>> - * - %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY)
>> - *   will be used.
>> - * - %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg
>> - *   disabled
>> - * - %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled
>> - *
>> - * Note: this is for cases where the PCS itself is involved in negotiation
>> - * (e.g. Clause 37, SGMII and similar) not Clause 73.
>> - */
>> -static inline unsigned int phylink_pcs_neg_mode(unsigned int mode,
>> -						phy_interface_t interface,
>> -						const unsigned long *advertising)
>> -{
>> -	unsigned int neg_mode;
>> -
>> -	switch (interface) {
>> -	case PHY_INTERFACE_MODE_SGMII:
>> -	case PHY_INTERFACE_MODE_QSGMII:
>> -	case PHY_INTERFACE_MODE_QUSGMII:
>> -	case PHY_INTERFACE_MODE_USXGMII:
>> -		/* These protocols are designed for use with a PHY which
>> -		 * communicates its negotiation result back to the MAC via
>> -		 * inband communication. Note: there exist PHYs that run
>> -		 * with SGMII but do not send the inband data.
>> -		 */
>> -		if (!phylink_autoneg_inband(mode))
>> -			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
>> -		else
>> -			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
>> -		break;
>> -
>> -	case PHY_INTERFACE_MODE_1000BASEX:
>> -	case PHY_INTERFACE_MODE_2500BASEX:
>> -		/* 1000base-X is designed for use media-side for Fibre
>> -		 * connections, and thus the Autoneg bit needs to be
>> -		 * taken into account. We also do this for 2500base-X
>> -		 * as well, but drivers may not support this, so may
>> -		 * need to override this.
>> -		 */
>> -		if (!phylink_autoneg_inband(mode))
>> -			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
>> -		else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
>> -					   advertising))
>> -			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
>> -		else
>> -			neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;
>> -		break;
>> -
>> -	default:
>> -		neg_mode = PHYLINK_PCS_NEG_NONE;
>> -		break;
>> -	}
>> -
>> -	return neg_mode;
>> -}
>> -
>>   /**
>>    * struct phylink_link_state - link state structure
>>    * @advertising: ethtool bitmask containing advertised link modes
>> -- 
>> 2.42.0
>>
>>
> 

[PATCH v3 2/6] net: phy: introduce core support for phy-mode = "10g-qxgmii"

[Luo Jie]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport
specification. It uses the same signaling as USXGMII, but it multiplexes
4 ports over the link, resulting in a maximum speed of 2.5G per port.

Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean
either the single-port USXGMII or the quad-port 10G-QXGMII variant, and
they could get away just fine with that thus far. But there is a need to
distinguish between the 2 as far as SerDes drivers are concerned.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 .../devicetree/bindings/net/ethernet-controller.yaml |  1 +
 Documentation/networking/phy.rst                     |  6 ++++++
 drivers/net/phy/phy-core.c                           |  1 +
 drivers/net/phy/phylink.c                            | 12 ++++++++++--
 include/linux/phy.h                                  |  4 ++++
 include/linux/phylink.h                              |  1 +
 6 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
index 9f6a5ccbcefe..044880d804db 100644
--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
@@ -104,6 +104,7 @@ properties:
       - usxgmii
       - 10gbase-r
       - 25gbase-r
+      - 10g-qxgmii
 
   phy-mode:
     $ref: "#/properties/phy-connection-type"
diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst
index 1283240d7620..f64641417c54 100644
--- a/Documentation/networking/phy.rst
+++ b/Documentation/networking/phy.rst
@@ -327,6 +327,12 @@ Some of the interface modes are described below:
     This is the Penta SGMII mode, it is similar to QSGMII but it combines 5
     SGMII lines into a single link compared to 4 on QSGMII.
 
+``PHY_INTERFACE_MODE_10G_QXGMII``
+    Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII
+    Multiport Copper Interface document. It supports 4 ports over a 10.3125 GHz
+    SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved
+    through symbol replication. The PCS expects the standard USXGMII code word.
+
 Pause frames / flow control
 ===========================
 
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 966c93cbe616..1cd58723d6d0 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -141,6 +141,7 @@ int phy_interface_num_ports(phy_interface_t interface)
 		return 1;
 	case PHY_INTERFACE_MODE_QSGMII:
 	case PHY_INTERFACE_MODE_QUSGMII:
+	case PHY_INTERFACE_MODE_10G_QXGMII:
 		return 4;
 	case PHY_INTERFACE_MODE_PSGMII:
 		return 5;
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 162f51b0986a..e9ab20bd6984 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -191,6 +191,7 @@ static unsigned int phylink_pcs_neg_mode(unsigned int mode, phy_interface_t inte
 	case PHY_INTERFACE_MODE_QSGMII:
 	case PHY_INTERFACE_MODE_QUSGMII:
 	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10G_QXGMII:
 		/* These protocols are designed for use with a PHY which
 		 * communicates its negotiation result back to the MAC via
 		 * inband communication. Note: there exist PHYs that run
@@ -283,6 +284,7 @@ static int phylink_interface_max_speed(phy_interface_t interface)
 		return SPEED_1000;
 
 	case PHY_INTERFACE_MODE_2500BASEX:
+	case PHY_INTERFACE_MODE_10G_QXGMII:
 		return SPEED_2500;
 
 	case PHY_INTERFACE_MODE_5GBASER:
@@ -552,7 +554,11 @@ static unsigned long phylink_get_capabilities(phy_interface_t interface,
 
 	switch (interface) {
 	case PHY_INTERFACE_MODE_USXGMII:
-		caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD;
+		caps |= MAC_10000FD | MAC_5000FD;
+		fallthrough;
+
+	case PHY_INTERFACE_MODE_10G_QXGMII:
+		caps |= MAC_2500FD;
 		fallthrough;
 
 	case PHY_INTERFACE_MODE_RGMII_TXID:
@@ -972,6 +978,7 @@ static int phylink_parse_mode(struct phylink *pl,
 			phylink_set(pl->supported, 25000baseSR_Full);
 			fallthrough;
 		case PHY_INTERFACE_MODE_USXGMII:
+		case PHY_INTERFACE_MODE_10G_QXGMII:
 		case PHY_INTERFACE_MODE_10GKR:
 		case PHY_INTERFACE_MODE_10GBASER:
 			phylink_set(pl->supported, 10baseT_Half);
@@ -1844,7 +1851,8 @@ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy,
 	if (phy->is_c45 && config.rate_matching == RATE_MATCH_NONE &&
 	    interface != PHY_INTERFACE_MODE_RXAUI &&
 	    interface != PHY_INTERFACE_MODE_XAUI &&
-	    interface != PHY_INTERFACE_MODE_USXGMII)
+	    interface != PHY_INTERFACE_MODE_USXGMII &&
+	    interface != PHY_INTERFACE_MODE_10G_QXGMII)
 		config.interface = PHY_INTERFACE_MODE_NA;
 	else
 		config.interface = interface;
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 3cc52826f18e..e0af0378e2a1 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -125,6 +125,7 @@ extern const int phy_10gbit_features_array[1];
  * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN
  * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII
  * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN
+ * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII
  * @PHY_INTERFACE_MODE_MAX: Book keeping
  *
  * Describes the interface between the MAC and PHY.
@@ -165,6 +166,7 @@ typedef enum {
 	PHY_INTERFACE_MODE_10GKR,
 	PHY_INTERFACE_MODE_QUSGMII,
 	PHY_INTERFACE_MODE_1000BASEKX,
+	PHY_INTERFACE_MODE_10G_QXGMII,
 	PHY_INTERFACE_MODE_MAX,
 } phy_interface_t;
 
@@ -286,6 +288,8 @@ static inline const char *phy_modes(phy_interface_t interface)
 		return "100base-x";
 	case PHY_INTERFACE_MODE_QUSGMII:
 		return "qusgmii";
+	case PHY_INTERFACE_MODE_10G_QXGMII:
+		return "10g-qxgmii";
 	default:
 		return "unknown";
 	}
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index d589f89c612c..d7e32c9f3ae1 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -614,6 +614,7 @@ static inline int phylink_get_link_timer_ns(phy_interface_t interface)
 	case PHY_INTERFACE_MODE_SGMII:
 	case PHY_INTERFACE_MODE_QSGMII:
 	case PHY_INTERFACE_MODE_USXGMII:
+	case PHY_INTERFACE_MODE_10G_QXGMII:
 		return 1600000;
 
 	case PHY_INTERFACE_MODE_1000BASEX:
-- 
2.42.0

Re: [PATCH v3 2/6] net: phy: introduce core support for phy-mode = "10g-qxgmii"

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 895 bytes --]

On Wed, Nov 15, 2023 at 10:06:26PM +0800, Luo Jie wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> 10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport
> specification. It uses the same signaling as USXGMII, but it multiplexes
> 4 ports over the link, resulting in a maximum speed of 2.5G per port.
> 
> Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean
> either the single-port USXGMII or the quad-port 10G-QXGMII variant, and
> they could get away just fine with that thus far. But there is a need to
> distinguish between the 2 as far as SerDes drivers are concerned.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
> ---
>  .../devicetree/bindings/net/ethernet-controller.yaml |  1 +

I know it is one line, but bindings need to be in their own patches
please.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v3 2/6] net: phy: introduce core support for phy-mode = "10g-qxgmii"

[Jie Luo]

On 11/15/2023 10:31 PM, Conor Dooley wrote:
> On Wed, Nov 15, 2023 at 10:06:26PM +0800, Luo Jie wrote:
>> From: Vladimir Oltean <vladimir.oltean@nxp.com>
>>
>> 10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport
>> specification. It uses the same signaling as USXGMII, but it multiplexes
>> 4 ports over the link, resulting in a maximum speed of 2.5G per port.
>>
>> Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean
>> either the single-port USXGMII or the quad-port 10G-QXGMII variant, and
>> they could get away just fine with that thus far. But there is a need to
>> distinguish between the 2 as far as SerDes drivers are concerned.
>>
>> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
>> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
>> ---
>>   .../devicetree/bindings/net/ethernet-controller.yaml |  1 +
> 
> I know it is one line, but bindings need to be in their own patches
> please.

Ok, will split the binding change out as a separate patch.
Thanks Conor for the suggestion.

[PATCH v3 3/6] net: phy: at803x: add QCA8084 ethernet phy support

[Luo Jie]

Add qca8084 PHY support, which is four-port PHY with maximum
link capability 2.5G, the features of each port is almost same
as QCA8081 and slave seed config is not needed.

Three kind of interface modes supported by qca8084.
PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_2500BASEX and
PHY_INTERFACE_MODE_SGMII.

The PCS(serdes) and clock are also needed to be configured to
bringup qca8084 PHY, which will be added in the pcs driver.

The additional CDT configurations used for qca8084.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 drivers/net/phy/at803x.c | 48 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 37fb033e1c29..471d5c13d76d 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -176,6 +176,7 @@
 #define AT8030_PHY_ID_MASK			0xffffffef
 
 #define QCA8081_PHY_ID				0x004dd101
+#define QCA8084_PHY_ID				0x004dd180
 
 #define QCA8327_A_PHY_ID			0x004dd033
 #define QCA8327_B_PHY_ID			0x004dd034
@@ -1760,6 +1761,9 @@ static bool qca808x_is_prefer_master(struct phy_device *phydev)
 
 static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
 {
+	if (phydev_id_compare(phydev, QCA8084_PHY_ID))
+		return false;
+
 	return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
 }
 
@@ -1824,6 +1828,21 @@ static int qca808x_read_status(struct phy_device *phydev)
 		return ret;
 
 	if (phydev->link) {
+		/* There are two PCSs available for QCA8084, which support the following
+		 * interface modes.
+		 *
+		 * 1. PHY_INTERFACE_MODE_10G_QXGMII utilizes PCS1 for all available 4 ports,
+		 * which is for all link speeds.
+		 *
+		 * 2. PHY_INTERFACE_MODE_2500BASEX utilizes PCS0 for the fourth port,
+		 * which is only for the link speed 2500M same as QCA8081.
+		 *
+		 * 3. PHY_INTERFACE_MODE_SGMII utilizes PCS0 for the fourth port,
+		 * which is for the link speed 10M, 100M and 1000M same as QCA8081.
+		 */
+		if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII)
+			return 0;
+
 		if (phydev->speed == SPEED_2500)
 			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
 		else
@@ -1958,6 +1977,14 @@ static int qca808x_cable_test_start(struct phy_device *phydev)
 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
 
+	if (phydev_id_compare(phydev, QCA8084_PHY_ID)) {
+		/* Adjust the positive and negative pulse thereshold of CDT */
+		phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8075, 0xa060);
+
+		/* Disable the near echo bypass */
+		phy_modify_mmd(phydev, MDIO_MMD_PCS, 0x807f, BIT(15), 0);
+	}
+
 	return 0;
 }
 
@@ -2227,6 +2254,26 @@ static struct phy_driver at803x_driver[] = {
 	.cable_test_start	= qca808x_cable_test_start,
 	.cable_test_get_status	= qca808x_cable_test_get_status,
 	.link_change_notify	= qca808x_link_change_notify,
+}, {
+	/* Qualcomm QCA8084 */
+	PHY_ID_MATCH_MODEL(QCA8084_PHY_ID),
+	.name			= "Qualcomm QCA8084",
+	.flags			= PHY_POLL_CABLE_TEST,
+	.probe			= at803x_probe,
+	.config_intr		= at803x_config_intr,
+	.handle_interrupt	= at803x_handle_interrupt,
+	.get_tunable		= at803x_get_tunable,
+	.set_tunable		= at803x_set_tunable,
+	.set_wol		= at803x_set_wol,
+	.get_wol		= at803x_get_wol,
+	.get_features		= qca808x_get_features,
+	.config_aneg		= at803x_config_aneg,
+	.suspend		= genphy_suspend,
+	.resume			= genphy_resume,
+	.read_status		= qca808x_read_status,
+	.soft_reset		= qca808x_soft_reset,
+	.cable_test_start	= qca808x_cable_test_start,
+	.cable_test_get_status	= qca808x_cable_test_get_status,
 }, };
 
 module_phy_driver(at803x_driver);
@@ -2242,6 +2289,7 @@ static struct mdio_device_id __maybe_unused atheros_tbl[] = {
 	{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
 	{ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
 	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
+	{ PHY_ID_MATCH_MODEL(QCA8084_PHY_ID) },
 	{ }
 };
 
-- 
2.42.0

[PATCH v3 4/6] net: phy: at803x: add the function phydev_id_is_qca808x

[Luo Jie]

The function phydev_id_is_qca808x is applicable to the
PHY qca8081 and qca8084.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 drivers/net/phy/at803x.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 471d5c13d76d..f56202f5944d 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -1165,6 +1165,12 @@ static void at803x_link_change_notify(struct phy_device *phydev)
 	}
 }
 
+static inline bool phydev_id_is_qca808x(struct phy_device *phydev)
+{
+	return phydev_id_compare(phydev, QCA8081_PHY_ID) ||
+		phydev_id_compare(phydev, QCA8084_PHY_ID);
+}
+
 static int at803x_read_specific_status(struct phy_device *phydev)
 {
 	int ss;
@@ -1184,8 +1190,8 @@ static int at803x_read_specific_status(struct phy_device *phydev)
 		if (sfc < 0)
 			return sfc;
 
-		/* qca8081 takes the different bits for speed value from at803x */
-		if (phydev->drv->phy_id == QCA8081_PHY_ID)
+		/* qca808x takes the different bits for speed value from at803x */
+		if (phydev_id_is_qca808x(phydev))
 			speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss);
 		else
 			speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss);
@@ -1316,7 +1322,7 @@ static int at803x_config_aneg(struct phy_device *phydev)
 	 */
 	ret = 0;
 
-	if (phydev->drv->phy_id == QCA8081_PHY_ID) {
+	if (phydev_id_is_qca808x(phydev)) {
 		int phy_ctrl = 0;
 
 		/* The reg MII_BMCR also needs to be configured for force mode, the
@@ -1470,8 +1476,8 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair)
 {
 	u16 cdt;
 
-	/* qca8081 takes the different bit 15 to enable CDT test */
-	if (phydev->drv->phy_id == QCA8081_PHY_ID)
+	/* qca808x takes the different bit 15 to enable CDT test */
+	if (phydev_id_is_qca808x(phydev))
 		cdt = QCA808X_CDT_ENABLE_TEST |
 			QCA808X_CDT_LENGTH_UNIT |
 			QCA808X_CDT_INTER_CHECK_DIS;
@@ -1487,7 +1493,7 @@ static int at803x_cdt_wait_for_completion(struct phy_device *phydev)
 	int val, ret;
 	u16 cdt_en;
 
-	if (phydev->drv->phy_id == QCA8081_PHY_ID)
+	if (phydev_id_is_qca808x(phydev))
 		cdt_en = QCA808X_CDT_ENABLE_TEST;
 	else
 		cdt_en = AT803X_CDT_ENABLE_TEST;
-- 
2.42.0

[PATCH v3 5/6] net: phy: at803x: Add qca8084_config_init function

[Luo Jie]

Configure MSE detect threshold and ADC clock edge invert.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 drivers/net/phy/at803x.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index f56202f5944d..06a068ca5539 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -280,6 +280,15 @@
 #define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL	0x9072
 #define QCA8081_PHY_FIFO_RSTN			BIT(11)
 
+/* QCA8084 ADC clock edge */
+#define QCA8084_ADC_CLK_SEL			0x8b80
+#define QCA8084_ADC_CLK_SEL_ACLK		GENMASK(7, 4)
+#define QCA8084_ADC_CLK_SEL_ACLK_FALL		0xf
+#define QCA8084_ADC_CLK_SEL_ACLK_RISE		0x0
+
+#define QCA8084_MSE_THRESHOLD			0x800a
+#define QCA8084_MSE_THRESHOLD_2P5G_VAL		0x51c6
+
 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
 MODULE_AUTHOR("Matus Ujhelyi");
 MODULE_LICENSE("GPL");
@@ -2083,6 +2092,23 @@ static void qca808x_link_change_notify(struct phy_device *phydev)
 			QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
 }
 
+static int qca8084_config_init(struct phy_device *phydev)
+{
+	int ret;
+
+	/* Invert ADC clock edge */
+	ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL,
+				    QCA8084_ADC_CLK_SEL_ACLK,
+				    FIELD_PREP(QCA8084_ADC_CLK_SEL_ACLK,
+					       QCA8084_ADC_CLK_SEL_ACLK_FALL));
+	if (ret < 0)
+		return ret;
+
+	/* Adjust MSE threshold value to avoid link issue with some link partner */
+	return phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
+			     QCA8084_MSE_THRESHOLD, QCA8084_MSE_THRESHOLD_2P5G_VAL);
+}
+
 static struct phy_driver at803x_driver[] = {
 {
 	/* Qualcomm Atheros AR8035 */
@@ -2280,6 +2306,7 @@ static struct phy_driver at803x_driver[] = {
 	.soft_reset		= qca808x_soft_reset,
 	.cable_test_start	= qca808x_cable_test_start,
 	.cable_test_get_status	= qca808x_cable_test_get_status,
+	.config_init		= qca8084_config_init,
 }, };
 
 module_phy_driver(at803x_driver);
-- 
2.42.0

[PATCH v3 6/6] net: phy: qca8084: add qca8084_link_change_notify

[Luo Jie]

When the link is changed, qca8084 needs to do the fifo reset and
adjust the IPG level for the qusgmii link speed 1000M.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 drivers/net/phy/at803x.c | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index 06a068ca5539..7267ce858937 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -289,6 +289,13 @@
 #define QCA8084_MSE_THRESHOLD			0x800a
 #define QCA8084_MSE_THRESHOLD_2P5G_VAL		0x51c6
 
+#define QCA8084_FIFO_CONTROL			0x19
+#define QCA8084_FIFO_MAC_2_PHY			BIT(1)
+#define QCA8084_FIFO_PHY_2_MAC			BIT(0)
+
+#define QCA8084_MMD7_IPG_OP			0x901d
+#define QCA8084_IPG_10_TO_11_EN			BIT(0)
+
 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
 MODULE_AUTHOR("Matus Ujhelyi");
 MODULE_LICENSE("GPL");
@@ -2109,6 +2116,35 @@ static int qca8084_config_init(struct phy_device *phydev)
 			     QCA8084_MSE_THRESHOLD, QCA8084_MSE_THRESHOLD_2P5G_VAL);
 }
 
+static void qca8084_link_change_notify(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = phy_modify(phydev, QCA8084_FIFO_CONTROL,
+			 QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC,
+			 0);
+	if (ret)
+		return;
+
+	/* If the PHY works on PHY_INTERFACE_MODE_10G_QXGMII mode, the fifo needs to
+	 * be kept as reset state in link down status.
+	 */
+	if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII || phydev->link) {
+		msleep(50);
+		ret = phy_modify(phydev, QCA8084_FIFO_CONTROL,
+				 QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC,
+				 QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC);
+		if (ret)
+			return;
+	}
+
+	/* Enable IPG 10 to 11 tuning on link speed 1000M of QUSGMII mode. */
+	if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII)
+		phy_modify_mmd(phydev, MDIO_MMD_AN, QCA8084_MMD7_IPG_OP,
+			       QCA8084_IPG_10_TO_11_EN,
+			       phydev->speed == SPEED_1000 ? QCA8084_IPG_10_TO_11_EN : 0);
+}
+
 static struct phy_driver at803x_driver[] = {
 {
 	/* Qualcomm Atheros AR8035 */
@@ -2307,6 +2343,7 @@ static struct phy_driver at803x_driver[] = {
 	.cable_test_start	= qca808x_cable_test_start,
 	.cable_test_get_status	= qca808x_cable_test_get_status,
 	.config_init		= qca8084_config_init,
+	.link_change_notify	= qca8084_link_change_notify,
 }, };
 
 module_phy_driver(at803x_driver);
-- 
2.42.0