Re: [PATCH v2 1/3] arm64: dts: qcom: x1e80100-hp-x14: add usb-1-ss1-sbu-mux

Johan Hovold
2025-04-11T11:25:35Z

[ +CC: Stephan ]

On Thu, Apr 10, 2025 at 12:07:28PM +0200, Jens Glathe via B4 Relay wrote:
> From: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
>
> The usb_1_1 port doesn't have the PS8830 repeater, but apparently some
> MUX for DP altmode control. After a suggestion from sgerhold on
> '#aarch64-laptops' I added gpio-sbu-mux nodes from the x1e80100-QCP
> tree, and this appears to work well. It is still guesswork, but
> working guesswork.

Did you confirm the three GPIOs experimentally, for example, by making
sure that inverting the enable signal polarity breaks USB?

> + usb-1-ss1-sbu-mux {
> + compatible = "onnn,fsusb42", "gpio-sbu-mux";
> +
> + enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>;
> + select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-0 = <&usb_1_ss1_sbu_default>;
> + pinctrl-names = "default";

> };
>
> &apps_rsc {
> @@ -1424,6 +1451,30 @@ reset-n-pins {
> };
> };
>
> + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state {
> + mode-pins {
> + pins = "gpio177";
> + function = "gpio";
> + bias-disable;
> + drive-strength = <2>;
> + output-high;
> + };

This is more of a question for Stephan who added this to QCP [1], but
why is this mode pin here and what does it do?

It's not part of the binding for the mux (which indeed only has two
control signals according to the datasheet) so it looks like something
is not modelled correctly.

> +
> + oe-n-pins {
> + pins = "gpio179";
> + function = "gpio";
> + bias-disable;
> + drive-strength = <2>;
> + };
> +
> + sel-pins {
> + pins = "gpio178";
> + function = "gpio";
> + bias-disable;
> + drive-strength = <2>;
> + };
> + };

Johan

[1] https://lore.kernel.org/all/20241212-x1e80100-qcp-dp-v1-2-37cb362a0dfe@linaro.org/