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Thu, 25 Jan 2024 00:02:39 -0800 (PST) Received: from linaro.org ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id ig8-20020a1709072e0800b00a31930ffa7esm80917ejc.153.2024.01.25.00.02.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 00:02:39 -0800 (PST) Date: Thu, 25 Jan 2024 10:02:37 +0200 From: Abel Vesa To: Konrad Dybcio Cc: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 07/11] arm64: dts: qcom: x1e80100: Add PCIe nodes Message-ID: References: <20240123-x1e80100-dts-missing-nodes-v4-0-072dc2f5c153@linaro.org> <20240123-x1e80100-dts-missing-nodes-v4-7-072dc2f5c153@linaro.org> <3d029d7c-7efb-42bb-a16d-30cf965f410b@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3d029d7c-7efb-42bb-a16d-30cf965f410b@linaro.org> On 24-01-23 19:20:38, Konrad Dybcio wrote: > > > On 1/23/24 12:01, Abel Vesa wrote: > > Add nodes for PCIe 4 and 6 controllers and their PHYs for X1E80100 platform. > > > > Co-developed-by: Sibi Sankar > > Signed-off-by: Sibi Sankar > > Co-developed-by: Rajendra Nayak > > Signed-off-by: Rajendra Nayak > > Signed-off-by: Abel Vesa > > --- > > [...] > > > + > > + interrupts = ; > > + interrupt-names = "msi"; > > You may want to add ITS MSIs too That will be added after we figure out the mapping. > > [...] > > > + > > + resets = <&gcc GCC_PCIE_6A_BCR>, > > + <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; > > The second entry is misaligned > > Konrad