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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?rgpSJHOASE8Sk9uBMs3Fh+o6mlumerFvd4VliNoSmF5Ah9u8L6ev8Sor41F6?= =?us-ascii?Q?35p/FEU16FWPnDCDfl82TLGGjTVL4EKFGtttSupWkEaInZzptGf8m+HdrbE/?= =?us-ascii?Q?Fzz7HU8ymdD8ARr3tYWbBkPMvEDn/g3UxbdKza0zPBhd7WB4RW6B2j/5r77Z?= =?us-ascii?Q?hCRU7w+dWRe5u1b7akoxWHiRhykma7bHThVGFBdcSL+r7DyXGqppyc2FckI7?= =?us-ascii?Q?dejtZK+IFwpsn/9WsWzOoMSGK5wzpErw6su7wAn3j94PMhQlptLE6Ig35Q3Z?= =?us-ascii?Q?cKfhEQPxyKIsi2FEpKIk+Fqzq4O/iq4kEY02aruiq94O9KOcFEvyfL4QBrn8?= =?us-ascii?Q?NCY4qkC/m3zVKX4QqRpgbrkPgTlsGOcG3gVR+7GsYlPGjSkaE/liTo7HOqkL?= =?us-ascii?Q?sZGjBMBc+VkUosfaYuCYAIcQIMBJYiPnAHInKMn0OZZk6bjFqfWQNnt+INbx?= =?us-ascii?Q?bgrIVVFmpwN1qgpqyZOlyKPO93q1kYn/9b4V+qluwFtHM4alG9AvW8+AqGf1?= =?us-ascii?Q?qiUHPfrJ/IGaEtuwrSsRZnggRGoqLvuztF8UCoshaKro37IdphwH5UpgnCt3?= =?us-ascii?Q?HH1hVMG3kHt0SkDQxK7a9/deSJdx5Bgal1kGSCCfTQynAlRqdex+ebc3X8W1?= =?us-ascii?Q?z9hGQ4mBZScXiVCbKuldXLb/Fniw2JsoA/scMBVTLs3UM98m1Y+e0fNE//Hq?= =?us-ascii?Q?aF48Bc1+h6o5qUd/9RRiVmEMS6Bj2Q1Ex22utiIAw/EmOVLJiiWeIyoTXvLj?= =?us-ascii?Q?19t/dveGWlHOM/AUlre8Ld3ynUUhs1CXc3BqOmUr0GnltoVeYQdrFzGyZBPE?= =?us-ascii?Q?H11G88/q3aiWGYG0iSjWCanW/LtMBYOyuZjsSdlKpRLnWVeNvi81uldcxp8t?= =?us-ascii?Q?Q+0XWWOH8UHUtE1bBG2/L0AcqaKopuyejU8PBvMEswfMeNpv2qJLbUzH86g/?= =?us-ascii?Q?oPlPOYZI9r71Mu447g36pnhNPyFC5FB+pFYa9NcFhh67lXPOnaUSvZnEbzWv?= =?us-ascii?Q?3LSbMKqivdNDIn/g+HDz1C1hlOnSwkxIwVhJXQA+vTtoEg0I0PWXfO+ljVHn?= =?us-ascii?Q?WqYZ0hmUwYHQkKSU4S6k21kz5sYEjKBmkl9B+a+1Pl/4FRpYCx7SHkZ378v/?= =?us-ascii?Q?ScyxRW387Xq8iB2NQL4ZA8oAOXoUadjPaiiSI5Y3jUCE8qQyOf0BpouXvhrM?= =?us-ascii?Q?0KH3xeUv/AOP3D5V4MnmX3/+CYlJscICgxrn46IcaGmHgfn2Ntnf6TK9PsVK?= =?us-ascii?Q?o1VbQ7H6nCzjHzVog/dlWwpMvSUWSeKLR6WA8yXlT5SWxhRmUv3dCppByzLQ?= =?us-ascii?Q?YnrPGhQJyHJVEQJjxCi9v8IwPYyi17/1y6HoAAzXf1LHpj+CF0ImpDhJoXLc?= =?us-ascii?Q?Zo+JhVKQ3ZD3HdLThhLFlu1tgtw0WAG7PK5X1NtKS84QbSTnN32gmJemr9Zh?= =?us-ascii?Q?B6ut6AKaSkb9m22EI5UQjD7qtwHU8c/V4xVus4kYEuvFii6tdLQ7U4MZ/ela?= =?us-ascii?Q?4AG93bHSS+dTjEmRWM1fzyW15G8mEprGlQVu4whJcPDC4ba8STBuh+bah+zi?= =?us-ascii?Q?CUDvwC95LoW8VsVT6Gkbpw6uGBQSljaWeRcBzIB0?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5f11f19c-e40d-4313-9c0f-08dc211b91d0 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2024 22:42:27.5276 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: hl/5Jl5oLiHSqufjNbay83UB9CI5Y3sduqYr6QLvkFlFov5N2yRRnT2WjXhXpKztgd2UoJXA1TRp1zQqgPcvnA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8582 On Fri, Aug 25, 2023 at 06:32:02PM +0900, Yoshihiro Shimoda wrote: > This is a preparation before adding the Msg-type outbound iATU > mapping. The respective update will require two more arguments added > to __dw_pcie_prog_outbound_atu(). That will make the already > complicated function prototype even more hard to comprehend accepting > _eight_ arguments. In order to prevent that and keep the code > more-or-less readable all the outbound iATU-related arguments are > moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer > to which shall be passed to dw_pcie_prog_outbound_atu(). The structure > is supposed to be locally defined and populated with the outbound iATU > settings implied by the caller context. > > As a result of the denoted change there is no longer need in having > the two distinctive methods for the Host and End-point outbound iATU > setups since the corresponding code can directly call the > dw_pcie_prog_outbound_atu() method with the config-structure > populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped. > > Signed-off-by: Yoshihiro Shimoda > Reviewed-by: Serge Semin > Reviewed-by: Manivannan Sadhasivam Yoshihiro: I want to use this patch to send out PME message when suspend, which should be similar with raise INTx. Can I include your this patches in my PME enable patches list if your patch still not merge yet. Frank > --- > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++--- > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------ > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++----------- > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++-- > 4 files changed, 77 insertions(+), 60 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index ab87ea3b0986..747d5bc07222 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -182,9 +182,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, > return 0; > } > > -static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no, > - phys_addr_t phys_addr, > - u64 pci_addr, size_t size) > +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, > + struct dw_pcie_ob_atu_cfg *atu) > { > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > u32 free_win; > @@ -196,13 +195,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no, > return -EINVAL; > } > > - ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM, > - phys_addr, pci_addr, size); > + atu->index = free_win; > + ret = dw_pcie_prog_outbound_atu(pci, atu); > if (ret) > return ret; > > set_bit(free_win, ep->ob_window_map); > - ep->outbound_addr[free_win] = phys_addr; > + ep->outbound_addr[free_win] = atu->cpu_addr; > > return 0; > } > @@ -305,8 +304,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, > int ret; > struct dw_pcie_ep *ep = epc_get_drvdata(epc); > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > - > - ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size); > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > + > + atu.func_no = func_no; > + atu.type = PCIE_ATU_TYPE_MEM; > + atu.cpu_addr = addr; > + atu.pci_addr = pci_addr; > + atu.size = size; > + ret = dw_pcie_ep_outbound_atu(ep, &atu); > if (ret) { > dev_err(pci->dev, "Failed to enable address\n"); > return ret; > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 5c8cbc3afae4..01eff83c1f6d 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -551,6 +551,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, > { > struct dw_pcie_rp *pp = bus->sysdata; > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > int type, ret; > u32 busdev; > > @@ -573,8 +574,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, > else > type = PCIE_ATU_TYPE_CFG1; > > - ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, > - pp->cfg0_size); > + atu.type = type; > + atu.cpu_addr = pp->cfg0_base; > + atu.pci_addr = busdev; > + atu.size = pp->cfg0_size; > + > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > if (ret) > return NULL; > > @@ -586,6 +591,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, > { > struct dw_pcie_rp *pp = bus->sysdata; > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > int ret; > > ret = pci_generic_config_read(bus, devfn, where, size, val); > @@ -593,9 +599,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, > return ret; > > if (pp->cfg0_io_shared) { > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, > - pp->io_base, pp->io_bus_addr, > - pp->io_size); > + atu.type = PCIE_ATU_TYPE_IO; > + atu.cpu_addr = pp->io_base; > + atu.pci_addr = pp->io_bus_addr; > + atu.size = pp->io_size; > + > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > if (ret) > return PCIBIOS_SET_FAILED; > } > @@ -608,6 +617,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, > { > struct dw_pcie_rp *pp = bus->sysdata; > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > int ret; > > ret = pci_generic_config_write(bus, devfn, where, size, val); > @@ -615,9 +625,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, > return ret; > > if (pp->cfg0_io_shared) { > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, > - pp->io_base, pp->io_bus_addr, > - pp->io_size); > + atu.type = PCIE_ATU_TYPE_IO; > + atu.cpu_addr = pp->io_base; > + atu.pci_addr = pp->io_bus_addr; > + atu.size = pp->io_size; > + > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > if (ret) > return PCIBIOS_SET_FAILED; > } > @@ -652,6 +665,7 @@ static struct pci_ops dw_pcie_ops = { > static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct dw_pcie_ob_atu_cfg atu = { 0 }; > struct resource_entry *entry; > int i, ret; > > @@ -679,10 +693,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > if (pci->num_ob_windows <= ++i) > break; > > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM, > - entry->res->start, > - entry->res->start - entry->offset, > - resource_size(entry->res)); > + atu.index = i; > + atu.type = PCIE_ATU_TYPE_MEM; > + atu.cpu_addr = entry->res->start; > + atu.pci_addr = entry->res->start - entry->offset; > + atu.size = resource_size(entry->res); > + > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > if (ret) { > dev_err(pci->dev, "Failed to set MEM range %pr\n", > entry->res); > @@ -692,10 +709,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > > if (pp->io_size) { > if (pci->num_ob_windows > ++i) { > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO, > - pp->io_base, > - pp->io_bus_addr, > - pp->io_size); > + atu.index = i; > + atu.type = PCIE_ATU_TYPE_IO; > + atu.cpu_addr = pp->io_base; > + atu.pci_addr = pp->io_bus_addr; > + atu.size = pp->io_size; > + > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > if (ret) { > dev_err(pci->dev, "Failed to set IO range %pr\n", > entry->res); > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 2459f2a61b9b..49b785509576 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -464,56 +464,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val) > return val | PCIE_ATU_TD; > } > > -static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, > - int index, int type, u64 cpu_addr, > - u64 pci_addr, u64 size) > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, > + const struct dw_pcie_ob_atu_cfg *atu) > { > + u64 cpu_addr = atu->cpu_addr; > u32 retries, val; > u64 limit_addr; > > if (pci->ops && pci->ops->cpu_addr_fixup) > cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); > > - limit_addr = cpu_addr + size - 1; > + limit_addr = cpu_addr + atu->size - 1; > > if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) || > !IS_ALIGNED(cpu_addr, pci->region_align) || > - !IS_ALIGNED(pci_addr, pci->region_align) || !size) { > + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { > return -EINVAL; > } > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE, > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, > lower_32_bits(cpu_addr)); > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE, > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE, > upper_32_bits(cpu_addr)); > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT, > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT, > lower_32_bits(limit_addr)); > if (dw_pcie_ver_is_ge(pci, 460A)) > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT, > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT, > upper_32_bits(limit_addr)); > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET, > - lower_32_bits(pci_addr)); > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET, > - upper_32_bits(pci_addr)); > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET, > + lower_32_bits(atu->pci_addr)); > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, > + upper_32_bits(atu->pci_addr)); > > - val = type | PCIE_ATU_FUNC_NUM(func_no); > + val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no); > if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && > dw_pcie_ver_is_ge(pci, 460A)) > val |= PCIE_ATU_INCREASE_REGION_SIZE; > if (dw_pcie_ver_is(pci, 490A)) > val = dw_pcie_enable_ecrc(val); > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val); > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); > > /* > * Make sure ATU enable takes effect before any subsequent config > * and I/O accesses. > */ > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { > - val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2); > + val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2); > if (val & PCIE_ATU_ENABLE) > return 0; > > @@ -525,21 +525,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, > return -ETIMEDOUT; > } > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, > - u64 cpu_addr, u64 pci_addr, u64 size) > -{ > - return __dw_pcie_prog_outbound_atu(pci, 0, index, type, > - cpu_addr, pci_addr, size); > -} > - > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, > - int type, u64 cpu_addr, u64 pci_addr, > - u64 size) > -{ > - return __dw_pcie_prog_outbound_atu(pci, func_no, index, type, > - cpu_addr, pci_addr, size); > -} > - > static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg) > { > return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg); > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 755bcb406769..296c5b1ddc91 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -298,6 +298,15 @@ enum dw_pcie_ltssm { > DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF, > }; > > +struct dw_pcie_ob_atu_cfg { > + int index; > + int type; > + u8 func_no; > + u64 cpu_addr; > + u64 pci_addr; > + u64 size; > +}; > + > struct dw_pcie_host_ops { > int (*host_init)(struct dw_pcie_rp *pp); > void (*host_deinit)(struct dw_pcie_rp *pp); > @@ -429,10 +438,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); > int dw_pcie_link_up(struct dw_pcie *pci); > void dw_pcie_upconfig_setup(struct dw_pcie *pci); > int dw_pcie_wait_for_link(struct dw_pcie *pci); > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, > - u64 cpu_addr, u64 pci_addr, u64 size); > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, > - int type, u64 cpu_addr, u64 pci_addr, u64 size); > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, > + const struct dw_pcie_ob_atu_cfg *atu); > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, > u64 cpu_addr, u64 pci_addr, u64 size); > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, > -- > 2.25.1 >