From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from hall.aurel32.net (hall.aurel32.net [195.154.113.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C69D4F213; Tue, 27 Feb 2024 18:07:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.154.113.88 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709057234; cv=none; b=YR4LvseAwm8/o62KwkXsOk+WM8ddopUl3Y1txZ+i5S7kbqL2cWe1R++GJscIQPbeIa41/LAY03y3EAF2RAYQIDY4EiouRvHl4t3aB7W8f7ovMz2g+c1en5AyOIfvAt7qG5AgSKwpxEvGRVtwMdyzBTOeaypsEnNexTkxekicOSc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709057234; c=relaxed/simple; bh=EDGc4T90gSY2gzBl84gNJRzHa6ffsk6idxwQzqrzpco=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=lVbd44uRf5gL3rM/0xLjaxLli2K/iBeRwe0R5kL51VQuyykEHbgpGt+jh6yOBpLWc4clQXncLAN121Jqb4QS+AmdwbjVEXCGk44uUKjcpAudmQeRzopnqpMfTNJRdOstmQXJZhp9pktK/mi5H5VVACgjVJFjCNm4xXUm2G49tsk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=aurel32.net; spf=pass smtp.mailfrom=aurel32.net; dkim=pass (2048-bit key) header.d=aurel32.net header.i=@aurel32.net header.b=B7+p+wRe; arc=none smtp.client-ip=195.154.113.88 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=aurel32.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aurel32.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=aurel32.net header.i=@aurel32.net header.b="B7+p+wRe" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=In-Reply-To:Content-Type:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Content-Transfer-Encoding:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=cCXTnPPUlwvk/cW+Q4SojvQKobQ4NrfAODoD6AwFqkE=; b=B7+p+wReujVPyD97CCYJ3zpaa4 x2kte552EqPOHJrblcwDoKNvonak17Y34QCJkH0Y3z1Yxv/h35uaYjeMHX1Mgxx/jMeXGXgYRLBBB kGQ0ugTuhcRwwL+3DARJaYzlL04zk5WS1pJpP/vpqymTC5QXv3hluQ1owY0Wnv7qXcKAPXXg0U3K/ fswEK8jf+r5mmH0LfYVPmLKfjE4q+MZWC5UzD8PGvFXcQbDm5kNfky7mP41n9yNU9R0SrK6vOyb7s 7ERL+dqalYI2mOBehgZbarvMzJf8SW/4bpY/ymOKkTcUBUaPMFZ4Y3hoG9jLdkg7Er/4RpTneR7DA 83MOZJ3Q==; Received: from ohm.aurel32.net ([2001:bc8:30d7:111::2] helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1rf1qt-005Xko-1r; Tue, 27 Feb 2024 19:06:51 +0100 Date: Tue, 27 Feb 2024 19:06:50 +0100 From: Aurelien Jarno To: Minda Chen Cc: Conor Dooley , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Thomas Gleixner , Daire McNamara , Emil Renner Berthing , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie Subject: Re: [PATCH v15,RESEND 00/23] Refactoring Microchip PCIe driver and add StarFive PCIe Message-ID: Mail-Followup-To: Minda Chen , Conor Dooley , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Thomas Gleixner , Daire McNamara , Emil Renner Berthing , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie References: <20240227103522.80915-1-minda.chen@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240227103522.80915-1-minda.chen@starfivetech.com> User-Agent: Mutt/2.2.12 (2023-09-09) On 2024-02-27 18:34, Minda Chen wrote: > This patchset final purpose is add PCIe driver for StarFive JH7110 SoC. > JH7110 using PLDA XpressRICH PCIe IP. Microchip PolarFire Using the > same IP and have commit their codes, which are mixed with PLDA > controller codes and Microchip platform codes. > > For re-use the PLDA controller codes, I request refactoring microchip > codes, move PLDA common codes to PLDA files. > Desigware and Cadence is good example for refactoring codes. > Thanks for the resend, I confirm that now the mail threading is correct. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net