* [PATCH 1/2] arm64: dts: imx8dxl: add fsl-dma.h dt-binding header file @ 2024-01-29 20:16 Frank Li 2024-01-29 20:16 ` [PATCH 2/2] arm64: dts: imx8dxl update edma0 information Frank Li 2024-02-23 1:56 ` [PATCH 1/2] arm64: dts: imx8dxl: add fsl-dma.h dt-binding header file Shawn Guo 0 siblings, 2 replies; 5+ messages in thread From: Frank Li @ 2024-01-29 20:16 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list Cc: imx Add fsl-dma.h dt-binding header file in imx8dxl chip dtsi file. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index f580eb6db9a61..a0674c5c55766 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/imx8-clock.h> +#include <dt-bindings/dma/fsl-edma.h> #include <dt-bindings/firmware/imx/rsrc.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -- 2.34.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] arm64: dts: imx8dxl update edma0 information 2024-01-29 20:16 [PATCH 1/2] arm64: dts: imx8dxl: add fsl-dma.h dt-binding header file Frank Li @ 2024-01-29 20:16 ` Frank Li 2024-02-06 10:38 ` Shawn Guo 2024-02-23 1:56 ` [PATCH 1/2] arm64: dts: imx8dxl: add fsl-dma.h dt-binding header file Shawn Guo 1 sibling, 1 reply; 5+ messages in thread From: Frank Li @ 2024-01-29 20:16 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list Cc: imx edma0 of iMX8DXL is difference with other imx8 chips. Update register's size, channel number and power-domain. Update i2c[0-3] channel number information. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- .../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi index 0a477f6318f15..f8fca86babda7 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -15,6 +15,63 @@ &adc0 { interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; }; +&edma0 { + reg = <0x591f0000 0x1a0000>; + #dma-cells = <3>; + dma-channels = <25>; + dma-channel-mask = <0x1c0cc0>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */ + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */ + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */ + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */ + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH10>, + <&pd IMX_SC_R_DMA_0_CH11>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH18>, + <&pd IMX_SC_R_DMA_0_CH19>, + <&pd IMX_SC_R_DMA_0_CH20>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH22>, + <&pd IMX_SC_R_DMA_0_CH23>, + <&pd IMX_SC_R_DMA_0_CH24>; +}; + &edma2 { interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, @@ -48,21 +105,29 @@ &edma3 { &i2c0 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + dma-names = "tx","rx"; + dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL_EDMA_RX>; }; &i2c1 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + dma-names = "tx","rx"; + dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL_EDMA_RX>; }; &i2c2 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + dma-names = "tx","rx"; + dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL_EDMA_RX>; }; &i2c3 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + dma-names = "tx","rx"; + dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL_EDMA_RX>; }; &lpuart0 { -- 2.34.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] arm64: dts: imx8dxl update edma0 information 2024-01-29 20:16 ` [PATCH 2/2] arm64: dts: imx8dxl update edma0 information Frank Li @ 2024-02-06 10:38 ` Shawn Guo 2024-02-06 15:24 ` Frank Li 0 siblings, 1 reply; 5+ messages in thread From: Shawn Guo @ 2024-02-06 10:38 UTC (permalink / raw) To: Frank Li Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list, imx On Mon, Jan 29, 2024 at 03:16:32PM -0500, Frank Li wrote: > edma0 of iMX8DXL is difference with other imx8 chips. Update register's > size, channel number and power-domain. > Update i2c[0-3] channel number information. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > .../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 65 +++++++++++++++++++ > 1 file changed, 65 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi > index 0a477f6318f15..f8fca86babda7 100644 > --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi > @@ -15,6 +15,63 @@ &adc0 { > interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; > }; > > +&edma0 { > + reg = <0x591f0000 0x1a0000>; > + #dma-cells = <3>; > + dma-channels = <25>; > + dma-channel-mask = <0x1c0cc0>; > + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ > + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ > + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ > + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ > + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */ > + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */ > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */ > + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */ > + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */ > + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */ > + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, > + <&pd IMX_SC_R_DMA_0_CH1>, > + <&pd IMX_SC_R_DMA_0_CH2>, > + <&pd IMX_SC_R_DMA_0_CH3>, > + <&pd IMX_SC_R_DMA_0_CH4>, > + <&pd IMX_SC_R_DMA_0_CH5>, > + <&pd IMX_SC_R_DMA_0_CH6>, > + <&pd IMX_SC_R_DMA_0_CH7>, > + <&pd IMX_SC_R_DMA_0_CH8>, > + <&pd IMX_SC_R_DMA_0_CH9>, > + <&pd IMX_SC_R_DMA_0_CH10>, > + <&pd IMX_SC_R_DMA_0_CH11>, > + <&pd IMX_SC_R_DMA_0_CH12>, > + <&pd IMX_SC_R_DMA_0_CH13>, > + <&pd IMX_SC_R_DMA_0_CH14>, > + <&pd IMX_SC_R_DMA_0_CH15>, > + <&pd IMX_SC_R_DMA_0_CH16>, > + <&pd IMX_SC_R_DMA_0_CH17>, > + <&pd IMX_SC_R_DMA_0_CH18>, > + <&pd IMX_SC_R_DMA_0_CH19>, > + <&pd IMX_SC_R_DMA_0_CH20>, > + <&pd IMX_SC_R_DMA_0_CH21>, > + <&pd IMX_SC_R_DMA_0_CH22>, > + <&pd IMX_SC_R_DMA_0_CH23>, > + <&pd IMX_SC_R_DMA_0_CH24>; > +}; > + > &edma2 { > interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, > @@ -48,21 +105,29 @@ &edma3 { > &i2c0 { > compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; > interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; > + dma-names = "tx","rx"; > + dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL_EDMA_RX>; > }; > > &i2c1 { > compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; > interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; > + dma-names = "tx","rx"; > + dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL_EDMA_RX>; No FSL_EDMA_TX for "tx"? Shawn > }; > > &i2c2 { > compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; > interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; > + dma-names = "tx","rx"; > + dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL_EDMA_RX>; > }; > > &i2c3 { > compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; > interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; > + dma-names = "tx","rx"; > + dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL_EDMA_RX>; > }; > > &lpuart0 { > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] arm64: dts: imx8dxl update edma0 information 2024-02-06 10:38 ` Shawn Guo @ 2024-02-06 15:24 ` Frank Li 0 siblings, 0 replies; 5+ messages in thread From: Frank Li @ 2024-02-06 15:24 UTC (permalink / raw) To: Shawn Guo Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list, imx On Tue, Feb 06, 2024 at 06:38:29PM +0800, Shawn Guo wrote: > On Mon, Jan 29, 2024 at 03:16:32PM -0500, Frank Li wrote: > > edma0 of iMX8DXL is difference with other imx8 chips. Update register's > > size, channel number and power-domain. > > Update i2c[0-3] channel number information. > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > .../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 65 +++++++++++++++++++ > > 1 file changed, 65 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi > > index 0a477f6318f15..f8fca86babda7 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi > > @@ -15,6 +15,63 @@ &adc0 { > > interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; > > }; > > > > +&edma0 { > > + reg = <0x591f0000 0x1a0000>; > > + #dma-cells = <3>; > > + dma-channels = <25>; > > + dma-channel-mask = <0x1c0cc0>; > > + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ > > + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ > > + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ > > + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ > > + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */ > > + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */ > > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */ > > + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */ > > + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */ > > + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */ > > + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, > > + <&pd IMX_SC_R_DMA_0_CH1>, > > + <&pd IMX_SC_R_DMA_0_CH2>, > > + <&pd IMX_SC_R_DMA_0_CH3>, > > + <&pd IMX_SC_R_DMA_0_CH4>, > > + <&pd IMX_SC_R_DMA_0_CH5>, > > + <&pd IMX_SC_R_DMA_0_CH6>, > > + <&pd IMX_SC_R_DMA_0_CH7>, > > + <&pd IMX_SC_R_DMA_0_CH8>, > > + <&pd IMX_SC_R_DMA_0_CH9>, > > + <&pd IMX_SC_R_DMA_0_CH10>, > > + <&pd IMX_SC_R_DMA_0_CH11>, > > + <&pd IMX_SC_R_DMA_0_CH12>, > > + <&pd IMX_SC_R_DMA_0_CH13>, > > + <&pd IMX_SC_R_DMA_0_CH14>, > > + <&pd IMX_SC_R_DMA_0_CH15>, > > + <&pd IMX_SC_R_DMA_0_CH16>, > > + <&pd IMX_SC_R_DMA_0_CH17>, > > + <&pd IMX_SC_R_DMA_0_CH18>, > > + <&pd IMX_SC_R_DMA_0_CH19>, > > + <&pd IMX_SC_R_DMA_0_CH20>, > > + <&pd IMX_SC_R_DMA_0_CH21>, > > + <&pd IMX_SC_R_DMA_0_CH22>, > > + <&pd IMX_SC_R_DMA_0_CH23>, > > + <&pd IMX_SC_R_DMA_0_CH24>; > > +}; > > + > > &edma2 { > > interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, > > <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, > > @@ -48,21 +105,29 @@ &edma3 { > > &i2c0 { > > compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; > > interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; > > + dma-names = "tx","rx"; > > + dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL_EDMA_RX>; > > }; > > > > &i2c1 { > > compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; > > interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; > > + dma-names = "tx","rx"; > > + dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL_EDMA_RX>; > > No FSL_EDMA_TX for "tx"? Yes, only defined FSL_EDMA_RX. It is bitmask. If no FSL_EDMA_RX, means TX channel. Frank > > Shawn > > > }; > > > > &i2c2 { > > compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; > > interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; > > + dma-names = "tx","rx"; > > + dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL_EDMA_RX>; > > }; > > > > &i2c3 { > > compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; > > interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; > > + dma-names = "tx","rx"; > > + dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL_EDMA_RX>; > > }; > > > > &lpuart0 { > > -- > > 2.34.1 > > > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] arm64: dts: imx8dxl: add fsl-dma.h dt-binding header file 2024-01-29 20:16 [PATCH 1/2] arm64: dts: imx8dxl: add fsl-dma.h dt-binding header file Frank Li 2024-01-29 20:16 ` [PATCH 2/2] arm64: dts: imx8dxl update edma0 information Frank Li @ 2024-02-23 1:56 ` Shawn Guo 1 sibling, 0 replies; 5+ messages in thread From: Shawn Guo @ 2024-02-23 1:56 UTC (permalink / raw) To: Frank Li Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list, imx On Mon, Jan 29, 2024 at 03:16:31PM -0500, Frank Li wrote: > Add fsl-dma.h dt-binding header file in imx8dxl chip dtsi file. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> Applied both, thanks! ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-02-23 1:57 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-01-29 20:16 [PATCH 1/2] arm64: dts: imx8dxl: add fsl-dma.h dt-binding header file Frank Li 2024-01-29 20:16 ` [PATCH 2/2] arm64: dts: imx8dxl update edma0 information Frank Li 2024-02-06 10:38 ` Shawn Guo 2024-02-06 15:24 ` Frank Li 2024-02-23 1:56 ` [PATCH 1/2] arm64: dts: imx8dxl: add fsl-dma.h dt-binding header file Shawn Guo
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