[PATCH v2 0/2] add uSDHC and SCMI nodes to the S32G2 SoC

[PATCH v2 0/2] add uSDHC and SCMI nodes to the S32G2 SoC

[Ghennadi Procopciuc]

From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

This patchset adds device tree support for S32G2 SCMI firmware and uSDHC
node. The SCMI clock IDs are based on a downstream version of the TF-A
stored on GitHub [0].

I can send the patches individually if you prefer that instead of
submitting them all at once.??

[0] https://github.com/nxp-auto-linux/arm-trusted-firmware

Changes in v2:
 - The SCMI clock bindings header has been removed.

Ghennadi Procopciuc (2):
  arm64: dts: s32g: add SCMI firmware node
  arm64: dts: s32g: add uSDHC node

 arch/arm64/boot/dts/freescale/s32g2.dtsi      | 37 ++++++++++++++++++-
 .../arm64/boot/dts/freescale/s32g274a-evb.dts |  6 ++-
 .../boot/dts/freescale/s32g274a-rdb2.dts      |  6 ++-
 3 files changed, 46 insertions(+), 3 deletions(-)

-- 
2.43.0

[PATCH v2 1/2] arm64: dts: s32g: add SCMI firmware node

[Ghennadi Procopciuc]

From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

Linux controls the clocks over SCMI on S32G SoCs. Therefore,
add the SCMI device tree node and the reserved region for SCMI
messages.

Signed-off-by: Catalin Udma <catalin-dan.udma@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi | 27 +++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 5ac1cc9ff50e..ef1a1d61f2ba 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,7 +3,7 @@
  * NXP S32G2 SoC family
  *
  * Copyright (c) 2021 SUSE LLC
- * Copyright (c) 2017-2021 NXP
+ * Copyright 2017-2021, 2024 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -14,6 +14,18 @@ / {
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	reserved-memory  {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		scmi_buf: shm@d0000000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x0 0xd0000000 0x0 0x80>;
+			no-map;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -77,6 +89,19 @@ timer {
 	};
 
 	firmware {
+		scmi {
+			compatible = "arm,scmi-smc";
+			arm,smc-id = <0xc20000fe>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			shmem = <&scmi_buf>;
+
+			clks: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+		};
+
 		psci {
 			compatible = "arm,psci-1.0";
 			method = "smc";
-- 
2.43.0

[PATCH v2 2/2] arm64: dts: s32g: add uSDHC node

[Ghennadi Procopciuc]

From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

Add the uSDHC node for the boards that are based on S32G SoCs.

Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi        | 10 ++++++++++
 arch/arm64/boot/dts/freescale/s32g274a-evb.dts  |  6 +++++-
 arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts |  6 +++++-
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index ef1a1d61f2ba..fc19ae2e8d3b 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -138,6 +138,16 @@ uart2: serial@402bc000 {
 			status = "disabled";
 		};
 
+		usdhc0: mmc@402f0000 {
+			compatible = "nxp,s32g2-usdhc";
+			reg = <0x402f0000 0x1000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks 32>, <&clks 31>, <&clks 33>;
+			clock-names = "ipg", "ahb", "per";
+			bus-width = <8>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@50800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x50800000 0x10000>,
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
index 9118d8d2ee01..00070c949e2a 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright (c) 2021 SUSE LLC
- * Copyright (c) 2019-2021 NXP
+ * Copyright 2019-2021, 2024 NXP
  */
 
 /dts-v1/;
@@ -32,3 +32,7 @@ memory@80000000 {
 &uart0 {
 	status = "okay";
 };
+
+&usdhc0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
index e05ee854cdf5..b3fc12899cae 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright (c) 2021 SUSE LLC
- * Copyright (c) 2019-2021 NXP
+ * Copyright 2019-2021, 2024 NXP
  */
 
 /dts-v1/;
@@ -38,3 +38,7 @@ &uart0 {
 &uart1 {
 	status = "okay";
 };
+
+&usdhc0 {
+	status = "okay";
+};
-- 
2.43.0

Re: [PATCH v2 1/2] arm64: dts: s32g: add SCMI firmware node

[Matthias Brugger]

On 22/01/2024 15:06, Ghennadi Procopciuc wrote:
> From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> 
> Linux controls the clocks over SCMI on S32G SoCs. Therefore,
> add the SCMI device tree node and the reserved region for SCMI
> messages.
> 
> Signed-off-by: Catalin Udma <catalin-dan.udma@nxp.com>
> Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

Reviewed-by: Matthias Brugger <mbrugger@suse.com>

> ---
>   arch/arm64/boot/dts/freescale/s32g2.dtsi | 27 +++++++++++++++++++++++-
>   1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 5ac1cc9ff50e..ef1a1d61f2ba 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -3,7 +3,7 @@
>    * NXP S32G2 SoC family
>    *
>    * Copyright (c) 2021 SUSE LLC
> - * Copyright (c) 2017-2021 NXP
> + * Copyright 2017-2021, 2024 NXP
>    */
>   
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -14,6 +14,18 @@ / {
>   	#address-cells = <2>;
>   	#size-cells = <2>;
>   
> +	reserved-memory  {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		scmi_buf: shm@d0000000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0x0 0xd0000000 0x0 0x80>;
> +			no-map;
> +		};
> +	};
> +
>   	cpus {
>   		#address-cells = <1>;
>   		#size-cells = <0>;
> @@ -77,6 +89,19 @@ timer {
>   	};
>   
>   	firmware {
> +		scmi {
> +			compatible = "arm,scmi-smc";
> +			arm,smc-id = <0xc20000fe>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			shmem = <&scmi_buf>;
> +
> +			clks: protocol@14 {
> +				reg = <0x14>;
> +				#clock-cells = <1>;
> +			};
> +		};
> +
>   		psci {
>   			compatible = "arm,psci-1.0";
>   			method = "smc";

Re: [PATCH v2 2/2] arm64: dts: s32g: add uSDHC node

[Matthias Brugger]

On 22/01/2024 15:06, Ghennadi Procopciuc wrote:
> From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> 
> Add the uSDHC node for the boards that are based on S32G SoCs.
> 
> Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
> Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

Reviewed-by: Matthias Brugger <mbrugger@suse.com>

> ---
>   arch/arm64/boot/dts/freescale/s32g2.dtsi        | 10 ++++++++++
>   arch/arm64/boot/dts/freescale/s32g274a-evb.dts  |  6 +++++-
>   arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts |  6 +++++-
>   3 files changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index ef1a1d61f2ba..fc19ae2e8d3b 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -138,6 +138,16 @@ uart2: serial@402bc000 {
>   			status = "disabled";
>   		};
>   
> +		usdhc0: mmc@402f0000 {
> +			compatible = "nxp,s32g2-usdhc";
> +			reg = <0x402f0000 0x1000>;
> +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks 32>, <&clks 31>, <&clks 33>;
> +			clock-names = "ipg", "ahb", "per";
> +			bus-width = <8>;
> +			status = "disabled";
> +		};
> +
>   		gic: interrupt-controller@50800000 {
>   			compatible = "arm,gic-v3";
>   			reg = <0x50800000 0x10000>,
> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> index 9118d8d2ee01..00070c949e2a 100644
> --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> @@ -1,7 +1,7 @@
>   // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
>   /*
>    * Copyright (c) 2021 SUSE LLC
> - * Copyright (c) 2019-2021 NXP
> + * Copyright 2019-2021, 2024 NXP
>    */
>   
>   /dts-v1/;
> @@ -32,3 +32,7 @@ memory@80000000 {
>   &uart0 {
>   	status = "okay";
>   };
> +
> +&usdhc0 {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> index e05ee854cdf5..b3fc12899cae 100644
> --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> @@ -1,7 +1,7 @@
>   // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
>   /*
>    * Copyright (c) 2021 SUSE LLC
> - * Copyright (c) 2019-2021 NXP
> + * Copyright 2019-2021, 2024 NXP
>    */
>   
>   /dts-v1/;
> @@ -38,3 +38,7 @@ &uart0 {
>   &uart1 {
>   	status = "okay";
>   };
> +
> +&usdhc0 {
> +	status = "okay";
> +};

Re: [PATCH v2 0/2] add uSDHC and SCMI nodes to the S32G2 SoC

[Ghennadi Procopciuc]

On 1/22/24 16:05, Ghennadi Procopciuc wrote:
> From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> 
> This patchset adds device tree support for S32G2 SCMI firmware and uSDHC
> node. The SCMI clock IDs are based on a downstream version of the TF-A
> stored on GitHub [0].
> 
> I can send the patches individually if you prefer that instead of
> submitting them all at once.??
> 
> [0] https://github.com/nxp-auto-linux/arm-trusted-firmware
> 
> Changes in v2:
>  - The SCMI clock bindings header has been removed.
> 
> Ghennadi Procopciuc (2):
>   arm64: dts: s32g: add SCMI firmware node
>   arm64: dts: s32g: add uSDHC node
> 
>  arch/arm64/boot/dts/freescale/s32g2.dtsi      | 37 ++++++++++++++++++-
>  .../arm64/boot/dts/freescale/s32g274a-evb.dts |  6 ++-
>  .../boot/dts/freescale/s32g274a-rdb2.dts      |  6 ++-
>  3 files changed, 46 insertions(+), 3 deletions(-)
> 
Hi Chester,

I want to confirm if you are open to accepting the proposed changes for
ARM/NXP S32G architecture, given your maintainer role. Please let me
know if any revisions or adaptations are required.

Regards,
Ghennadi

Re: [PATCH v2 1/2] arm64: dts: s32g: add SCMI firmware node

[Chester Lin]

Hi Ghennadi,

On Mon, Jan 22, 2024 at 03:39:09PM +0100, Matthias Brugger wrote:
> 
> 
> On 22/01/2024 15:06, Ghennadi Procopciuc wrote:
> > From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> > 
> > Linux controls the clocks over SCMI on S32G SoCs. Therefore,
> > add the SCMI device tree node and the reserved region for SCMI

Is there any dt-binding required to match the SCMI clock IDs declared in
SCMI? I assume that s32g series will need fixed dt-bindings for clocks to make
sure there will be no kabi issue in the future.

Thanks,
Chester

> > messages.
> > 
> > Signed-off-by: Catalin Udma <catalin-dan.udma@nxp.com>
> > Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> 
> Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> 
> > ---
> >   arch/arm64/boot/dts/freescale/s32g2.dtsi | 27 +++++++++++++++++++++++-
> >   1 file changed, 26 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > index 5ac1cc9ff50e..ef1a1d61f2ba 100644
> > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > @@ -3,7 +3,7 @@
> >    * NXP S32G2 SoC family
> >    *
> >    * Copyright (c) 2021 SUSE LLC
> > - * Copyright (c) 2017-2021 NXP
> > + * Copyright 2017-2021, 2024 NXP
> >    */
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> > @@ -14,6 +14,18 @@ / {
> >   	#address-cells = <2>;
> >   	#size-cells = <2>;
> > +	reserved-memory  {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		scmi_buf: shm@d0000000 {
> > +			compatible = "arm,scmi-shmem";
> > +			reg = <0x0 0xd0000000 0x0 0x80>;
> > +			no-map;
> > +		};
> > +	};
> > +
> >   	cpus {
> >   		#address-cells = <1>;
> >   		#size-cells = <0>;
> > @@ -77,6 +89,19 @@ timer {
> >   	};
> >   	firmware {
> > +		scmi {
> > +			compatible = "arm,scmi-smc";
> > +			arm,smc-id = <0xc20000fe>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			shmem = <&scmi_buf>;
> > +
> > +			clks: protocol@14 {
> > +				reg = <0x14>;
> > +				#clock-cells = <1>;
> > +			};
> > +		};
> > +
> >   		psci {
> >   			compatible = "arm,psci-1.0";
> >   			method = "smc";

Re: [PATCH v2 2/2] arm64: dts: s32g: add uSDHC node

[Chester Lin]

Hi Ghennadi,

On Mon, Jan 22, 2024 at 04:06:01PM +0200, Ghennadi Procopciuc wrote:
> From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> 
> Add the uSDHC node for the boards that are based on S32G SoCs.
> 
> Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
> Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/s32g2.dtsi        | 10 ++++++++++
>  arch/arm64/boot/dts/freescale/s32g274a-evb.dts  |  6 +++++-
>  arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts |  6 +++++-
>  3 files changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index ef1a1d61f2ba..fc19ae2e8d3b 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -138,6 +138,16 @@ uart2: serial@402bc000 {
>  			status = "disabled";
>  		};
>  
> +		usdhc0: mmc@402f0000 {
> +			compatible = "nxp,s32g2-usdhc";
> +			reg = <0x402f0000 0x1000>;
> +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks 32>, <&clks 31>, <&clks 33>;

Same as I have mentioned in [PATCH v2 1/2], could we have fixed dt-bindings to
replace with these raw clock id values (32, 31, 33)?

Chester
> +			clock-names = "ipg", "ahb", "per";
> +			bus-width = <8>;
> +			status = "disabled";
> +		};
> +
>  		gic: interrupt-controller@50800000 {
>  			compatible = "arm,gic-v3";
>  			reg = <0x50800000 0x10000>,
> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> index 9118d8d2ee01..00070c949e2a 100644
> --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> @@ -1,7 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
>  /*
>   * Copyright (c) 2021 SUSE LLC
> - * Copyright (c) 2019-2021 NXP
> + * Copyright 2019-2021, 2024 NXP
>   */
>  
>  /dts-v1/;
> @@ -32,3 +32,7 @@ memory@80000000 {
>  &uart0 {
>  	status = "okay";
>  };
> +
> +&usdhc0 {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> index e05ee854cdf5..b3fc12899cae 100644
> --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> @@ -1,7 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
>  /*
>   * Copyright (c) 2021 SUSE LLC
> - * Copyright (c) 2019-2021 NXP
> + * Copyright 2019-2021, 2024 NXP
>   */
>  
>  /dts-v1/;
> @@ -38,3 +38,7 @@ &uart0 {
>  &uart1 {
>  	status = "okay";
>  };
> +
> +&usdhc0 {
> +	status = "okay";
> +};
> -- 
> 2.43.0
> 

Re: [PATCH v2 2/2] arm64: dts: s32g: add uSDHC node

[Chester Lin]

Hi Ghennadi,

On Sat, Feb 24, 2024 at 04:22:30PM +0800, Chester Lin wrote:
> Hi Ghennadi,
> 
> On Mon, Jan 22, 2024 at 04:06:01PM +0200, Ghennadi Procopciuc wrote:
> > From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> > 
> > Add the uSDHC node for the boards that are based on S32G SoCs.
> > 
> > Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
> > Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/s32g2.dtsi        | 10 ++++++++++
> >  arch/arm64/boot/dts/freescale/s32g274a-evb.dts  |  6 +++++-
> >  arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts |  6 +++++-
> >  3 files changed, 20 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > index ef1a1d61f2ba..fc19ae2e8d3b 100644
> > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > @@ -138,6 +138,16 @@ uart2: serial@402bc000 {
> >  			status = "disabled";
> >  		};
> >  
> > +		usdhc0: mmc@402f0000 {
> > +			compatible = "nxp,s32g2-usdhc";
> > +			reg = <0x402f0000 0x1000>;
> > +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&clks 32>, <&clks 31>, <&clks 33>;
> 
> Same as I have mentioned in [PATCH v2 1/2], could we have fixed dt-bindings to
> replace with these raw clock id values (32, 31, 33)?
> 

Just found the previous review discussion in v1:
https://lore.kernel.org/all/f54d947c-58dc-498f-8871-b472f97be4a8@oss.nxp.com/

What I'm worried is that, could these raw clock IDs be rearranged in the
downstream TF-A? If so it would cause ABI inconsistency and clock issues
since the kernel is not aware of any raw ID changes in downstream TF-A.

Chester

> > +			clock-names = "ipg", "ahb", "per";
> > +			bus-width = <8>;
> > +			status = "disabled";
> > +		};
> > +
> >  		gic: interrupt-controller@50800000 {
> >  			compatible = "arm,gic-v3";
> >  			reg = <0x50800000 0x10000>,
> > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> > index 9118d8d2ee01..00070c949e2a 100644
> > --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> > +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> > @@ -1,7 +1,7 @@
> >  // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> >  /*
> >   * Copyright (c) 2021 SUSE LLC
> > - * Copyright (c) 2019-2021 NXP
> > + * Copyright 2019-2021, 2024 NXP
> >   */
> >  
> >  /dts-v1/;
> > @@ -32,3 +32,7 @@ memory@80000000 {
> >  &uart0 {
> >  	status = "okay";
> >  };
> > +
> > +&usdhc0 {
> > +	status = "okay";
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> > index e05ee854cdf5..b3fc12899cae 100644
> > --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> > +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> > @@ -1,7 +1,7 @@
> >  // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> >  /*
> >   * Copyright (c) 2021 SUSE LLC
> > - * Copyright (c) 2019-2021 NXP
> > + * Copyright 2019-2021, 2024 NXP
> >   */
> >  
> >  /dts-v1/;
> > @@ -38,3 +38,7 @@ &uart0 {
> >  &uart1 {
> >  	status = "okay";
> >  };
> > +
> > +&usdhc0 {
> > +	status = "okay";
> > +};
> > -- 
> > 2.43.0
> > 

Re: [PATCH v2 2/2] arm64: dts: s32g: add uSDHC node

[Ghennadi Procopciuc]

On 2/24/24 12:44, Chester Lin wrote:
> Hi Ghennadi,
> 
> On Sat, Feb 24, 2024 at 04:22:30PM +0800, Chester Lin wrote:
>> Hi Ghennadi,

Hi Chester,
>>
>> On Mon, Jan 22, 2024 at 04:06:01PM +0200, Ghennadi Procopciuc wrote:
>>> From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
>>>
>>> Add the uSDHC node for the boards that are based on S32G SoCs.
>>>
>>> Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
>>> Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
>>> ---
>>>  arch/arm64/boot/dts/freescale/s32g2.dtsi        | 10 ++++++++++
>>>  arch/arm64/boot/dts/freescale/s32g274a-evb.dts  |  6 +++++-
>>>  arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts |  6 +++++-
>>>  3 files changed, 20 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>>> index ef1a1d61f2ba..fc19ae2e8d3b 100644
>>> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
>>> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
>>> @@ -138,6 +138,16 @@ uart2: serial@402bc000 {
>>>  			status = "disabled";
>>>  		};
>>>  
>>> +		usdhc0: mmc@402f0000 {
>>> +			compatible = "nxp,s32g2-usdhc";
>>> +			reg = <0x402f0000 0x1000>;
>>> +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
>>> +			clocks = <&clks 32>, <&clks 31>, <&clks 33>;
>>
>> Same as I have mentioned in [PATCH v2 1/2], could we have fixed dt-bindings to
>> replace with these raw clock id values (32, 31, 33)?
>>
> 
> Just found the previous review discussion in v1:
> https://lore.kernel.org/all/f54d947c-58dc-498f-8871-b472f97be4a8@oss.nxp.com/
> 
Indeed, I switched to raw clocks instead of placing them into a binding
header after receiving this feedback on v1.

> What I'm worried is that, could these raw clock IDs be rearranged in the
> downstream TF-A? If so it would cause ABI inconsistency and clock issues
> since the kernel is not aware of any raw ID changes in downstream TF-A.

These clock IDs will become immutable in the downstream version of TF-A
once the patches get merged. This will prevent any unfortunate events
when the Kernel and TF-A are not in sync with regard to SCMI clock IDs.

Best regards,
Ghennadi
> 
> Chester
> 
>>> +			clock-names = "ipg", "ahb", "per";
>>> +			bus-width = <8>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>>  		gic: interrupt-controller@50800000 {
>>>  			compatible = "arm,gic-v3";
>>>  			reg = <0x50800000 0x10000>,
>>> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
>>> index 9118d8d2ee01..00070c949e2a 100644
>>> --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
>>> +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
>>> @@ -1,7 +1,7 @@
>>>  // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
>>>  /*
>>>   * Copyright (c) 2021 SUSE LLC
>>> - * Copyright (c) 2019-2021 NXP
>>> + * Copyright 2019-2021, 2024 NXP
>>>   */
>>>  
>>>  /dts-v1/;
>>> @@ -32,3 +32,7 @@ memory@80000000 {
>>>  &uart0 {
>>>  	status = "okay";
>>>  };
>>> +
>>> +&usdhc0 {
>>> +	status = "okay";
>>> +};
>>> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
>>> index e05ee854cdf5..b3fc12899cae 100644
>>> --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
>>> +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
>>> @@ -1,7 +1,7 @@
>>>  // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
>>>  /*
>>>   * Copyright (c) 2021 SUSE LLC
>>> - * Copyright (c) 2019-2021 NXP
>>> + * Copyright 2019-2021, 2024 NXP
>>>   */
>>>  
>>>  /dts-v1/;
>>> @@ -38,3 +38,7 @@ &uart0 {
>>>  &uart1 {
>>>  	status = "okay";
>>>  };
>>> +
>>> +&usdhc0 {
>>> +	status = "okay";
>>> +};
>>> -- 
>>> 2.43.0
>>>

-- 
Regards,
Ghennadi

Re: [PATCH v2 2/2] arm64: dts: s32g: add uSDHC node

[Chester Lin]

On Mon, Feb 26, 2024 at 08:29:31AM +0200, Ghennadi Procopciuc wrote:
> On 2/24/24 12:44, Chester Lin wrote:
> > Hi Ghennadi,
> > 
> > On Sat, Feb 24, 2024 at 04:22:30PM +0800, Chester Lin wrote:
> >> Hi Ghennadi,
> 
> Hi Chester,
> >>
> >> On Mon, Jan 22, 2024 at 04:06:01PM +0200, Ghennadi Procopciuc wrote:
> >>> From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> >>>
> >>> Add the uSDHC node for the boards that are based on S32G SoCs.
> >>>
> >>> Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
> >>> Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> >>> ---
> >>>  arch/arm64/boot/dts/freescale/s32g2.dtsi        | 10 ++++++++++
> >>>  arch/arm64/boot/dts/freescale/s32g274a-evb.dts  |  6 +++++-
> >>>  arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts |  6 +++++-
> >>>  3 files changed, 20 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> >>> index ef1a1d61f2ba..fc19ae2e8d3b 100644
> >>> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> >>> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> >>> @@ -138,6 +138,16 @@ uart2: serial@402bc000 {
> >>>  			status = "disabled";
> >>>  		};
> >>>  
> >>> +		usdhc0: mmc@402f0000 {
> >>> +			compatible = "nxp,s32g2-usdhc";
> >>> +			reg = <0x402f0000 0x1000>;
> >>> +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> >>> +			clocks = <&clks 32>, <&clks 31>, <&clks 33>;
> >>
> >> Same as I have mentioned in [PATCH v2 1/2], could we have fixed dt-bindings to
> >> replace with these raw clock id values (32, 31, 33)?
> >>
> > 
> > Just found the previous review discussion in v1:
> > https://lore.kernel.org/all/f54d947c-58dc-498f-8871-b472f97be4a8@oss.nxp.com/
> > 
> Indeed, I switched to raw clocks instead of placing them into a binding
> header after receiving this feedback on v1.
> 
> > What I'm worried is that, could these raw clock IDs be rearranged in the
> > downstream TF-A? If so it would cause ABI inconsistency and clock issues
> > since the kernel is not aware of any raw ID changes in downstream TF-A.
> 
> These clock IDs will become immutable in the downstream version of TF-A
> once the patches get merged. This will prevent any unfortunate events
> when the Kernel and TF-A are not in sync with regard to SCMI clock IDs.
> 
> Best regards,
> Ghennadi

Thanks for explanation.

Reviewed-by: Chester Lin <chester62515@gmail.com>

> > 
> > Chester
> > 
> >>> +			clock-names = "ipg", "ahb", "per";
> >>> +			bus-width = <8>;
> >>> +			status = "disabled";
> >>> +		};
> >>> +
> >>>  		gic: interrupt-controller@50800000 {
> >>>  			compatible = "arm,gic-v3";
> >>>  			reg = <0x50800000 0x10000>,
> >>> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> >>> index 9118d8d2ee01..00070c949e2a 100644
> >>> --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> >>> +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> >>> @@ -1,7 +1,7 @@
> >>>  // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> >>>  /*
> >>>   * Copyright (c) 2021 SUSE LLC
> >>> - * Copyright (c) 2019-2021 NXP
> >>> + * Copyright 2019-2021, 2024 NXP
> >>>   */
> >>>  
> >>>  /dts-v1/;
> >>> @@ -32,3 +32,7 @@ memory@80000000 {
> >>>  &uart0 {
> >>>  	status = "okay";
> >>>  };
> >>> +
> >>> +&usdhc0 {
> >>> +	status = "okay";
> >>> +};
> >>> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> >>> index e05ee854cdf5..b3fc12899cae 100644
> >>> --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> >>> +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> >>> @@ -1,7 +1,7 @@
> >>>  // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> >>>  /*
> >>>   * Copyright (c) 2021 SUSE LLC
> >>> - * Copyright (c) 2019-2021 NXP
> >>> + * Copyright 2019-2021, 2024 NXP
> >>>   */
> >>>  
> >>>  /dts-v1/;
> >>> @@ -38,3 +38,7 @@ &uart0 {
> >>>  &uart1 {
> >>>  	status = "okay";
> >>>  };
> >>> +
> >>> +&usdhc0 {
> >>> +	status = "okay";
> >>> +};
> >>> -- 
> >>> 2.43.0
> >>>
> 
> -- 
> Regards,
> Ghennadi
> 

Re: [PATCH v2 1/2] arm64: dts: s32g: add SCMI firmware node

[Chester Lin]

On Mon, Jan 22, 2024 at 03:39:09PM +0100, Matthias Brugger wrote:
> 
> 
> On 22/01/2024 15:06, Ghennadi Procopciuc wrote:
> > From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> > 
> > Linux controls the clocks over SCMI on S32G SoCs. Therefore,
> > add the SCMI device tree node and the reserved region for SCMI
> > messages.
> > 
> > Signed-off-by: Catalin Udma <catalin-dan.udma@nxp.com>
> > Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> 
> Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> 
> > ---
> >   arch/arm64/boot/dts/freescale/s32g2.dtsi | 27 +++++++++++++++++++++++-
> >   1 file changed, 26 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > index 5ac1cc9ff50e..ef1a1d61f2ba 100644
> > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> > @@ -3,7 +3,7 @@
> >    * NXP S32G2 SoC family
> >    *
> >    * Copyright (c) 2021 SUSE LLC
> > - * Copyright (c) 2017-2021 NXP
> > + * Copyright 2017-2021, 2024 NXP
> >    */
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> > @@ -14,6 +14,18 @@ / {
> >   	#address-cells = <2>;
> >   	#size-cells = <2>;
> > +	reserved-memory  {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		scmi_buf: shm@d0000000 {
> > +			compatible = "arm,scmi-shmem";
> > +			reg = <0x0 0xd0000000 0x0 0x80>;
> > +			no-map;
> > +		};
> > +	};
> > +
> >   	cpus {
> >   		#address-cells = <1>;
> >   		#size-cells = <0>;
> > @@ -77,6 +89,19 @@ timer {
> >   	};
> >   	firmware {
> > +		scmi {
> > +			compatible = "arm,scmi-smc";
> > +			arm,smc-id = <0xc20000fe>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			shmem = <&scmi_buf>;
> > +
> > +			clks: protocol@14 {
> > +				reg = <0x14>;
> > +				#clock-cells = <1>;
> > +			};
> > +		};
> > +
> >   		psci {
> >   			compatible = "arm,psci-1.0";
> >   			method = "smc";

Reviewed-by: Chester Lin <chester62515@gmail.com>

Re: [PATCH v2 0/2] add uSDHC and SCMI nodes to the S32G2 SoC

[Chester Lin]

Hi,

On Thu, Feb 08, 2024 at 11:34:58AM +0200, Ghennadi Procopciuc wrote:
> On 1/22/24 16:05, Ghennadi Procopciuc wrote:
> > From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> > 
> > This patchset adds device tree support for S32G2 SCMI firmware and uSDHC
> > node. The SCMI clock IDs are based on a downstream version of the TF-A
> > stored on GitHub [0].
> > 
> > I can send the patches individually if you prefer that instead of
> > submitting them all at once.??
> > 
> > [0] https://github.com/nxp-auto-linux/arm-trusted-firmware
> > 
> > Changes in v2:
> >  - The SCMI clock bindings header has been removed.
> > 
> > Ghennadi Procopciuc (2):
> >   arm64: dts: s32g: add SCMI firmware node
> >   arm64: dts: s32g: add uSDHC node
> > 
> >  arch/arm64/boot/dts/freescale/s32g2.dtsi      | 37 ++++++++++++++++++-
> >  .../arm64/boot/dts/freescale/s32g274a-evb.dts |  6 ++-
> >  .../boot/dts/freescale/s32g274a-rdb2.dts      |  6 ++-
> >  3 files changed, 46 insertions(+), 3 deletions(-)
> > 
> Hi Chester,
> 
> I want to confirm if you are open to accepting the proposed changes for
> ARM/NXP S32G architecture, given your maintainer role. Please let me
> know if any revisions or adaptations are required.
> 

These patches look good to me.

Hi Shawn,

Per the discussion in another thread, could you help to apply these two
through the imx tree? Thanks!

Chester

> Regards,
> Ghennadi
> 

Re: [PATCH v2 0/2] add uSDHC and SCMI nodes to the S32G2 SoC

[Ghennadi Procopciuc]

On 3/2/24 04:01, Chester Lin wrote:
[...]
> Hi Shawn,
> 
> Per the discussion in another thread, could you help to apply these two
> through the imx tree? Thanks!
> 
> Chester

Hi Shawn,

I noticed that Chester's email was sent to you as a CC recipient, which
may cause it to be filtered out based on your inbox rules. This is why I
wanted to bring this thread to your attention and kindly ask you to
confirm whether these patches will be pulled through the imx tree.

Regards,
Ghennadi

Re: [PATCH v2 0/2] add uSDHC and SCMI nodes to the S32G2 SoC

[Shawn Guo]

On Mon, Jan 22, 2024 at 04:05:59PM +0200, Ghennadi Procopciuc wrote:
> From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> 
> This patchset adds device tree support for S32G2 SCMI firmware and uSDHC
> node. The SCMI clock IDs are based on a downstream version of the TF-A
> stored on GitHub [0].
> 
> I can send the patches individually if you prefer that instead of
> submitting them all at once.??
> 
> [0] https://github.com/nxp-auto-linux/arm-trusted-firmware
> 
> Changes in v2:
>  - The SCMI clock bindings header has been removed.
> 
> Ghennadi Procopciuc (2):
>   arm64: dts: s32g: add SCMI firmware node
>   arm64: dts: s32g: add uSDHC node

Applied both, thanks!