From: Ian Ray <ian.ray@gehealthcare.com>
To: Fabio Estevam <festevam@gmail.com>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: imx8mp-msc-sm2s: Add i2c{1,6} sda-/scl-gpios
Date: Mon, 8 Apr 2024 14:44:16 +0300 [thread overview]
Message-ID: <ZhPYkGLM_b5IEKs2@de2cfed78370> (raw)
In-Reply-To: <CAOMZO5B-vTRSfi=tNc_iZxnxYstL8JJOd_1rMf4ps9WHyfx0GQ@mail.gmail.com>
On Mon, Apr 08, 2024 at 08:31:53AM -0300, Fabio Estevam wrote:
>
> Hi Ian,
>
> > + pinctrl_i2c1_gpio: i2c1gpiogrp {
> > + fsl,pins =
> > + <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3>,
>
> The Sion bit is unnecessary in the GPIO mode so you could pass 0x1c3 instead.
Thank you -- I will submit a V2.
Would 0x1c2 be more correct? From the IMX8MPRM.pdf, it seems that the
lowest bit is reserved. Example: 8.2.4.158 SW_PAD_CTL_PAD_GPIO1_IO05
SW PAD Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05).
next prev parent reply other threads:[~2024-04-08 11:44 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-08 9:24 [PATCH] arm64: dts: imx8mp-msc-sm2s: Add i2c{1,6} sda-/scl-gpios Ian Ray
2024-04-08 11:31 ` Fabio Estevam
2024-04-08 11:44 ` Ian Ray [this message]
2024-04-08 11:48 ` Fabio Estevam
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