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[166.137.160.39]) by smtp.gmail.com with ESMTPSA id q18-20020a63d612000000b005dc9ab425c2sm3053438pgg.35.2024.04.12.11.26.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Apr 2024 11:26:14 -0700 (PDT) Date: Fri, 12 Apr 2024 11:26:10 -0700 From: Charlie Jenkins To: Conor Dooley Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Evan Green , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jonathan Corbet , Shuah Khan , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH 15/19] riscv: hwcap: Add v to hwcap if xtheadvector enabled Message-ID: References: <20240411-dev-charlie-support_thead_vector_6_9-v1-0-4af9815ec746@rivosinc.com> <20240411-dev-charlie-support_thead_vector_6_9-v1-15-4af9815ec746@rivosinc.com> <20240412-thrill-amnesty-019897f21466@wendy> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240412-thrill-amnesty-019897f21466@wendy> On Fri, Apr 12, 2024 at 12:37:08PM +0100, Conor Dooley wrote: > On Thu, Apr 11, 2024 at 09:11:21PM -0700, Charlie Jenkins wrote: > > xtheadvector is not vector 1.0 compatible, but it can leverage all of > > the same save/restore routines as vector plus > > riscv_v_first_use_handler(). vector 1.0 and xtheadvector are mutually > > exclusive so there is no risk of overlap. > > I think this not okay to do - if a program checks hwcap to see if vector > is supported they'll get told it is on T-Head system where only the 0.7.1 > is. That's fair. I did remove it from the hwprobe result but this is kind of a gross way of doing it. I'll mess around with this so this isn't necessary. - Charlie > > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/kernel/cpufeature.c | 17 +++++++++++++++-- > > 1 file changed, 15 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 41a4d2028428..59f628b1341c 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -647,9 +647,13 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) > > * Many vendors with T-Head CPU cores which implement the 0.7.1 > > * version of the vector specification put "v" into their DTs. > > * CPU cores with the ratified spec will contain non-zero > > - * marchid. > > + * marchid. Only allow "v" to be set if xtheadvector is present. > > */ > > - if (acpi_disabled && this_vendorid == THEAD_VENDOR_ID && > > + if (__riscv_isa_vendor_extension_available(isavendorinfo->isa, > > + RISCV_ISA_VENDOR_EXT_XTHEADVECTOR)) { > > + this_hwcap |= isa2hwcap[RISCV_ISA_EXT_v]; > > + set_bit(RISCV_ISA_EXT_v, isainfo->isa); > > + } else if (acpi_disabled && this_vendorid == THEAD_VENDOR_ID && > > this_archid == 0x0) { > > this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v]; > > clear_bit(RISCV_ISA_EXT_v, isainfo->isa); > > @@ -776,6 +780,15 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) > > > > of_node_put(cpu_node); > > > > + /* > > + * Enable kernel vector routines if xtheadvector is present > > + */ > > + if (__riscv_isa_vendor_extension_available(isavendorinfo->isa, > > + RISCV_ISA_VENDOR_EXT_XTHEADVECTOR)) { > > + this_hwcap |= isa2hwcap[RISCV_ISA_EXT_v]; > > + set_bit(RISCV_ISA_EXT_v, isainfo->isa); > > + } > > + > > /* > > * All "okay" harts should have same isa. Set HWCAP based on > > * common capabilities of every "okay" hart, in case they don't. > > > > -- > > 2.44.0 > >