From: Charlie Jenkins <charlie@rivosinc.com>
To: Conor Dooley <conor@kernel.org>
Cc: "Evan Green" <evan@rivosinc.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH 02/19] riscv: cpufeature: Fix thead vector hwcap removal
Date: Fri, 12 Apr 2024 11:46:21 -0700 [thread overview]
Message-ID: <ZhmBfaKXMMtolwSr@ghost> (raw)
In-Reply-To: <20240412-employer-crier-c201704d22e3@spud>
On Fri, Apr 12, 2024 at 07:38:04PM +0100, Conor Dooley wrote:
> On Fri, Apr 12, 2024 at 10:04:17AM -0700, Evan Green wrote:
> > On Fri, Apr 12, 2024 at 3:26 AM Conor Dooley <conor.dooley@microchip.com> wrote:
> > >
> > > On Thu, Apr 11, 2024 at 09:11:08PM -0700, Charlie Jenkins wrote:
> > > > The riscv_cpuinfo struct that contains mvendorid and marchid is not
> > > > populated until all harts are booted which happens after the DT parsing.
> > > > Use the vendorid/archid values from the DT if available or assume all
> > > > harts have the same values as the boot hart as a fallback.
> > > >
> > > > Fixes: d82f32202e0d ("RISC-V: Ignore V from the riscv,isa DT property on older T-Head CPUs")
> > >
> > > If this is our only use case for getting the mvendorid/marchid stuff
> > > from dt, then I don't think we should add it. None of the devicetrees
> > > that the commit you're fixing here addresses will have these properties
> > > and if they did have them, they'd then also be new enough to hopefully
> > > not have "v" either - the issue is they're using whatever crap the
> > > vendor shipped.
> > > If we're gonna get the information from DT, we already have something
> > > that we can look at to perform the disable as the cpu compatibles give
> > > us enough information to make the decision.
> > >
> > > I also think that we could just cache the boot CPU's marchid/mvendorid,
> > > since we already have to look at it in riscv_fill_cpu_mfr_info(), avoid
> > > repeating these ecalls on all systems.
> > >
> > > Perhaps for now we could just look at the boot CPU alone? To my
> > > knowledge the systems that this targets all have homogeneous
> > > marchid/mvendorid values of 0x0.
> >
> > It's possible I'm misinterpreting, but is the suggestion to apply the
> > marchid/mvendorid we find on the boot CPU and assume it's the same on
> > all other CPUs? Since we're reporting the marchid/mvendorid/mimpid to
> > usermode in a per-hart way, it would be better IMO if we really do
> > query marchid/mvendorid/mimpid on each hart. The problem with applying
> > the boot CPU's value everywhere is if we're ever wrong in the future
> > (ie that assumption doesn't hold on some machine), we'll only find out
> > about it after the fact. Since we reported the wrong information to
> > usermode via hwprobe, it'll be an ugly userspace ABI issue to clean
> > up.
>
> You're misinterpreting, we do get the values on all individually as
> they're brought online. This is only used by the code that throws a bone
> to people with crappy vendor dtbs that put "v" in riscv,isa when they
> support the unratified version.
Not quite, the alternatives are patched before the other cpus are
booted, so the alternatives will have false positives resulting in
broken kernels.
- Charlie
next prev parent reply other threads:[~2024-04-12 18:46 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-12 4:11 [PATCH 00/19] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-04-12 4:11 ` [PATCH 01/19] dt-bindings: riscv: Add vendorid and archid Charlie Jenkins
2024-04-12 9:57 ` Conor Dooley
2024-04-12 4:11 ` [PATCH 02/19] riscv: cpufeature: Fix thead vector hwcap removal Charlie Jenkins
2024-04-12 10:25 ` Conor Dooley
2024-04-12 17:04 ` Evan Green
2024-04-12 18:38 ` Conor Dooley
2024-04-12 18:46 ` Charlie Jenkins [this message]
2024-04-12 19:26 ` Conor Dooley
2024-04-12 20:34 ` Charlie Jenkins
2024-04-12 20:42 ` Conor Dooley
2024-04-12 17:12 ` Charlie Jenkins
2024-04-12 18:47 ` Conor Dooley
2024-04-12 20:48 ` Charlie Jenkins
2024-04-12 21:27 ` Conor Dooley
2024-04-12 21:31 ` Charlie Jenkins
2024-04-12 23:40 ` Conor Dooley
2024-04-16 3:34 ` Charlie Jenkins
2024-04-16 7:36 ` Conor Dooley
2024-04-17 4:25 ` Charlie Jenkins
2024-04-17 16:02 ` Evan Green
2024-04-17 22:02 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 03/19] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-04-12 10:27 ` Conor Dooley
2024-04-12 17:13 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 04/19] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-04-12 4:11 ` [PATCH 05/19] riscv: Fix extension subset checking Charlie Jenkins
2024-04-12 11:25 ` Conor Dooley
2024-04-12 4:11 ` [PATCH 06/19] riscv: Extend cpufeature.c to detect vendor extensions Charlie Jenkins
2024-04-12 12:30 ` Conor Dooley
2024-04-12 16:58 ` Charlie Jenkins
2024-04-12 18:59 ` Conor Dooley
2024-04-12 14:44 ` kernel test robot
2024-04-13 22:10 ` kernel test robot
2024-04-12 4:11 ` [PATCH 07/19] riscv: Optimize riscv_cpu_isa_extension_(un)likely() Charlie Jenkins
2024-04-12 10:40 ` Conor Dooley
2024-04-12 17:34 ` Charlie Jenkins
2024-04-12 20:33 ` Conor Dooley
2024-04-12 4:11 ` [PATCH 08/19] riscv: Introduce vendor variants of extension helpers Charlie Jenkins
2024-04-12 11:49 ` Conor Dooley
2024-04-12 17:43 ` Charlie Jenkins
2024-04-12 20:40 ` Conor Dooley
2024-04-12 21:03 ` Charlie Jenkins
2024-04-12 21:34 ` Conor Dooley
2024-04-12 21:56 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 09/19] riscv: uaccess: Add alternative for xtheadvector uaccess Charlie Jenkins
2024-04-12 4:11 ` [PATCH 10/19] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-04-12 11:27 ` Conor Dooley
2024-04-12 18:22 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 11/19] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-04-12 4:11 ` [PATCH 12/19] riscv: Create xtheadvector file Charlie Jenkins
2024-04-12 11:30 ` Conor Dooley
2024-04-12 18:24 ` Charlie Jenkins
2024-04-12 19:00 ` Conor Dooley
2024-04-12 20:53 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 13/19] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-04-12 4:11 ` [PATCH 14/19] riscv: hwprobe: Disambiguate vector and xtheadvector in hwprobe Charlie Jenkins
2024-04-12 11:34 ` Conor Dooley
2024-04-12 17:04 ` Evan Green
2024-04-12 18:22 ` Charlie Jenkins
2024-04-12 22:08 ` Evan Green
2024-04-12 22:37 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 15/19] riscv: hwcap: Add v to hwcap if xtheadvector enabled Charlie Jenkins
2024-04-12 11:37 ` Conor Dooley
2024-04-12 18:26 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 16/19] riscv: hwprobe: Add vendor extension probing Charlie Jenkins
2024-04-12 11:39 ` Conor Dooley
2024-04-12 17:05 ` Evan Green
2024-04-12 18:16 ` Charlie Jenkins
2024-04-12 19:07 ` Evan Green
2024-04-12 20:20 ` Charlie Jenkins
2024-04-12 21:43 ` Evan Green
2024-04-12 22:21 ` Charlie Jenkins
2024-04-12 22:50 ` Evan Green
2024-04-12 23:12 ` Charlie Jenkins
2024-04-12 4:11 ` [PATCH 17/19] riscv: hwprobe: Document vendor extensions and xtheadvector extension Charlie Jenkins
2024-04-12 4:11 ` [PATCH 18/19] selftests: riscv: Fix vector tests Charlie Jenkins
2024-04-12 4:11 ` [PATCH 19/19] selftests: riscv: Support xtheadvector in " Charlie Jenkins
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