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AJvYcCXqLGW379s1UXLEGxewR1OATQzYINyWnWVNh6I+mN8tOzX7At4Rno4E/BVcrSHVjGOi1wjMNtc89UvGuomg0Vi0oIx36KySaBrVrg== X-Gm-Message-State: AOJu0Yxld29YWIY8/J/0G49qQuhXdXSbz+QW4Cy6QRE/fkZN6+9ZiQ1a hTgGom2YkBnud5XqyhWhMKLxmxx571fh0jUTrc8x9xZUxgCO6eoT1Grlrnva7QE= X-Google-Smtp-Source: AGHT+IEiDU5SQjuL7+0vdKdkoS1KFGY8onYhPVJwXQzy7eXZ9mhuURRy3tq7dfxgiflxBiFa6A84tg== X-Received: by 2002:a05:6a21:3381:b0:1aa:6ddb:4adf with SMTP id yy1-20020a056a21338100b001aa6ddb4adfmr1271607pzb.39.1713391214298; Wed, 17 Apr 2024 15:00:14 -0700 (PDT) Received: from ghost ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id j18-20020a62e912000000b006e681769ee0sm151780pfh.145.2024.04.17.15.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Apr 2024 15:00:13 -0700 (PDT) Date: Wed, 17 Apr 2024 15:00:07 -0700 From: Charlie Jenkins To: Conor Dooley Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Evan Green , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jonathan Corbet , Shuah Khan , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v2 13/17] riscv: vector: Support xtheadvector save/restore Message-ID: References: <20240415-dev-charlie-support_thead_vector_6_9-v2-0-c7d68c603268@rivosinc.com> <20240415-dev-charlie-support_thead_vector_6_9-v2-13-c7d68c603268@rivosinc.com> <20240417-semisweet-willed-1ce1098d8c41@spud> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240417-semisweet-willed-1ce1098d8c41@spud> On Wed, Apr 17, 2024 at 03:50:24PM +0100, Conor Dooley wrote: > On Mon, Apr 15, 2024 at 09:12:10PM -0700, Charlie Jenkins wrote: > > > diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c > > index 6727d1d3b8f2..f42eaa8178e9 100644 > > --- a/arch/riscv/kernel/vector.c > > +++ b/arch/riscv/kernel/vector.c > > @@ -33,10 +33,24 @@ int riscv_v_setup_vsize(void) > > { > > unsigned long this_vsize; > > > > - /* There are 32 vector registers with vlenb length. */ > > - riscv_v_enable(); > > - this_vsize = csr_read(CSR_VLENB) * 32; > > - riscv_v_disable(); > > + /* > > + * This is called before alternatives have been patched so can't use > > + * riscv_has_vendor_extension_unlikely > > () after that function name please. > > > + */ > > + if (has_xtheadvector_no_alternatives()) { > > + /* > > + * Although xtheadvector states that th.vlenb exists and > > + * overlaps with the vector 1.0 vlenb, an illegal instruction is > > + * raised if read. These systems all currently have a fixed > > + * vector length of 128, so hardcode that value. > > I had this written before the meeting, so pasting it anyway: > -- >8 -- > From 5ed25d0f841e755b8dd4f1f6a3ea824601758d8e Mon Sep 17 00:00:00 2001 > From: Conor Dooley > Date: Wed, 17 Apr 2024 14:39:36 +0100 > Subject: [PATCH] dt-bindings: riscv: cpus: add a vlen register length property > > Add a property analogous to the vlenb CSR so that software can detect > the vector length of each CPU prior to it being brought online. > Currently software has to assume that the vector length read from the > boot CPU applies to all possible CPUs. On T-Head CPUs implementing > pre-ratification vector, reading the th.vlenb CSR may produce an illegal > instruction trap, so this property is required on such systems. > > Signed-off-by: Conor Dooley > --- > We could actually enforce the latter since we know the compatibles of > the relevant CPUs and can tell if xtheadvector is present. > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index d067f2a468ee..2a6449a0f1d7 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -95,6 +95,12 @@ properties: > description: > The blocksize in bytes for the Zicboz cache operations. > > + riscv,vlenb: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + VLEN/8, the vector register length in bytes. This property is required in > + systems where the vector register length is not identical on all harts. > + > # RISC-V has multiple properties for cache op block sizes as the sizes > # differ between individual CBO extensions > cache-op-block-size: false > -- > 2.43.0 > > > > > + */ > > + this_vsize = 128; > > + } else { > > + /* There are 32 vector registers with vlenb length. */ > > + riscv_v_enable(); > > + this_vsize = csr_read(CSR_VLENB) * 32; > > + riscv_v_disable(); > > + } Thank you for this, I can add this patch to my v3. - Charlie