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AJvYcCUb5QBnOD4G1Hq/G2YaDLOmxdUeO7zUNzPTMD6BTSgOVJjuIb4E0ZaFPJ81f9tY9xDxGtJDpU5QMqUDMO/c5UT1wfUuffY1ohuSjA== X-Gm-Message-State: AOJu0YwWOQD+O3QLXSMb8TGGfluZ/NqVZ4f6JlRz19EO/Amk3bHUILHn NN/5kBpKmcAzdyREzOvRj5FjSLLbHLDdPUA73HUpZYRsOKdrgfM8 X-Google-Smtp-Source: AGHT+IHDnjdZhBKZ/N8qotjF8wfVr8PE8appA8t34tqhSKSbaxo3xaKZxkRcR1Kc49r1HaArvS4mCg== X-Received: by 2002:a5d:59a8:0:b0:343:7b6b:dcc6 with SMTP id p8-20020a5d59a8000000b003437b6bdcc6mr7249290wrr.30.1713734212622; Sun, 21 Apr 2024 14:16:52 -0700 (PDT) Received: from andrea ([31.189.47.123]) by smtp.gmail.com with ESMTPSA id n12-20020a5d67cc000000b0034a51283404sm7734635wrw.72.2024.04.21.14.16.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Apr 2024 14:16:52 -0700 (PDT) Date: Sun, 21 Apr 2024 23:16:47 +0200 From: Andrea Parri To: Andrew Jones Cc: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor.dooley@microchip.com, anup@brainfault.org, atishp@atishpatra.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, christoph.muellner@vrull.eu, heiko@sntech.de, charlie@rivosinc.com, David.Laight@aculab.com, luxu.kernel@bytedance.com Subject: Re: [PATCH v2 3/6] riscv: Add Zawrs support for spinlocks Message-ID: References: <20240419135321.70781-8-ajones@ventanamicro.com> <20240419135321.70781-11-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240419135321.70781-11-ajones@ventanamicro.com> On Fri, Apr 19, 2024 at 03:53:25PM +0200, Andrew Jones wrote: > From: Christoph M??llner > > RISC-V code uses the generic ticket lock implementation, which calls > the macros smp_cond_load_relaxed() and smp_cond_load_acquire(). > Introduce a RISC-V specific implementation of smp_cond_load_relaxed() > which applies WRS.NTO of the Zawrs extension in order to reduce power > consumption while waiting and allows hypervisors to enable guests to > trap while waiting. smp_cond_load_acquire() doesn't need a RISC-V > specific implementation as the generic implementation is based on > smp_cond_load_relaxed() and smp_acquire__after_ctrl_dep() sufficiently > provides the acquire semantics. > > This implementation is heavily based on Arm's approach which is the > approach Andrea Parri also suggested. > > The Zawrs specification can be found here: > https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc > > Signed-off-by: Christoph M??llner > Co-developed-by: Andrew Jones > Signed-off-by: Andrew Jones > --- > arch/riscv/Kconfig | 13 ++++++++ > arch/riscv/include/asm/barrier.h | 45 ++++++++++++++++++--------- > arch/riscv/include/asm/cmpxchg.h | 51 +++++++++++++++++++++++++++++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/asm/insn-def.h | 2 ++ > arch/riscv/kernel/cpufeature.c | 1 + > 6 files changed, 98 insertions(+), 15 deletions(-) Doesn't apply to riscv/for-next (due to, AFAIU, https://lore.kernel.org/all/171275883330.18495.10110341843571163280.git-patchwork-notify@kernel.org/ ). But other than that, this LGTM. One nit below. > -#define __smp_store_release(p, v) \ > -do { \ > - compiletime_assert_atomic_type(*p); \ > - RISCV_FENCE(rw, w); \ > - WRITE_ONCE(*p, v); \ > -} while (0) > - > -#define __smp_load_acquire(p) \ > -({ \ > - typeof(*p) ___p1 = READ_ONCE(*p); \ > - compiletime_assert_atomic_type(*p); \ > - RISCV_FENCE(r, rw); \ > - ___p1; \ > -}) > - > /* > * This is a very specific barrier: it's currently only used in two places in > * the kernel, both in the scheduler. See include/linux/spinlock.h for the two > @@ -70,6 +56,35 @@ do { \ > */ > #define smp_mb__after_spinlock() RISCV_FENCE(iorw, iorw) > > +#define __smp_store_release(p, v) \ > +do { \ > + compiletime_assert_atomic_type(*p); \ > + RISCV_FENCE(rw, w); \ > + WRITE_ONCE(*p, v); \ > +} while (0) > + > +#define __smp_load_acquire(p) \ > +({ \ > + typeof(*p) ___p1 = READ_ONCE(*p); \ > + compiletime_assert_atomic_type(*p); \ > + RISCV_FENCE(r, rw); \ > + ___p1; \ > +}) Unrelated/unmotivated changes. Andrea