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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, May 01, 2024 at 09:46:00AM -0700, Evan Green wrote: > On Fri, Apr 26, 2024 at 2:37 PM Charlie Jenkins wrote: > > > > Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which > > allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR > > vendor extension. > > > > This new key will allow userspace code to probe for which thead vendor > > extensions are supported. This API is modeled to be consistent with > > RISCV_HWPROBE_KEY_IMA_EXT_0. The bitmask returned will have each bit > > corresponding to a supported thead vendor extension of the cpumask set. > > Just like RISCV_HWPROBE_KEY_IMA_EXT_0, this allows a userspace program > > to determine all of the supported thead vendor extensions in one call. > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/include/asm/hwprobe.h | 4 +-- > > .../include/asm/vendor_extensions/thead_hwprobe.h | 11 ++++++ > > arch/riscv/include/uapi/asm/hwprobe.h | 3 +- > > arch/riscv/include/uapi/asm/vendor/thead.h | 3 ++ > > arch/riscv/kernel/sys_hwprobe.c | 9 +++++ > > arch/riscv/kernel/vendor_extensions/Makefile | 1 + > > .../riscv/kernel/vendor_extensions/thead_hwprobe.c | 42 ++++++++++++++++++++++ > > 7 files changed, 70 insertions(+), 3 deletions(-) > > > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > > index 630507dff5ea..e68496b4f8de 100644 > > --- a/arch/riscv/include/asm/hwprobe.h > > +++ b/arch/riscv/include/asm/hwprobe.h > > @@ -1,6 +1,6 @@ > > /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > > /* > > - * Copyright 2023 Rivos, Inc > > + * Copyright 2023-2024 Rivos, Inc > > */ > > > > #ifndef _ASM_HWPROBE_H > > @@ -8,7 +8,7 @@ > > > > #include > > > > -#define RISCV_HWPROBE_MAX_KEY 6 > > +#define RISCV_HWPROBE_MAX_KEY 7 > > > > static inline bool riscv_hwprobe_key_is_valid(__s64 key) > > { > > diff --git a/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h > > new file mode 100644 > > index 000000000000..907cfc4eb4dc > > --- /dev/null > > +++ b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h > > @@ -0,0 +1,11 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H > > +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H > > + > > +#include > > + > > +#include > > + > > +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus); > > + > > +#endif > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > > index 9f2a8e3ff204..21e96a63f9ea 100644 > > --- a/arch/riscv/include/uapi/asm/hwprobe.h > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > > @@ -1,6 +1,6 @@ > > /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > > /* > > - * Copyright 2023 Rivos, Inc > > + * Copyright 2023-2024 Rivos, Inc > > */ > > > > #ifndef _UAPI_ASM_HWPROBE_H > > @@ -67,6 +67,7 @@ struct riscv_hwprobe { > > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) > > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) > > #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 > > +#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 7 > > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > > > > /* Flags */ > > diff --git a/arch/riscv/include/uapi/asm/vendor/thead.h b/arch/riscv/include/uapi/asm/vendor/thead.h > > new file mode 100644 > > index 000000000000..43790ebe5faf > > --- /dev/null > > +++ b/arch/riscv/include/uapi/asm/vendor/thead.h > > @@ -0,0 +1,3 @@ > > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > > + > > +#define RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR (1 << 0) > > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > > index 8cae41a502dd..e59cac545df5 100644 > > --- a/arch/riscv/kernel/sys_hwprobe.c > > +++ b/arch/riscv/kernel/sys_hwprobe.c > > @@ -13,6 +13,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > > > @@ -216,6 +217,14 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > > pair->value = riscv_cboz_block_size; > > break; > > > > + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: > > +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD > > + hwprobe_isa_vendor_ext_thead_0(pair, cpus); > > +#else > > + pair->value = 0; > > +#endif > > Could we move this ifdef into the header by declaring a dummy > hwprobe_isa_vendor_ext_thead_0() in the header for the !ENABLED case? > > > + break; > > + > > /* > > * For forward compatibility, unknown keys don't fail the whole > > * call, but get their element key set to -1 and value set to 0 > > diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile > > index 8f1c5a4dc38f..f511fd269e8a 100644 > > --- a/arch/riscv/kernel/vendor_extensions/Makefile > > +++ b/arch/riscv/kernel/vendor_extensions/Makefile > > @@ -1,4 +1,5 @@ > > # SPDX-License-Identifier: GPL-2.0-only > > > > obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o > > +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead_hwprobe.o > > obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o > > diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c > > new file mode 100644 > > index 000000000000..e8e2de292032 > > --- /dev/null > > +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c > > @@ -0,0 +1,42 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > + > > +#include > > +#include > > +#include > > + > > +#include > > +#include > > + > > +#include > > +#include > > + > > +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus) > > +{ > > + /* > > + * Loop through and record extensions that 1) anyone has, and 2) anyone > > + * doesn't have. > > + */ > > + > > + struct riscv_isainfo *per_hart_thead_bitmap = riscv_isa_vendor_ext_list_thead.per_hart_vendor_bitmap; > > + int cpu; > > + u64 missing; > > + > > + for_each_cpu(cpu, cpus) { > > + struct riscv_isainfo *isainfo = &per_hart_thead_bitmap[cpu]; > > + > > +#define EXT_KEY(ext) \ > > + do { \ > > + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_VENDOR_EXT_##ext)) \ > > + pair->value |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ > > + else \ > > + missing |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ > > + } while (false) > > + > > + EXT_KEY(XTHEADVECTOR); > > + > > +#undef EXT_KEY > > + } > > + > > + /* Now turn off reporting features if any CPU is missing it. */> + pair->value &= ~missing; > > +} > > Something to consider, perhaps when there's a second vendor, is how we > might reduce this boilerplate on the second vendor. Probably best to > wait though until we know exactly what the commonalities are. This > looks good for now. > Yes it should be mostly identical on second vendor. I think the only difference would be "per_hart_thead_bitmap" and the list of extensions. I can probably factor this out a bit. - Charlie > > > > > -- > > 2.44.0 > >