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Thu, 13 Jun 2024 03:49:22 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45D3nLW0009867 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Jun 2024 03:49:21 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 12 Jun 2024 20:49:17 -0700 Date: Thu, 13 Jun 2024 09:19:13 +0530 From: Varadarajan Narayanan To: Georgi Djakov CC: Konrad Dybcio , Dmitry Baryshkov , , , , , , , , , , , , Subject: Re: [PATCH v9 6/6] arm64: dts: qcom: ipq9574: Add icc provider ability to gcc Message-ID: References: <1a08ef42-b52f-4c97-90d7-e7fdee7725b4@linaro.org> <176137e5-6312-4d46-97b6-c4494bc1c61b@kernel.org> <8e32a8be-dbbf-49ca-92a1-2fe3c8bfb571@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <8e32a8be-dbbf-49ca-92a1-2fe3c8bfb571@kernel.org> X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: nS2B1HDPmkmi_KaZUDeK3HPSMD89fvdJ X-Proofpoint-ORIG-GUID: nS2B1HDPmkmi_KaZUDeK3HPSMD89fvdJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-12_12,2024-06-13_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 clxscore=1015 mlxscore=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 phishscore=0 bulkscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406130024 On Wed, Jun 12, 2024 at 03:52:51PM +0300, Georgi Djakov wrote: > On 12.06.24 13:28, Varadarajan Narayanan wrote: > > On Wed, Jun 12, 2024 at 11:48:17AM +0300, Georgi Djakov wrote: > > > On 12.06.24 9:30, Varadarajan Narayanan wrote: > > > > On Tue, Jun 11, 2024 at 02:29:48PM +0300, Georgi Djakov wrote: > > > > > On 11.06.24 12:42, Varadarajan Narayanan wrote: > > > > > > On Thu, Jun 06, 2024 at 04:06:01PM +0200, Konrad Dybcio wrote: > > > > > > > On 8.05.2024 10:10 AM, Dmitry Baryshkov wrote: > > > > > > > > On Wed, 8 May 2024 at 09:53, Varadarajan Narayanan > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > On Fri, May 03, 2024 at 04:51:04PM +0300, Georgi Djakov wrote: > > > > > > > > > > Hi Varada, > > > > > > > > > > > > > > > > > > > > Thank you for your work on this! > > > > > > > > > > > > > > > > > > > > On 2.05.24 12:30, Varadarajan Narayanan wrote: > > > > > > > > > > > On Tue, Apr 30, 2024 at 12:05:29PM +0200, Konrad Dybcio wrote: > > > > > > > > > > > > On 25.04.2024 12:26 PM, Varadarajan Narayanan wrote: > > > > > > > > > > > > > On Tue, Apr 23, 2024 at 02:58:41PM +0200, Konrad Dybcio wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On 4/18/24 11:23, Varadarajan Narayanan wrote: > > > > > > > > > > > > > > > IPQ SoCs dont involve RPM in managing NoC related clocks and > > > > > > > > > > > > > > > there is no NoC scaling. Linux itself handles these clocks. > > > > > > > > > > > > > > > However, these should not be exposed as just clocks and align > > > > > > > > > > > > > > > with other Qualcomm SoCs that handle these clocks from a > > > > > > > > > > > > > > > interconnect provider. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hence include icc provider capability to the gcc node so that > > > > > > > > > > > > > > > peripherals can use the interconnect facility to enable these > > > > > > > > > > > > > > > clocks. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Reviewed-by: Dmitry Baryshkov > > > > > > > > > > > > > > > Signed-off-by: Varadarajan Narayanan > > > > > > > > > > > > > > > --- > > > > > > > > > > > > > > > > > > > > > > > > > > > > If this is all you do to enable interconnect (which is not the case, > > > > > > > > > > > > > > as this patch only satisfies the bindings checker, the meaningful > > > > > > > > > > > > > > change happens in the previous patch) and nothing explodes, this is > > > > > > > > > > > > > > an apparent sign of your driver doing nothing. > > > > > > > > > > > > > > > > > > > > > > > > > > It appears to do nothing because, we are just enabling the clock > > > > > > > > > > > > > provider to also act as interconnect provider. Only when the > > > > > > > > > > > > > consumers are enabled with interconnect usage, this will create > > > > > > > > > > > > > paths and turn on the relevant NOC clocks. > > > > > > > > > > > > > > > > > > > > > > > > No, with sync_state it actually does "something" (sets the interconnect > > > > > > > > > > > > path bandwidths to zero). And *this* patch does nothing functionally, > > > > > > > > > > > > it only makes the dt checker happy. > > > > > > > > > > > > > [..] > > > > > nsscc_ipq9574 was not using icc_sync_state. After adding that, I > > can see the following messages printed from icc_sync_state. I > > also added a print to confirm if 'p->set(n, n);' is called. > > Ok, that's good! So now when all providers are using sync_state, we > can go back to the initial comment from Konrad. I think you should > re-check the tests that you did, as the current results just lead to > more questions than answers. Maybe it was just the sync-state that > was missing, or there is some other issue. Georgi, Thanks very much for the clarifications. Will re-test the patches and update the thread. -Varada > [..] > > > > The gcc based interconnect paths are referenced by PCIe controller > > nodes. Please refer to this patch > > > > [PATCH V5 4/6] arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes > > https://lore.kernel.org/linux-arm-msm/20240512082858.1806694-5-quic_devipriy@quicinc.com/ > > > > Sorry, did not post the nsscc related patches since this base ICC > > patch hasn't reached closure. The nsscc patches are very similar > > to this gcc based series. Wanted to gather the issues raised in > > this and address them in nsscc so that it is in a more acceptable > > shape. > > > > Thanks > > Varada >