From: Charlie Jenkins <charlie@rivosinc.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: "Jesse Taube" <jesse@rivosinc.com>,
linux-riscv@lists.infradead.org,
"Jonathan Corbet" <corbet@lwn.net>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Clément Léger" <cleger@rivosinc.com>,
"Evan Green" <evan@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Xiao Wang" <xiao.w.wang@intel.com>,
"Andy Chiu" <andy.chiu@sifive.com>,
"Eric Biggers" <ebiggers@google.com>,
"Greentime Hu" <greentime.hu@sifive.com>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Costa Shulyupin" <costa.shul@redhat.com>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Baoquan He" <bhe@redhat.com>,
"Anup Patel" <apatel@ventanamicro.com>,
"Zong Li" <zong.li@sifive.com>,
"Sami Tolvanen" <samitolvanen@google.com>,
"Ben Dooks" <ben.dooks@codethink.co.uk>,
"Alexandre Ghiti" <alexghiti@rivosinc.com>,
"Gustavo A. R. Silva" <gustavoars@kernel.org>,
"Erick Archer" <erick.archer@gmx.com>,
"Joel Granados" <j.granados@samsung.com>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v2 3/6] RISC-V: Check scalar unaligned access on all CPUs
Date: Mon, 17 Jun 2024 16:56:58 -0700 [thread overview]
Message-ID: <ZnDNSthEVSSXpJnC@ghost> (raw)
In-Reply-To: <20240614-padded-mammal-d956735c1293@wendy>
On Fri, Jun 14, 2024 at 09:22:47AM +0100, Conor Dooley wrote:
> On Thu, Jun 13, 2024 at 03:16:12PM -0400, Jesse Taube wrote:
> > Originally, the check_unaligned_access_emulated_all_cpus function
> > only checked the boot hart. This fixes the function to check all
> > harts.
>
> This seems like it should be split out and get a Fixes: tag & a cc:
> stable.
These changes are great Jesse! I agree with Conor, please split these
changes into two different patches with a fixes tag for
71c54b3d169d ("riscv: report misaligned accesses emulation to hwprobe").
- Charlie
>
> > Check for Zicclsm before checking for unaligned access. This will
> > greatly reduce the boot up time as finding the access speed is no longer
> > necessary.
> >
> > Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> > ---
> > V1 -> V2:
> > - New patch
> > ---
> > arch/riscv/kernel/traps_misaligned.c | 23 ++++++----------------
> > arch/riscv/kernel/unaligned_access_speed.c | 23 +++++++++++++---------
> > 2 files changed, 20 insertions(+), 26 deletions(-)
> >
> > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> > index b62d5a2f4541..8fadbe00dd62 100644
> > --- a/arch/riscv/kernel/traps_misaligned.c
> > +++ b/arch/riscv/kernel/traps_misaligned.c
> > @@ -526,31 +526,17 @@ int handle_misaligned_store(struct pt_regs *regs)
> > return 0;
> > }
> >
> > -static bool check_unaligned_access_emulated(int cpu)
> > +static void check_unaligned_access_emulated(struct work_struct *unused)
> > {
> > + int cpu = smp_processor_id();
> > long *mas_ptr = per_cpu_ptr(&misaligned_access_speed, cpu);
> > unsigned long tmp_var, tmp_val;
> > - bool misaligned_emu_detected;
> >
> > *mas_ptr = RISCV_HWPROBE_MISALIGNED_UNKNOWN;
> >
> > __asm__ __volatile__ (
> > " "REG_L" %[tmp], 1(%[ptr])\n"
> > : [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory");
> > -
> > - misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_EMULATED);
> > - /*
> > - * If unaligned_ctl is already set, this means that we detected that all
> > - * CPUS uses emulated misaligned access at boot time. If that changed
> > - * when hotplugging the new cpu, this is something we don't handle.
> > - */
> > - if (unlikely(unaligned_ctl && !misaligned_emu_detected)) {
> > - pr_crit("CPU misaligned accesses non homogeneous (expected all emulated)\n");
> > - while (true)
> > - cpu_relax();
> > - }
> > -
> > - return misaligned_emu_detected;
> > }
> >
> > bool check_unaligned_access_emulated_all_cpus(void)
> > @@ -562,8 +548,11 @@ bool check_unaligned_access_emulated_all_cpus(void)
> > * accesses emulated since tasks requesting such control can run on any
> > * CPU.
> > */
> > + schedule_on_each_cpu(check_unaligned_access_emulated);
> > +
> > for_each_online_cpu(cpu)
> > - if (!check_unaligned_access_emulated(cpu))
> > + if (per_cpu(misaligned_access_speed, cpu)
> > + != RISCV_HWPROBE_MISALIGNED_EMULATED)
> > return false;
> >
> > unaligned_ctl = true;
> > diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c
> > index a9a6bcb02acf..70c1588fc353 100644
> > --- a/arch/riscv/kernel/unaligned_access_speed.c
> > +++ b/arch/riscv/kernel/unaligned_access_speed.c
> > @@ -259,23 +259,28 @@ static int check_unaligned_access_speed_all_cpus(void)
> > kfree(bufs);
> > return 0;
> > }
> > +#endif /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */
> >
> > static int check_unaligned_access_all_cpus(void)
> > {
> > - bool all_cpus_emulated = check_unaligned_access_emulated_all_cpus();
> > + bool all_cpus_emulated;
> > + int cpu;
> >
> > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICCLSM)) {
> > + for_each_online_cpu(cpu) {
> > + per_cpu(misaligned_access_speed, cpu) = RISCV_HWPROBE_MISALIGNED_FAST;
> > + }
> > + return 0;
> > + }
> > +
> > + all_cpus_emulated = check_unaligned_access_emulated_all_cpus();
> > +
> > +#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS
>
> Can we make this an IS_ENABLED() please?
>
>
> Thanks,
> Conor.
>
> > if (!all_cpus_emulated)
> > return check_unaligned_access_speed_all_cpus();
> > +#endif
> >
> > return 0;
> > }
> > -#else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */
> > -static int check_unaligned_access_all_cpus(void)
> > -{
> > - check_unaligned_access_emulated_all_cpus();
> > -
> > - return 0;
> > -}
> > -#endif
> >
> > arch_initcall(check_unaligned_access_all_cpus);
> > --
> > 2.43.0
> >
next prev parent reply other threads:[~2024-06-17 23:57 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-13 19:16 [PATCH v2 0/6] RISC-V: Detect and report speed of unaligned vector accesses Jesse Taube
2024-06-13 19:16 ` [PATCH v2 1/6] RISC-V: Add Zicclsm to cpufeature and hwprobe Jesse Taube
2024-06-14 8:09 ` Conor Dooley
2024-06-17 3:18 ` Andy Chiu
2024-06-13 19:16 ` [PATCH v2 2/6] dt-bindings: riscv: Add Zicclsm ISA extension description Jesse Taube
2024-06-14 8:06 ` Conor Dooley
2024-06-13 19:16 ` [PATCH v2 3/6] RISC-V: Check scalar unaligned access on all CPUs Jesse Taube
2024-06-14 8:22 ` Conor Dooley
2024-06-17 23:56 ` Charlie Jenkins [this message]
2024-06-13 19:16 ` [PATCH v2 4/6] RISC-V: Detect unaligned vector accesses supported Jesse Taube
2024-06-14 8:36 ` Conor Dooley
2024-06-14 8:40 ` Conor Dooley
2024-06-14 14:28 ` Jesse Taube
2024-06-14 14:32 ` Conor Dooley
2024-06-17 16:39 ` Charlie Jenkins
2024-06-18 1:43 ` Charlie Jenkins
2024-06-18 2:09 ` Charlie Jenkins
2024-06-20 21:31 ` Jesse Taube
2024-06-20 22:14 ` Charlie Jenkins
2024-06-20 23:08 ` Jesse Taube
2024-06-21 10:06 ` Conor Dooley
2024-06-21 17:18 ` Charlie Jenkins
2024-06-21 17:58 ` Eric Biggers
2024-06-21 18:02 ` Conor Dooley
2024-06-21 18:07 ` Jesse Taube
2024-06-22 11:42 ` Conor Dooley
2024-06-20 18:51 ` Evan Green
2024-06-24 5:34 ` Andy Chiu
2024-06-24 16:57 ` Evan Green
2024-06-13 19:16 ` [PATCH v2 5/6] RISC-V: Report vector unaligned access speed hwprobe Jesse Taube
2024-06-20 18:51 ` Evan Green
2024-06-13 19:16 ` [PATCH v2 6/6] RISC-V: hwprobe: Document unaligned vector perf key Jesse Taube
2024-06-20 18:51 ` Evan Green
2024-06-21 18:30 ` Jesse Taube
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