Re: [PATCH v2] arm64: dts: qcom: x1e80100: Enable tsens and thermal zone nodes

[Abel Vesa <abel.vesa@linaro.org>]

On 24-06-17 11:24:22, Johan Hovold wrote:
> On Fri, Jun 14, 2024 at 01:50:07PM +0300, Abel Vesa wrote:
> > From: Rajendra Nayak <quic_rjendra@quicinc.com>
> > 
> > Add tsens and thermal zones nodes for x1e80100 SoC.
> > 
> > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > ---
> > Changes in v2:
> > - Dropped the thermal engine nodes.
> > - Dropped comments from tsens nodes.
> > - Droppd the polling-delay entirely and polling-delay-passive where not
> >   necessary.
> > - Added top/bottom location to all sensors (where applicable).
> > - Fixed trip points with duplicate values for same temp.
> > - Marked as critical the 125°C throughout all trip points.
> > - Link to v1: https://lore.kernel.org/r/20240527-x1e80100-dts-thermal-v1-1-ea13b8fa6ffc@linaro.org
> > ---
> >  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 1176 ++++++++++++++++++++++++++++++++
> >  1 file changed, 1176 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > index 9944c654851e..df13df7967db 100644
> > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> 
> > +		cpu0-0-bottom-thermal {
> > +			thermal-sensors = <&tsens0 2>;
> > +
> > +			trips {
> > +				trip-point0 {
> > +					temperature = <90000>;
> > +					hysteresis = <2000>;
> > +					type = "passive";
> > +				};
> > +
> > +				trip-point1 {
> > +					temperature = <95000>;
> > +					hysteresis = <2000>;
> > +					type = "passive";
> > +				};
> > +
> > +				cpu-critical {
> > +					temperature = <110000>;
> > +					hysteresis = <1000>;
> > +					type = "critical";
> > +				};
> > +			};
> > +		};
> 
> The CPU bottom thermal zones fail to register with v2:
> 
> [    0.146219] thermal_sys: Thermal zone name (cpu0-0-bottom-thermal) too long, should be under 20 chars

Urgh, did not test after renaming the zones.

Talking to Daniel Lezcano, he seems to suggest that the size can become
dynamic at some point. For now will switch back to
cpu0-0-0-bottom-thermal and cpuss0-0-thermal. So that's O for top and 1
for bottom. TBF, the positions are not really top and bottom on this
platform, but rather left top and right bottom.

> 
> Johan