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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f9ebbc8dbcsm19672865ad.307.2024.06.21.17.03.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 17:03:49 -0700 (PDT) Date: Fri, 21 Jun 2024 17:03:45 -0700 From: William McVicker To: =?iso-8859-1?Q?Andr=E9?= Draszik Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar , Sam Protsenko , Krzysztof Kozlowski , Tudor Ambarus , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: Re: [PATCH v3 4/6] phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk Message-ID: References: <20240617-usb-phy-gs101-v3-0-b66de9ae7424@linaro.org> <20240617-usb-phy-gs101-v3-4-b66de9ae7424@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240617-usb-phy-gs101-v3-4-b66de9ae7424@linaro.org> On 06/17/2024, André Draszik wrote: > In preparation for support for additional platforms, convert the phy > register access clock to using the clk_bulk interfaces. > > Newer SoCs like Google Tensor gs101 require additional clocks for > access to additional (different) register areas (PHY, PMA, PCS), and > converting to clk_bulk simplifies addition of those extra clocks. > > Signed-off-by: André Draszik Tested-by: Will McVicker [...] Thanks, Will