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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7065124dd1bsm1989696b3a.108.2024.06.21.17.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 17:07:48 -0700 (PDT) Date: Fri, 21 Jun 2024 17:07:44 -0700 From: William McVicker To: =?iso-8859-1?Q?Andr=E9?= Draszik Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , Marek Szyprowski , Sylwester Nawrocki , Alim Akhtar , Sam Protsenko , Krzysztof Kozlowski , Tudor Ambarus , Roy Luo , kernel-team@android.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: Re: [PATCH v3 6/6] phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS) Message-ID: References: <20240617-usb-phy-gs101-v3-0-b66de9ae7424@linaro.org> <20240617-usb-phy-gs101-v3-6-b66de9ae7424@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240617-usb-phy-gs101-v3-6-b66de9ae7424@linaro.org> On 06/17/2024, André Draszik wrote: > Add support for the Exynos USB 3.1 DRD combo phy, as found in Exynos 9 > SoCs like Google GS101. It supports USB SS, HS and DisplayPort. > > In terms of UTMI+, this is very similar to the existing Exynos850 > support in this driver. The difference is that this combo phy supports > both UTMI+ (HS) and PIPE3 (SS). It also supports DP alt mode. > > The number of ports for UTMI+ and PIPE3 can be determined using the > LINKPORT register (which also exists on Exynos E850). > > For SuperSpeed (SS) a new SS phy is in use and its PIPE3 interface is > new compared to Exynos E850, and also very different from the existing > support for older Exynos SoCs in this driver. > > The SS phy needs a bit more configuration work and register tuning for > signal quality to work reliably, presumably due to the higher > frequency, e.g. to account for different board layouts. Additionally, > power needs to be enabled before writing to the SS phy registers. > > This commit adds the necessary changes for USB HS and SS to work. > DisplayPort is out of scope in this commit. > > Notes: > * For the register tuning, exynos5_usbdrd_apply_phy_tunes() has been > added with the appropriate data structures to support tuning at > various stages during initialisation. Since these are hardware > specific, the platform data is supposed to be populated accordingly. > The implementation is loosely modelled after the Samsung UFS PHY > driver. > > There is one tuning state for UTMI+, PTS_UTMI_POSTINIT, to execute > after init and generally intended for HS signal tuning, as done in > this commit. > > PTS_PIPE3_PREINIT PTS_PIPE3_INIT PTS_PIPE3_POSTINIT > PTS_PIPE3_POSTLOCK are tuning states for PIPE3. In the downstream > driver, preinit differs by Exynos SoC, and postinit and postlock > are different per board. The latter haven't been implemented for > gs101 here, because downstream doesn't use them on gs101 either. > > * Signal lock acquisition for SS depends on the orientation of the > USB-C plug. Since there currently is no infrastructure to chain > connector events to both the USB DWC3 driver and this phy driver, a > work-around has been added in > exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock() to check both > registers if it failed in one of the orientations. > > * Equally, we can only establish SS speed in one of the connector > orientations due to programming differences when selecting the lane > mux in exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel(), which really > needs to be dynamic, based on the orientation of the connector. > > * As is, we can establish a HS link using any cable, and an SS link in > one orientation of the plug, falling back to HS if the orientation is > reversed to the expectation. > > Signed-off-by: André Draszik Tested-by: Will McVicker [...] Thanks, Will