* [PATCH v5 01/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
@ 2024-06-07 11:14 ` Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 02/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names Niklas Cassel
` (13 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-07 11:14 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Niklas Cassel,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the
reg-name "apb" for the device tree binding in Root Complex mode
(snps,dw-pcie.yaml), it doesn't make sense that those drivers should use a
different reg-name when running in Endpoint mode (snps,dw-pcie-ep.yaml).
Therefore, since "apb" is already defined in snps,dw-pcie.yaml, add it
also for snps,dw-pcie-ep.yaml.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
index bbdb01d22848..00dec01f1f73 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
@@ -100,7 +100,7 @@ properties:
for new bindings.
oneOf:
- description: See native 'elbi/app' CSR region for details.
- enum: [ link, appl ]
+ enum: [ apb, link, appl ]
- description: See native 'atu' CSR region for details.
enum: [ atu_dma ]
allOf:
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 02/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 01/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name Niklas Cassel
@ 2024-06-07 11:14 ` Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 03/13] dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy irqs Niklas Cassel
` (12 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-07 11:14 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Niklas Cassel,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the
interrupt-names "sys", "pmc", "msg", "err" for the device tree binding in
Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those
drivers should use different interrupt-names when running in Endpoint mode
(snps,dw-pcie-ep.yaml).
Therefore, since "sys", "pmc", "msg", "err" are already defined in
snps,dw-pcie.yaml, add them also for snps,dw-pcie-ep.yaml.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
index 00dec01f1f73..f5f12cbc2cb3 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
@@ -156,7 +156,7 @@ properties:
for new bindings.
oneOf:
- description: See native "app" IRQ for details
- enum: [ intr ]
+ enum: [ intr, sys, pmc, msg, err ]
max-functions:
maximum: 32
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 03/13] dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy irqs
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 01/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 02/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names Niklas Cassel
@ 2024-06-07 11:14 ` Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 04/13] dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support Niklas Cassel
` (11 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-07 11:14 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Niklas Cassel,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
The DWC core has four interrupt signals: tx_inta, tx_intb, tx_intc, tx_intd
that are triggered when the PCIe controller (when running in Endpoint mode)
has sent an Assert_INTA Message to the upstream device.
Some DWC controllers have these interrupt in a combined interrupt signal.
Add the description of these interrupts to the device tree binding.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
index f5f12cbc2cb3..f474b9e3fc7e 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
@@ -151,6 +151,15 @@ properties:
Application-specific IRQ raised depending on the vendor-specific
events basis.
const: app
+ - description:
+ Interrupts triggered when the controller itself (in Endpoint mode)
+ has sent an Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message to
+ the upstream device.
+ pattern: "^tx_int(a|b|c|d)$"
+ - description:
+ Combined interrupt signal raised when the controller has sent an
+ Assert_INT{A,B,C,D} message. See "^tx_int(a|b|c|d)$" for details.
+ const: legacy
- description:
Vendor-specific IRQ names. Consider using the generic names above
for new bindings.
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 04/13] dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
` (2 preceding siblings ...)
2024-06-07 11:14 ` [PATCH v5 03/13] dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy irqs Niklas Cassel
@ 2024-06-07 11:14 ` Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 05/13] dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy irq Niklas Cassel
` (10 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-07 11:14 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Niklas Cassel,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
Refactor the rockchip-dw-pcie binding to move generic properties to a new
rockchip-dw-pcie-common binding that can be shared by both RC and EP mode.
No functional change intended.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../bindings/pci/rockchip-dw-pcie-common.yaml | 111 +++++++++++++++++++++
.../devicetree/bindings/pci/rockchip-dw-pcie.yaml | 93 +----------------
2 files changed, 114 insertions(+), 90 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
new file mode 100644
index 000000000000..60d190a77580
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
+
+maintainers:
+ - Shawn Lin <shawn.lin@rock-chips.com>
+ - Simon Xue <xxm@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |+
+ Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
+ SoCs.
+
+properties:
+ clocks:
+ minItems: 5
+ items:
+ - description: AHB clock for PCIe master
+ - description: AHB clock for PCIe slave
+ - description: AHB clock for PCIe dbi
+ - description: APB clock for PCIe
+ - description: Auxiliary clock for PCIe
+ - description: PIPE clock
+ - description: Reference clock for PCIe
+
+ clock-names:
+ minItems: 5
+ items:
+ - const: aclk_mst
+ - const: aclk_slv
+ - const: aclk_dbi
+ - const: pclk
+ - const: aux
+ - const: pipe
+ - const: ref
+
+ interrupts:
+ items:
+ - description:
+ Combined system interrupt, which is used to signal the following
+ interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
+ hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
+ edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
+ - description:
+ Combined PM interrupt, which is used to signal the following
+ interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
+ linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
+ linkst_out_l0s, pm_dstate_update
+ - description:
+ Combined message interrupt, which is used to signal the following
+ interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
+ pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
+ - description:
+ Combined legacy interrupt, which is used to signal the following
+ interrupts - inta, intb, intc, intd
+ - description:
+ Combined error interrupt, which is used to signal the following
+ interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
+ tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
+ nf_err_rx, f_err_rx, radm_qoverflow
+
+ interrupt-names:
+ items:
+ - const: sys
+ - const: pmc
+ - const: msg
+ - const: legacy
+ - const: err
+
+ num-lanes: true
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: pcie-phy
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ oneOf:
+ - const: pipe
+ - items:
+ - const: pwr
+ - const: pipe
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - num-lanes
+ - phys
+ - phy-names
+ - power-domains
+ - resets
+ - reset-names
+
+additionalProperties: true
+
+...
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
index 5f719218c472..550d8a684af3 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: DesignWare based PCIe controller on Rockchip SoCs
+title: DesignWare based PCIe Root Complex controller on Rockchip SoCs
maintainers:
- Shawn Lin <shawn.lin@rock-chips.com>
@@ -12,12 +12,13 @@ maintainers:
- Heiko Stuebner <heiko@sntech.de>
description: |+
- RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
+ RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
PCIe IP and thus inherits all the common properties defined in
snps,dw-pcie.yaml.
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
+ - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
properties:
compatible:
@@ -40,61 +41,6 @@ properties:
- const: apb
- const: config
- clocks:
- minItems: 5
- items:
- - description: AHB clock for PCIe master
- - description: AHB clock for PCIe slave
- - description: AHB clock for PCIe dbi
- - description: APB clock for PCIe
- - description: Auxiliary clock for PCIe
- - description: PIPE clock
- - description: Reference clock for PCIe
-
- clock-names:
- minItems: 5
- items:
- - const: aclk_mst
- - const: aclk_slv
- - const: aclk_dbi
- - const: pclk
- - const: aux
- - const: pipe
- - const: ref
-
- interrupts:
- items:
- - description:
- Combined system interrupt, which is used to signal the following
- interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
- hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
- edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
- - description:
- Combined PM interrupt, which is used to signal the following
- interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
- linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
- linkst_out_l0s, pm_dstate_update
- - description:
- Combined message interrupt, which is used to signal the following
- interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
- pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
- - description:
- Combined legacy interrupt, which is used to signal the following
- interrupts - inta, intb, intc, intd
- - description:
- Combined error interrupt, which is used to signal the following
- interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
- tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
- nf_err_rx, f_err_rx, radm_qoverflow
-
- interrupt-names:
- items:
- - const: sys
- - const: pmc
- - const: msg
- - const: legacy
- - const: err
-
legacy-interrupt-controller:
description: Interrupt controller node for handling legacy PCI interrupts.
type: object
@@ -119,47 +65,14 @@ properties:
msi-map: true
- num-lanes: true
-
- phys:
- maxItems: 1
-
- phy-names:
- const: pcie-phy
-
- power-domains:
- maxItems: 1
-
ranges:
minItems: 2
maxItems: 3
- resets:
- minItems: 1
- maxItems: 2
-
- reset-names:
- oneOf:
- - const: pipe
- - items:
- - const: pwr
- - const: pipe
-
vpcie3v3-supply: true
required:
- - compatible
- - reg
- - reg-names
- - clocks
- - clock-names
- msi-map
- - num-lanes
- - phys
- - phy-names
- - power-domains
- - resets
- - reset-names
unevaluatedProperties: false
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 05/13] dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy irq
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
` (3 preceding siblings ...)
2024-06-07 11:14 ` [PATCH v5 04/13] dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support Niklas Cassel
@ 2024-06-07 11:14 ` Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 06/13] dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller Niklas Cassel
` (9 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-07 11:14 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Niklas Cassel,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
The descriptions of the combined interrupt signals (level1) mention
all the lower interrupt signals (level2) for each combined interrupt,
regardless if the lower (level2) signal is RC or EP specific.
E.g. the description of "Combined system interrupt" includes rbar_update,
which is EP specific, and the description of "Combined message interrupt"
includes obff_idle, obff_obff, obff_cpu_active, which are all EP specific.
The only exception is the "Combined legacy interrupt", which for some
reason does not provide an exhaustive list of the lower (level2) signals.
Add the missing lower interrupt signals: tx_inta, tx_intb, tx_intc, and
tx_intd for the "Combined legacy interrupt", as per the rk3568 and rk3588
Technical Reference Manuals, such that the descriptions of the combined
interrupt signals are consistent.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
index 60d190a77580..ec5e6a3d048e 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
@@ -56,7 +56,8 @@ properties:
pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
- description:
Combined legacy interrupt, which is used to signal the following
- interrupts - inta, intb, intc, intd
+ interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc,
+ tx_intd
- description:
Combined error interrupt, which is used to signal the following
interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 06/13] dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
` (4 preceding siblings ...)
2024-06-07 11:14 ` [PATCH v5 05/13] dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy irq Niklas Cassel
@ 2024-06-07 11:14 ` Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 07/13] PCI: dw-rockchip: Fix weird indentation Niklas Cassel
` (8 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-07 11:14 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Niklas Cassel,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
Document DT bindings for PCIe Endpoint controller found in Rockchip SoCs.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../bindings/pci/rockchip-dw-pcie-common.yaml | 14 ++++
.../bindings/pci/rockchip-dw-pcie-ep.yaml | 95 ++++++++++++++++++++++
2 files changed, 109 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
index ec5e6a3d048e..cc9adfc7611c 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
@@ -39,6 +39,7 @@ properties:
- const: ref
interrupts:
+ minItems: 5
items:
- description:
Combined system interrupt, which is used to signal the following
@@ -63,14 +64,27 @@ properties:
interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
nf_err_rx, f_err_rx, radm_qoverflow
+ - description:
+ eDMA write channel 0 interrupt
+ - description:
+ eDMA write channel 1 interrupt
+ - description:
+ eDMA read channel 0 interrupt
+ - description:
+ eDMA read channel 1 interrupt
interrupt-names:
+ minItems: 5
items:
- const: sys
- const: pmc
- const: msg
- const: legacy
- const: err
+ - const: dma0
+ - const: dma1
+ - const: dma2
+ - const: dma3
num-lanes: true
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml
new file mode 100644
index 000000000000..f2d1137aff50
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DesignWare based PCIe Endpoint controller on Rockchip SoCs
+
+maintainers:
+ - Niklas Cassel <cassel@kernel.org>
+
+description: |+
+ RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare
+ PCIe IP and thus inherits all the common properties defined in
+ snps,dw-pcie-ep.yaml.
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
+ - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-pcie-ep
+ - rockchip,rk3588-pcie-ep
+
+ reg:
+ items:
+ - description: Data Bus Interface (DBI) registers
+ - description: Data Bus Interface (DBI) shadow registers
+ - description: Rockchip designed configuration registers
+ - description: Memory region used to map remote RC address space
+ - description: Internal Address Translation Unit (iATU) registers
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: dbi2
+ - const: apb
+ - const: addr_space
+ - const: atu
+
+required:
+ - interrupts
+ - interrupt-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/rk3588-power.h>
+ #include <dt-bindings/reset/rockchip,rk3588-cru.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie3x4_ep: pcie-ep@fe150000 {
+ compatible = "rockchip,rk3588-pcie-ep";
+ reg = <0xa 0x40000000 0x0 0x00100000>,
+ <0xa 0x40100000 0x0 0x00100000>,
+ <0x0 0xfe150000 0x0 0x00010000>,
+ <0x9 0x00000000 0x0 0x40000000>,
+ <0xa 0x40300000 0x0 0x00100000>;
+ reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err",
+ "dma0", "dma1", "dma2", "dma3";
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ reset-names = "pwr", "pipe";
+ };
+ };
+...
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 07/13] PCI: dw-rockchip: Fix weird indentation
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
` (5 preceding siblings ...)
2024-06-07 11:14 ` [PATCH v5 06/13] dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller Niklas Cassel
@ 2024-06-07 11:14 ` Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 08/13] PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper Niklas Cassel
` (7 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-07 11:14 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Niklas Cassel,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
Fix the indentation of rockchip_pcie_{readl,writel}_apb() parameters to
match the opening parenthesis.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 61b1acba7182..3dfed08ef456 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -60,14 +60,13 @@ struct rockchip_pcie {
struct irq_domain *irq_domain;
};
-static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip,
- u32 reg)
+static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg)
{
return readl_relaxed(rockchip->apb_base + reg);
}
-static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip,
- u32 val, u32 reg)
+static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, u32 val,
+ u32 reg)
{
writel_relaxed(val, rockchip->apb_base + reg);
}
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 08/13] PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
` (6 preceding siblings ...)
2024-06-07 11:14 ` [PATCH v5 07/13] PCI: dw-rockchip: Fix weird indentation Niklas Cassel
@ 2024-06-07 11:14 ` Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 09/13] PCI: dw-rockchip: Refactor the driver to prepare for EP mode Niklas Cassel
` (6 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-07 11:14 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Niklas Cassel,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
Add a rockchip_pcie_ltssm() helper function that reads the LTSSM status.
This helper will be used in additional places in follow-up commits.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 3dfed08ef456..1380e3a5284b 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -143,6 +143,11 @@ static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
return 0;
}
+static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip)
+{
+ return rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS);
+}
+
static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
{
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
@@ -152,7 +157,7 @@ static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
static int rockchip_pcie_link_up(struct dw_pcie *pci)
{
struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
- u32 val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS);
+ u32 val = rockchip_pcie_get_ltssm(rockchip);
if ((val & PCIE_LINKUP) == PCIE_LINKUP &&
(val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY)
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 09/13] PCI: dw-rockchip: Refactor the driver to prepare for EP mode
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
` (7 preceding siblings ...)
2024-06-07 11:14 ` [PATCH v5 08/13] PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper Niklas Cassel
@ 2024-06-07 11:14 ` Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 10/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
` (5 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-07 11:14 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Niklas Cassel,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
This refactors the driver to prepare for EP mode.
Add of-match data to the existing compatible, and explicitly define it as
DW_PCIE_RC_TYPE. This way, we will be able to add EP mode in a follow-up
commit in a much less intrusive way, which makes the follup-up commit much
easier to review.
No functional change intended.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 84 +++++++++++++++++++--------
1 file changed, 60 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 1380e3a5284b..bd35620b1a96 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -49,15 +49,20 @@
#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
struct rockchip_pcie {
- struct dw_pcie pci;
- void __iomem *apb_base;
- struct phy *phy;
- struct clk_bulk_data *clks;
- unsigned int clk_cnt;
- struct reset_control *rst;
- struct gpio_desc *rst_gpio;
- struct regulator *vpcie3v3;
- struct irq_domain *irq_domain;
+ struct dw_pcie pci;
+ void __iomem *apb_base;
+ struct phy *phy;
+ struct clk_bulk_data *clks;
+ unsigned int clk_cnt;
+ struct reset_control *rst;
+ struct gpio_desc *rst_gpio;
+ struct regulator *vpcie3v3;
+ struct irq_domain *irq_domain;
+ const struct rockchip_pcie_of_data *data;
+};
+
+struct rockchip_pcie_of_data {
+ enum dw_pcie_device_mode mode;
};
static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg)
@@ -195,7 +200,6 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
struct device *dev = rockchip->pci.dev;
- u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
int irq, ret;
irq = of_irq_get_byname(dev->of_node, "legacy");
@@ -209,12 +213,6 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler,
rockchip);
- /* LTSSM enable control mode */
- rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
-
- rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE,
- PCIE_CLIENT_GENERAL_CONTROL);
-
return 0;
}
@@ -294,13 +292,35 @@ static const struct dw_pcie_ops dw_pcie_ops = {
.start_link = rockchip_pcie_start_link,
};
+static int rockchip_pcie_configure_rc(struct rockchip_pcie *rockchip)
+{
+ struct dw_pcie_rp *pp;
+ u32 val;
+
+ /* LTSSM enable control mode */
+ val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
+ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
+
+ rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE,
+ PCIE_CLIENT_GENERAL_CONTROL);
+
+ pp = &rockchip->pci.pp;
+ pp->ops = &rockchip_pcie_host_ops;
+
+ return dw_pcie_host_init(pp);
+}
+
static int rockchip_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct rockchip_pcie *rockchip;
- struct dw_pcie_rp *pp;
+ const struct rockchip_pcie_of_data *data;
int ret;
+ data = of_device_get_match_data(dev);
+ if (!data)
+ return -EINVAL;
+
rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
if (!rockchip)
return -ENOMEM;
@@ -309,9 +329,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
rockchip->pci.dev = dev;
rockchip->pci.ops = &dw_pcie_ops;
-
- pp = &rockchip->pci.pp;
- pp->ops = &rockchip_pcie_host_ops;
+ rockchip->data = data;
ret = rockchip_pcie_resource_get(pdev, rockchip);
if (ret)
@@ -347,10 +365,21 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
if (ret)
goto deinit_phy;
- ret = dw_pcie_host_init(pp);
- if (!ret)
- return 0;
+ switch (data->mode) {
+ case DW_PCIE_RC_TYPE:
+ ret = rockchip_pcie_configure_rc(rockchip);
+ if (ret)
+ goto deinit_clk;
+ break;
+ default:
+ dev_err(dev, "INVALID device type %d\n", data->mode);
+ ret = -EINVAL;
+ goto deinit_clk;
+ }
+
+ return 0;
+deinit_clk:
clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
deinit_phy:
rockchip_pcie_phy_deinit(rockchip);
@@ -361,8 +390,15 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
return ret;
}
+static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = {
+ .mode = DW_PCIE_RC_TYPE,
+};
+
static const struct of_device_id rockchip_pcie_of_match[] = {
- { .compatible = "rockchip,rk3568-pcie", },
+ {
+ .compatible = "rockchip,rk3568-pcie",
+ .data = &rockchip_pcie_rc_of_data_rk3568,
+ },
{},
};
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 10/13] PCI: dw-rockchip: Add endpoint mode support
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
` (8 preceding siblings ...)
2024-06-07 11:14 ` [PATCH v5 09/13] PCI: dw-rockchip: Refactor the driver to prepare for EP mode Niklas Cassel
@ 2024-06-07 11:14 ` Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 11/13] misc: pci_endpoint_test: Add support for rockchip rk3588 Niklas Cassel
` (4 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-07 11:14 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Niklas Cassel,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
The PCIe controller in rk3568 and rk3588 can operate in endpoint mode.
This endpoint mode support heavily leverages the existing code in
pcie-designware-ep.c.
Add support for endpoint mode to the existing pcie-dw-rockchip glue
driver.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/Kconfig | 21 ++-
drivers/pci/controller/dwc/Makefile | 2 +-
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 209 ++++++++++++++++++++++++++
3 files changed, 227 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index 8afacc90c63b..9c4fb8ba7573 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -311,16 +311,29 @@ config PCIE_RCAR_GEN4_EP
SoCs. To compile this driver as a module, choose M here: the module
will be called pcie-rcar-gen4.ko. This uses the DesignWare core.
+config PCIE_ROCKCHIP_DW
+ bool
+
config PCIE_ROCKCHIP_DW_HOST
- bool "Rockchip DesignWare PCIe controller"
- select PCIE_DW
- select PCIE_DW_HOST
+ bool "Rockchip DesignWare PCIe controller (host mode)"
depends on PCI_MSI
depends on ARCH_ROCKCHIP || COMPILE_TEST
depends on OF
+ select PCIE_DW_HOST
+ select PCIE_ROCKCHIP_DW
+ help
+ Enables support for the DesignWare PCIe controller in the
+ Rockchip SoC (except RK3399) to work in host mode.
+
+config PCIE_ROCKCHIP_DW_EP
+ bool "Rockchip DesignWare PCIe controller (endpoint mode)"
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
+ depends on OF
+ select PCIE_DW_EP
+ select PCIE_ROCKCHIP_DW
help
Enables support for the DesignWare PCIe controller in the
- Rockchip SoC except RK3399.
+ Rockchip SoC (except RK3399) to work in endpoint mode.
config PCI_EXYNOS
tristate "Samsung Exynos PCIe controller"
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index bac103faa523..ec215b3d6191 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o
obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
-obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o
+obj-$(CONFIG_PCIE_ROCKCHIP_DW) += pcie-dw-rockchip.o
obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o
obj-$(CONFIG_PCIE_KEEMBAY) += pcie-keembay.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index bd35620b1a96..0a0fdfc66b91 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -34,10 +34,16 @@
#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40)
+#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0)
#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc)
+#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8)
+#define PCIE_CLIENT_INTR_STATUS_MISC 0x10
+#define PCIE_CLIENT_INTR_MASK_MISC 0x24
#define PCIE_SMLH_LINKUP BIT(16)
#define PCIE_RDLH_LINKUP BIT(17)
#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
+#define PCIE_RDLH_LINK_UP_CHGED BIT(1)
+#define PCIE_LINK_REQ_RST_NOT_INT BIT(2)
#define PCIE_L0S_ENTRY 0x11
#define PCIE_CLIENT_GENERAL_CONTROL 0x0
#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
@@ -63,6 +69,7 @@ struct rockchip_pcie {
struct rockchip_pcie_of_data {
enum dw_pcie_device_mode mode;
+ const struct pci_epc_features *epc_features;
};
static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg)
@@ -159,6 +166,12 @@ static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
PCIE_CLIENT_GENERAL_CONTROL);
}
+static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip)
+{
+ rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM,
+ PCIE_CLIENT_GENERAL_CONTROL);
+}
+
static int rockchip_pcie_link_up(struct dw_pcie *pci)
{
struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
@@ -195,6 +208,13 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci)
return 0;
}
+static void rockchip_pcie_stop_link(struct dw_pcie *pci)
+{
+ struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
+
+ rockchip_pcie_disable_ltssm(rockchip);
+}
+
static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
@@ -220,6 +240,82 @@ static const struct dw_pcie_host_ops rockchip_pcie_host_ops = {
.init = rockchip_pcie_host_init,
};
+static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ enum pci_barno bar;
+
+ for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
+ dw_pcie_ep_reset_bar(pci, bar);
+};
+
+static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
+ unsigned int type, u16 interrupt_num)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+ switch (type) {
+ case PCI_IRQ_INTX:
+ return dw_pcie_ep_raise_intx_irq(ep, func_no);
+ case PCI_IRQ_MSI:
+ return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
+ case PCI_IRQ_MSIX:
+ return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
+ default:
+ dev_err(pci->dev, "UNKNOWN IRQ type\n");
+ }
+
+ return 0;
+}
+
+static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
+ .linkup_notifier = true,
+ .msi_capable = true,
+ .msix_capable = true,
+ .align = SZ_64K,
+ .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+ .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+ .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+ .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+ .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+ .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+};
+
+/*
+ * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of
+ * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver,
+ * so mark it as RESERVED. (rockchip_pcie_ep_init() will disable all BARs by
+ * default.) If the host could write to BAR4, the iATU settings (for all other
+ * BARs) would be overwritten, resulting in (all other BARs) no longer working.
+ */
+static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {
+ .linkup_notifier = true,
+ .msi_capable = true,
+ .msix_capable = true,
+ .align = SZ_64K,
+ .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+ .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+ .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+ .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+ .bar[BAR_4] = { .type = BAR_RESERVED, },
+ .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },
+};
+
+static const struct pci_epc_features *
+rockchip_pcie_get_features(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
+
+ return rockchip->data->epc_features;
+}
+
+static const struct dw_pcie_ep_ops rockchip_pcie_ep_ops = {
+ .init = rockchip_pcie_ep_init,
+ .raise_irq = rockchip_pcie_raise_irq,
+ .get_features = rockchip_pcie_get_features,
+};
+
static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip)
{
struct device *dev = rockchip->pci.dev;
@@ -290,13 +386,46 @@ static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip)
static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = rockchip_pcie_link_up,
.start_link = rockchip_pcie_start_link,
+ .stop_link = rockchip_pcie_stop_link,
};
+static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
+{
+ struct rockchip_pcie *rockchip = arg;
+ struct dw_pcie *pci = &rockchip->pci;
+ struct device *dev = pci->dev;
+ u32 reg, val;
+
+ reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
+ rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
+
+ dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg);
+ dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));
+
+ if (reg & PCIE_LINK_REQ_RST_NOT_INT) {
+ dev_dbg(dev, "hot reset or link-down reset\n");
+ dw_pcie_ep_linkdown(&pci->ep);
+ }
+
+ if (reg & PCIE_RDLH_LINK_UP_CHGED) {
+ val = rockchip_pcie_get_ltssm(rockchip);
+ if ((val & PCIE_LINKUP) == PCIE_LINKUP) {
+ dev_dbg(dev, "link up\n");
+ dw_pcie_ep_linkup(&pci->ep);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
static int rockchip_pcie_configure_rc(struct rockchip_pcie *rockchip)
{
struct dw_pcie_rp *pp;
u32 val;
+ if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST))
+ return -ENODEV;
+
/* LTSSM enable control mode */
val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
@@ -310,6 +439,63 @@ static int rockchip_pcie_configure_rc(struct rockchip_pcie *rockchip)
return dw_pcie_host_init(pp);
}
+static int rockchip_pcie_configure_ep(struct platform_device *pdev,
+ struct rockchip_pcie *rockchip)
+{
+ struct device *dev = &pdev->dev;
+ int irq, ret;
+ u32 val;
+
+ if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP))
+ return -ENODEV;
+
+ irq = platform_get_irq_byname(pdev, "sys");
+ if (irq < 0) {
+ dev_err(dev, "missing sys IRQ resource\n");
+ return irq;
+ }
+
+ ret = devm_request_threaded_irq(dev, irq, NULL,
+ rockchip_pcie_ep_sys_irq_thread,
+ IRQF_ONESHOT, "pcie-sys", rockchip);
+ if (ret) {
+ dev_err(dev, "failed to request PCIe sys IRQ\n");
+ return ret;
+ }
+
+ /* LTSSM enable control mode */
+ val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
+ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
+
+ rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE,
+ PCIE_CLIENT_GENERAL_CONTROL);
+
+ rockchip->pci.ep.ops = &rockchip_pcie_ep_ops;
+ rockchip->pci.ep.page_size = SZ_64K;
+
+ dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
+
+ ret = dw_pcie_ep_init(&rockchip->pci.ep);
+ if (ret) {
+ dev_err(dev, "failed to initialize endpoint\n");
+ return ret;
+ }
+
+ ret = dw_pcie_ep_init_registers(&rockchip->pci.ep);
+ if (ret) {
+ dev_err(dev, "failed to initialize DWC endpoint registers\n");
+ dw_pcie_ep_deinit(&rockchip->pci.ep);
+ return ret;
+ }
+
+ dw_pcie_ep_init_notify(&rockchip->pci.ep);
+
+ /* unmask DLL up/down indicator and hot reset/link-down reset */
+ rockchip_pcie_writel_apb(rockchip, 0x60000, PCIE_CLIENT_INTR_MASK_MISC);
+
+ return ret;
+}
+
static int rockchip_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -371,6 +557,11 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
if (ret)
goto deinit_clk;
break;
+ case DW_PCIE_EP_TYPE:
+ ret = rockchip_pcie_configure_ep(pdev, rockchip);
+ if (ret)
+ goto deinit_clk;
+ break;
default:
dev_err(dev, "INVALID device type %d\n", data->mode);
ret = -EINVAL;
@@ -394,11 +585,29 @@ static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = {
.mode = DW_PCIE_RC_TYPE,
};
+static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3568 = {
+ .mode = DW_PCIE_EP_TYPE,
+ .epc_features = &rockchip_pcie_epc_features_rk3568,
+};
+
+static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3588 = {
+ .mode = DW_PCIE_EP_TYPE,
+ .epc_features = &rockchip_pcie_epc_features_rk3588,
+};
+
static const struct of_device_id rockchip_pcie_of_match[] = {
{
.compatible = "rockchip,rk3568-pcie",
.data = &rockchip_pcie_rc_of_data_rk3568,
},
+ {
+ .compatible = "rockchip,rk3568-pcie-ep",
+ .data = &rockchip_pcie_ep_of_data_rk3568,
+ },
+ {
+ .compatible = "rockchip,rk3588-pcie-ep",
+ .data = &rockchip_pcie_ep_of_data_rk3588,
+ },
{},
};
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 11/13] misc: pci_endpoint_test: Add support for rockchip rk3588
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
` (9 preceding siblings ...)
2024-06-07 11:14 ` [PATCH v5 10/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
@ 2024-06-07 11:14 ` Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 12/13] arm64: dts: rockchip: Add PCIe endpoint mode support Niklas Cassel
` (3 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-07 11:14 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Niklas Cassel,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
Rockchip rk3588 requires 64k alignment.
While there is an existing device_id:vendor_id in the driver with 64k
alignment, that device_id:vendor_id is am654, which uses BAR2 instead of
BAR0 as the test_reg_bar, and also has special is_am654_pci_dev() checks
in the driver to disallow BAR0. In order to allow testing all BARs, add a
new rk3588 entry in the driver.
We intentionally do not add the vendor id to pci_ids.h, since the policy
for that file is that the vendor id has to be used by multiple drivers.
Hopefully, this new entry will be short-lived, as there is a series on the
mailing list which intends to move the address alignment restrictions from
this driver to the endpoint side.
Add a new entry for rk3588 in order to allow us to test all BARs.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/misc/pci_endpoint_test.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 4f3ec1f2ba9f..0ffc8e02b863 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -85,6 +85,9 @@
#define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
#define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031
+#define PCI_VENDOR_ID_ROCKCHIP 0x1d87
+#define PCI_DEVICE_ID_ROCKCHIP_RK3588 0x3588
+
static DEFINE_IDA(pci_endpoint_test_ida);
#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
@@ -1006,6 +1009,11 @@ static const struct pci_endpoint_test_data j721e_data = {
.irq_type = IRQ_TYPE_MSI,
};
+static const struct pci_endpoint_test_data rk3588_data = {
+ .alignment = SZ_64K,
+ .irq_type = IRQ_TYPE_MSI,
+};
+
static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
.driver_data = (kernel_ulong_t)&default_data,
@@ -1043,6 +1051,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721S2),
.driver_data = (kernel_ulong_t)&j721e_data,
},
+ { PCI_DEVICE(PCI_VENDOR_ID_ROCKCHIP, PCI_DEVICE_ID_ROCKCHIP_RK3588),
+ .driver_data = (kernel_ulong_t)&rk3588_data,
+ },
{ }
};
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 12/13] arm64: dts: rockchip: Add PCIe endpoint mode support
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
` (10 preceding siblings ...)
2024-06-07 11:14 ` [PATCH v5 11/13] misc: pci_endpoint_test: Add support for rockchip rk3588 Niklas Cassel
@ 2024-06-07 11:14 ` Niklas Cassel
2024-06-07 11:14 ` [PATCH v5 13/13] arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode Niklas Cassel
` (2 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-07 11:14 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Niklas Cassel,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
Add a device tree node representing PCIe endpoint mode.
The controller can either be configured to run in Root Complex or Endpoint
node.
If a user wants to run the controller in endpoint mode, the user has to
disable the pcie3x4 node and enable the pcie3x4_ep node.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/rockchip/rk3588.dtsi | 35 ++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index 5984016b5f96..a88f5a9b6d66 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -186,6 +186,41 @@ pcie3x4_intc: legacy-interrupt-controller {
};
};
+ pcie3x4_ep: pcie-ep@fe150000 {
+ compatible = "rockchip,rk3588-pcie-ep";
+ reg = <0xa 0x40000000 0x0 0x00100000>,
+ <0xa 0x40100000 0x0 0x00100000>,
+ <0x0 0xfe150000 0x0 0x00010000>,
+ <0x9 0x00000000 0x0 0x40000000>,
+ <0xa 0x40300000 0x0 0x00100000>;
+ reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err",
+ "dma0", "dma1", "dma2", "dma3";
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ reset-names = "pwr", "pipe";
+ status = "disabled";
+ };
+
pcie3x2: pcie@fe160000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
#address-cells = <3>;
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 13/13] arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
` (11 preceding siblings ...)
2024-06-07 11:14 ` [PATCH v5 12/13] arm64: dts: rockchip: Add PCIe endpoint mode support Niklas Cassel
@ 2024-06-07 11:14 ` Niklas Cassel
2024-06-17 8:00 ` [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
2024-06-26 15:32 ` (subset) " Heiko Stuebner
14 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-07 11:14 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Niklas Cassel,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
Add rock5b overlays for PCIe endpoint mode support.
If using the rock5b as an endpoint against a normal PC, only the
rk3588-rock-5b-pcie-ep.dtbo needs to be applied.
If using two rock5b:s, with one board as EP and the other board as RC,
rk3588-rock-5b-pcie-ep.dtbo and rk3588-rock-5b-pcie-srns.dtbo has to
be applied to the respective boards.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
arch/arm64/boot/dts/rockchip/Makefile | 5 +++++
.../boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso | 25 ++++++++++++++++++++++
.../dts/rockchip/rk3588-rock-5b-pcie-srns.dtso | 16 ++++++++++++++
3 files changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index f42fa62b4064..df7f5103b018 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -124,6 +124,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb
@@ -134,3 +136,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb
+
+# Enable support for device-tree overlays
+DTC_FLAGS_rk3588-rock-5b += -@
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso
new file mode 100644
index 000000000000..672d748fcc67
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode
+ * in the SRNS (Separate Reference Clock No Spread) configuration.
+ *
+ * NOTE: If using a setup with two ROCK 5B:s, with one board running in
+ * RC mode and the other board running in EP mode, see also the device
+ * tree overlay: rk3588-rock-5b-pcie-srns.dtso.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&pcie30phy {
+ rockchip,rx-common-refclk-mode = <0 0 0 0>;
+};
+
+&pcie3x4 {
+ status = "disabled";
+};
+
+&pcie3x4_ep {
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso
new file mode 100644
index 000000000000..1a0f1af65c43
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex
+ * mode in the SRNS (Separate Reference Clock No Spread) configuration.
+ *
+ * This device tree overlay is only needed (on the RC side) when running
+ * a setup with two ROCK 5B:s, with one board running in RC mode and the
+ * other board running in EP mode.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&pcie30phy {
+ rockchip,rx-common-refclk-mode = <0 0 0 0>;
+};
--
2.45.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
` (12 preceding siblings ...)
2024-06-07 11:14 ` [PATCH v5 13/13] arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode Niklas Cassel
@ 2024-06-17 8:00 ` Niklas Cassel
2024-06-21 19:39 ` Krzysztof Wilczyński
2024-06-26 15:32 ` (subset) " Heiko Stuebner
14 siblings, 1 reply; 22+ messages in thread
From: Niklas Cassel @ 2024-06-17 8:00 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue
Cc: linux-pci, devicetree, linux-rockchip
On Fri, Jun 07, 2024 at 01:14:20PM +0200, Niklas Cassel wrote:
> Hello all,
>
> This series adds PCIe endpoint mode support for the rockchip rk3588 and
> rk3568 SoCs.
>
> This series is based on: pci/next
> (git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git)
>
> This series can also be found in git:
> https://github.com/floatious/linux/commits/rockchip-pcie-ep-v5
>
> Testing done:
> This series has been tested with two rock5b:s, one running in RC mode and
> one running in EP mode. This series has also been tested with an Intel x86
> host and rock5b running in EP mode.
(snip)
Hello PCI maintainers,
If there is anything more I can do to get this picked up, please tell me.
Kind regards,
Niklas
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support
2024-06-17 8:00 ` [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
@ 2024-06-21 19:39 ` Krzysztof Wilczyński
2024-06-22 12:10 ` Niklas Cassel
2024-06-22 13:39 ` Niklas Cassel
0 siblings, 2 replies; 22+ messages in thread
From: Krzysztof Wilczyński @ 2024-06-21 19:39 UTC (permalink / raw)
To: Niklas Cassel
Cc: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, Kishon Vijay Abraham I, Arnd Bergmann,
Damien Le Moal, Jon Lin, Shawn Lin, Simon Xue, linux-pci,
devicetree, linux-rockchip
Hello,
[...]
> If there is anything more I can do to get this picked up, please tell me.
Looks good! As such...
Applied to dt-bindings, thank you!
[01/06] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name
https://git.kernel.org/pci/pci/c/3b287269ab60
[02/06] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names
https://git.kernel.org/pci/pci/c/b96353773d24
[03/06] dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy IRQs
https://git.kernel.org/pci/pci/c/6f308c017c27
[04/06] dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support
https://git.kernel.org/pci/pci/c/9b0b9b588c00
[05/06] dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy IRQ
https://git.kernel.org/pci/pci/c/5f262f67cbc5
[06/06] dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller
https://git.kernel.org/pci/pci/c/ff36edde817e
Applied to controller/rockchip, thank you!
[01/04] PCI: dw-rockchip: Fix weird indentation
https://git.kernel.org/pci/pci/c/e7e8872191af
[02/04] PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper
https://git.kernel.org/pci/pci/c/cbb2d4ae3fdc
[03/04] PCI: dw-rockchip: Add endpoint mode support
https://git.kernel.org/pci/pci/c/67fe449bcd85
[04/04] PCI: dw-rockchip: Refactor the driver to prepare for EP mode
https://git.kernel.org/pci/pci/c/ecdc98a3a912
Applied to endpoint, thank you!
[1/1] misc: pci_endpoint_test: Add support for Rockchip rk3588
https://git.kernel.org/pci/pci/c/657463e393d1
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support
2024-06-21 19:39 ` Krzysztof Wilczyński
@ 2024-06-22 12:10 ` Niklas Cassel
2024-06-22 13:39 ` Niklas Cassel
1 sibling, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-22 12:10 UTC (permalink / raw)
To: Krzysztof Wilczyński, Heiko Stuebner
Cc: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kishon Vijay Abraham I, Arnd Bergmann, Damien Le Moal, Jon Lin,
Shawn Lin, Simon Xue, linux-pci, devicetree, linux-rockchip
Krzysztof,
thank you very much for applying!
Heiko,
now when the DT-binding and driver has been queued for 6.11,
is there any chance of getting patches 12/13 and 13/13 applied
to the linux-rockchip tree?
Kind regards,
Niklas
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support
2024-06-21 19:39 ` Krzysztof Wilczyński
2024-06-22 12:10 ` Niklas Cassel
@ 2024-06-22 13:39 ` Niklas Cassel
2024-06-22 15:43 ` Krzysztof Wilczyński
1 sibling, 1 reply; 22+ messages in thread
From: Niklas Cassel @ 2024-06-22 13:39 UTC (permalink / raw)
To: Krzysztof Wilczyński
Cc: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, Kishon Vijay Abraham I, Arnd Bergmann,
Damien Le Moal, Jon Lin, Shawn Lin, Simon Xue, linux-pci,
devicetree, linux-rockchip
On Sat, Jun 22, 2024 at 04:39:37AM +0900, Krzysztof Wilczyński wrote:
> Hello,
>
> [...]
> > If there is anything more I can do to get this picked up, please tell me.
>
> Looks good! As such...
>
> Applied to controller/rockchip, thank you!
>
> [01/04] PCI: dw-rockchip: Fix weird indentation
> https://git.kernel.org/pci/pci/c/e7e8872191af
>
> [02/04] PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper
> https://git.kernel.org/pci/pci/c/cbb2d4ae3fdc
>
> [03/04] PCI: dw-rockchip: Add endpoint mode support
> https://git.kernel.org/pci/pci/c/67fe449bcd85
>
> [04/04] PCI: dw-rockchip: Refactor the driver to prepare for EP mode
> https://git.kernel.org/pci/pci/c/ecdc98a3a912
Krzysztof,
unfortunately, the controller/rockchip branch currently doesn't build:
drivers/pci/controller/dwc/pcie-dw-rockchip.c: In function ‘rockchip_pcie_ep_sys_irq_thread’:
drivers/pci/controller/dwc/pcie-dw-rockchip.c:407:17: error: implicit declaration of function ‘dw_pcie_ep_linkdown’;
did you mean ‘dw_pcie_ep_linkup’? [-Wimplicit-function-declaration]
407 | dw_pcie_ep_linkdown(&pci->ep);
| ^~~~~~~~~~~~~~~~~~~
| dw_pcie_ep_linkup
Could you possibly include the commit:
3d2e425263e2 ("PCI: dwc: ep: Add a generic dw_pcie_ep_linkdown() API to handle Link Down event")
from the controller/dwc branch in the controller/rockchip as well,
or rebase the controller/rockchip branch on top of the controller/dwc branch,
or merge the controller/dwc branch to the controller/rockchip branch?
Additionally, since you picked up Mani's series which removes
dw_pcie_ep_init_notify() on the controller/dwc branch:
9eba2f70362f ("PCI: dwc: ep: Remove dw_pcie_ep_init_notify() wrapper")
You will need to pick up this patch as well:
https://lore.kernel.org/linux-pci/20240622132024.2927799-2-cassel@kernel.org/T/#u
Otherwise there will be a build error when merging the controller/dwc
and the controller/rockchip branch to for-next.
The patch that I sent out can be picked up to the controller/rockchip right
now (since the API that Mani is switching to already exists in Linus's tree).
May I ask why all the branches for the different DWC glue drivers are not
based on the controller/dwc branch?
They are obviously going to be tightly related.
Kind regards,
Niklas
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support
2024-06-22 13:39 ` Niklas Cassel
@ 2024-06-22 15:43 ` Krzysztof Wilczyński
2024-06-22 16:34 ` Niklas Cassel
0 siblings, 1 reply; 22+ messages in thread
From: Krzysztof Wilczyński @ 2024-06-22 15:43 UTC (permalink / raw)
To: Niklas Cassel
Cc: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, Kishon Vijay Abraham I, Arnd Bergmann,
Damien Le Moal, Jon Lin, Shawn Lin, Simon Xue, linux-pci,
devicetree, linux-rockchip
Hello,
[...]
> Could you possibly include the commit:
> 3d2e425263e2 ("PCI: dwc: ep: Add a generic dw_pcie_ep_linkdown() API to handle Link Down event")
> from the controller/dwc branch in the controller/rockchip as well,
> or rebase the controller/rockchip branch on top of the controller/dwc branch,
> or merge the controller/dwc branch to the controller/rockchip branch?
>
Done.
> Additionally, since you picked up Mani's series which removes
> dw_pcie_ep_init_notify() on the controller/dwc branch:
> 9eba2f70362f ("PCI: dwc: ep: Remove dw_pcie_ep_init_notify() wrapper")
>
> You will need to pick up this patch as well:
> https://lore.kernel.org/linux-pci/20240622132024.2927799-2-cassel@kernel.org/T/#u
> Otherwise there will be a build error when merging the controller/dwc
> and the controller/rockchip branch to for-next.
> The patch that I sent out can be picked up to the controller/rockchip right
> now (since the API that Mani is switching to already exists in Linus's tree).
Done.
Hopefully, this settles things for a bit.
> May I ask why all the branches for the different DWC glue drivers are not
> based on the controller/dwc branch?
No worries.
> They are obviously going to be tightly related.
Normally, we prefer to apply things to specific topic branches, but I will
revisit this approach going forward, since changes between Endpoint, DWC
and specific controller drivers are often tightly coupled, as you noted,
which can make things a bit of a mess, unnecessarily.
We are going to do some clean up once Bjorn sends his Pull Request.
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support
2024-06-22 15:43 ` Krzysztof Wilczyński
@ 2024-06-22 16:34 ` Niklas Cassel
0 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-22 16:34 UTC (permalink / raw)
To: Krzysztof Wilczyński
Cc: Jingoo Han, Manivannan Sadhasivam, Bjorn Helgaas,
Lorenzo Pieralisi, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, Kishon Vijay Abraham I, Arnd Bergmann,
Damien Le Moal, Jon Lin, Shawn Lin, Simon Xue, linux-pci,
devicetree, linux-rockchip
On Sun, Jun 23, 2024 at 12:43:24AM +0900, Krzysztof Wilczyński wrote:
> Hello,
>
> [...]
> > Could you possibly include the commit:
> > 3d2e425263e2 ("PCI: dwc: ep: Add a generic dw_pcie_ep_linkdown() API to handle Link Down event")
> > from the controller/dwc branch in the controller/rockchip as well,
> > or rebase the controller/rockchip branch on top of the controller/dwc branch,
> > or merge the controller/dwc branch to the controller/rockchip branch?
> >
>
> Done.
>
> > Additionally, since you picked up Mani's series which removes
> > dw_pcie_ep_init_notify() on the controller/dwc branch:
> > 9eba2f70362f ("PCI: dwc: ep: Remove dw_pcie_ep_init_notify() wrapper")
> >
> > You will need to pick up this patch as well:
> > https://lore.kernel.org/linux-pci/20240622132024.2927799-2-cassel@kernel.org/T/#u
> > Otherwise there will be a build error when merging the controller/dwc
> > and the controller/rockchip branch to for-next.
> > The patch that I sent out can be picked up to the controller/rockchip right
> > now (since the API that Mani is switching to already exists in Linus's tree).
>
> Done.
>
> Hopefully, this settles things for a bit.
Everything looks good! :)
I'm glad that we got this sorted quickly, thank you Krzysztof!
Kind regards,
Niklas
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: (subset) [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support
2024-06-07 11:14 [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
` (13 preceding siblings ...)
2024-06-17 8:00 ` [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
@ 2024-06-26 15:32 ` Heiko Stuebner
2024-06-26 18:13 ` Niklas Cassel
14 siblings, 1 reply; 22+ messages in thread
From: Heiko Stuebner @ 2024-06-26 15:32 UTC (permalink / raw)
To: Simon Xue, Shawn Lin, Arnd Bergmann, Krzysztof Wilczyński,
Kishon Vijay Abraham I, Damien Le Moal, Jon Lin,
Lorenzo Pieralisi, Manivannan Sadhasivam, Krzysztof Kozlowski,
Jingoo Han, Bjorn Helgaas, Conor Dooley, Niklas Cassel,
Rob Herring
Cc: Heiko Stuebner, linux-rockchip, linux-pci, devicetree
On Fri, 07 Jun 2024 13:14:20 +0200, Niklas Cassel wrote:
> This series adds PCIe endpoint mode support for the rockchip rk3588 and
> rk3568 SoCs.
>
> This series is based on: pci/next
> (git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git)
>
> This series can also be found in git:
> https://github.com/floatious/linux/commits/rockchip-pcie-ep-v5
>
> [...]
Applied, thanks!
[12/13] arm64: dts: rockchip: Add PCIe endpoint mode support
commit: 2fe9fe4e54f5763b8b681478dda9ac61fd42ecaf
[13/13] arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode
commit: 41367db58cbf51ecb89ca017b7473688345caa7b
I've dropped the overlay-symbol-enablement for now.
As this creates massive size increases there have actually
been concerns of things like TF-A getting overwhelmed by
the size if I remember correctly.
In any case, right now we don't have an established way on
how to handle overlay symbold for Rockchip boards.
For example broadcom enables symbols for all DTs, Nvidia and TI do
it for select boards only, while for example Mediatek and Freescale
do not handle symbols at all right now.
So I'll just postpone that decision for a bit.
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: (subset) [PATCH v5 00/13] PCI: dw-rockchip: Add endpoint mode support
2024-06-26 15:32 ` (subset) " Heiko Stuebner
@ 2024-06-26 18:13 ` Niklas Cassel
0 siblings, 0 replies; 22+ messages in thread
From: Niklas Cassel @ 2024-06-26 18:13 UTC (permalink / raw)
To: Heiko Stuebner
Cc: Simon Xue, Shawn Lin, Arnd Bergmann, Krzysztof Wilczyński,
Kishon Vijay Abraham I, Damien Le Moal, Jon Lin,
Lorenzo Pieralisi, Manivannan Sadhasivam, Krzysztof Kozlowski,
Jingoo Han, Bjorn Helgaas, Conor Dooley, Rob Herring,
linux-rockchip, linux-pci, devicetree
On Wed, Jun 26, 2024 at 05:32:49PM +0200, Heiko Stuebner wrote:
> On Fri, 07 Jun 2024 13:14:20 +0200, Niklas Cassel wrote:
> > This series adds PCIe endpoint mode support for the rockchip rk3588 and
> > rk3568 SoCs.
> >
> > This series is based on: pci/next
> > (git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git)
> >
> > This series can also be found in git:
> > https://github.com/floatious/linux/commits/rockchip-pcie-ep-v5
> >
> > [...]
>
> Applied, thanks!
>
> [12/13] arm64: dts: rockchip: Add PCIe endpoint mode support
> commit: 2fe9fe4e54f5763b8b681478dda9ac61fd42ecaf
> [13/13] arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode
> commit: 41367db58cbf51ecb89ca017b7473688345caa7b
>
> I've dropped the overlay-symbol-enablement for now.
> As this creates massive size increases there have actually
> been concerns of things like TF-A getting overwhelmed by
> the size if I remember correctly.
>
> In any case, right now we don't have an established way on
> how to handle overlay symbold for Rockchip boards.
>
> For example broadcom enables symbols for all DTs, Nvidia and TI do
> it for select boards only, while for example Mediatek and Freescale
> do not handle symbols at all right now.
>
> So I'll just postpone that decision for a bit.
Okay, I see your argument.
Thank you for applying, I just realized that rk3588.dtsi has been renamed to
rk3588-extra.dtsi, so I was about to rebase and resend these two patches.
The conflict was trivial, and it looks correct in your tree, so thanks a lot
for fixing this up!
Kind regards,
Niklas
^ permalink raw reply [flat|nested] 22+ messages in thread