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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1faac99a30fsm527375ad.223.2024.06.26.16.39.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jun 2024 16:39:03 -0700 (PDT) Date: Wed, 26 Jun 2024 16:39:00 -0700 From: William McVicker To: Peter Griffin Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, cw00.choi@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH 2/3] soc: samsung: exynos-pmu: add support for PMU_ALIVE non atomic registers Message-ID: References: <20240626194300.302327-1-peter.griffin@linaro.org> <20240626194300.302327-3-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240626194300.302327-3-peter.griffin@linaro.org> On 06/26/2024, Peter Griffin wrote: > Not all registers in PMU_ALIVE block support atomic set/clear operations. > GS101_SYSIP_DAT0 and GS101_SYSTEM_CONFIGURATION registers are two regs > where attempting atomic access fails. > > As documentation on exactly which registers support atomic operations is > not forthcoming. We default to atomic access, unless the register is > explicitly added to the tensor_is_atomic() function. Update the comment > to reflect this as well. > > Signed-off-by: Peter Griffin Reviewed-by: Will McVicker Tested-by: Will McVicker I verified reboot and power off on my Pixel 6 Pro. > --- > drivers/soc/samsung/exynos-pmu.c | 16 ++++++++++++++-- > include/linux/soc/samsung/exynos-regs-pmu.h | 4 ++++ > 2 files changed, 18 insertions(+), 2 deletions(-) > > diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c > index 624324f4001c..5556acc7c092 100644 > --- a/drivers/soc/samsung/exynos-pmu.c > +++ b/drivers/soc/samsung/exynos-pmu.c > @@ -129,14 +129,26 @@ static int tensor_set_bits_atomic(void *ctx, unsigned int offset, u32 val, > return ret; > } > > +static bool tensor_is_atomic(unsigned int reg) > +{ > + switch (reg) { > + case GS101_SYSIP_DAT0: > + case GS101_SYSTEM_CONFIGURATION: > + return false; > + default: > + return true; > + } > +} > + > static int tensor_sec_update_bits(void *ctx, unsigned int reg, > unsigned int mask, unsigned int val) > { > /* > * Use atomic operations for PMU_ALIVE registers (offset 0~0x3FFF) > - * as the target registers can be accessed by multiple masters. > + * as the target registers can be accessed by multiple masters. Some > + * SFRs don't support this however as reported by tensor_is_atomic() > */ > - if (reg > PMUALIVE_MASK) > + if (reg > PMUALIVE_MASK || !tensor_is_atomic(reg)) nit: Should we just move all the logic, e.g. `reg > PMUALIVE_MASK` into `tensor_is_atomic()`? [...] Thanks, Will