[PATCH v3 00/11] riscv: add initial support for SpacemiT K1

[PATCH v3 00/11] riscv: add initial support for SpacemiT K1

[Yixun Lan]

SpacemiT K1 is an ideal chip for some new extension such as RISC-V Vector
1.0 and Zicond evaluation now. Add initial support for it to allow more
people to participate in building drivers to mainline for it.

This kernel has been tested upon Banana Pi BPI-F3 board on vendor U-Boot
bootflow generated by Armbian SDK[1] and patched OpenSBI[2] to enable
Zicboz, which does not in the vendor dts on its U-Boot. Then successfully
booted to busybox on initrd with this log[3].

As previous discussion in patch v1[4], maintainer expect more basic drivers
ready before really merging it, which would be fine. For other follow-up patches, 
that are clk, pinctrl/gpio, reset.. My current goal would target at a headless
system including SD card, emmc, and ethernet.

P.S: talked to Yangyu, I will help and take care of this patch series, thanks
---
Changes in v3:
 - fix dt_binding_check error
 - fix plic compatible
 - fix uart node name
 - add uart1 dts node
 - collect tags
 - Link to v2: https://lore.kernel.org/r/20240627-k1-01-basic-dt-v2-0-cc06c7555f07@gentoo.org

Changes in v2:
 - fix timebase-frequency according to current setting
 - add other uart dt nodes, fix input frequency
 - introduce new uart compatible for K1 SoC
 - add 'k1' prefix to bananapi-f3.dts
 - fix k1-clint compatible
 - fix some typos
 - Link to v1: https://lore.kernel.org/r/tencent_BC64B7B1876F5D10479BD19112F73F262505@qq.com

Link: https://github.com/BPI-SINOVOIP/armbian-build/tree/v24.04.30 [1]
Link: https://gist.github.com/cyyself/a07096e6e99c949ed13f8fa16d884402 [2]
Link: https://gist.github.com/cyyself/a2201c01f5c8955a119641f97b7d0280 [3]
Link: https://lore.kernel.org/r/20240618-hardwood-footrest-ab5ec5bce3cf@wendy [4]

To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Conor Dooley <conor@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>
To: Palmer Dabbelt <palmer@dabbelt.com>
To: Albert Ou <aou@eecs.berkeley.edu>
To: Daniel Lezcano <daniel.lezcano@linaro.org>
To: Thomas Gleixner <tglx@linutronix.de>
To: Samuel Holland <samuel.holland@sifive.com>
To: Anup Patel <anup@brainfault.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: Jiri Slaby <jirislaby@kernel.org>
To: Lubomir Rintel <lkundrak@v3.sk>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-serial@vger.kernel.org
Cc: Inochi Amaoto <inochiama@outlook.com>
Cc: Icenowy Zheng <uwu@icenowy.me>
Cc: Meng Zhang <zhangmeng.kevin@spacemit.com>

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Signed-off-by: Yixun Lan <dlan@gentoo.org>

---
Yangyu Chen (9):
      dt-bindings: vendor-prefixes: add spacemit
      dt-bindings: riscv: Add SpacemiT X60 compatibles
      dt-bindings: riscv: add SpacemiT K1 bindings
      dt-bindings: timer: Add SpacemiT K1 CLINT
      dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC
      riscv: add SpacemiT SoC family Kconfig support
      riscv: dts: add initial SpacemiT K1 SoC device tree
      riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree
      riscv: defconfig: enable SpacemiT SoC

Yixun Lan (2):
      dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible
      riscv: dts: spacemit: add uart1 node for K1 SoC

 .../interrupt-controller/sifive,plic-1.0.0.yaml    |   1 +
 Documentation/devicetree/bindings/riscv/cpus.yaml  |   1 +
 .../devicetree/bindings/riscv/spacemit.yaml        |  28 ++
 Documentation/devicetree/bindings/serial/8250.yaml |   4 +-
 .../devicetree/bindings/timer/sifive,clint.yaml    |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 arch/riscv/Kconfig.socs                            |   5 +
 arch/riscv/boot/dts/Makefile                       |   1 +
 arch/riscv/boot/dts/spacemit/Makefile              |   2 +
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts    |  19 +
 arch/riscv/boot/dts/spacemit/k1.dtsi               | 386 +++++++++++++++++++++
 arch/riscv/configs/defconfig                       |   1 +
 12 files changed, 450 insertions(+), 1 deletion(-)
---
base-commit: 22a40d14b572deb80c0648557f4bd502d7e83826
change-id: 20240626-k1-01-basic-dt-1aa31eeebcd2

Best regards,
-- 
Yixun Lan <dlan@gentoo.org>

[PATCH v3 01/11] dt-bindings: vendor-prefixes: add spacemit

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Add new vendor strings to dt bindings for SpacemiT K1 SoC.

Link: https://www.spacemit.com/en/spacemit-key-stone-2/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index fbf47f0bacf1a..7ee6e4a89376e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1362,6 +1362,8 @@ patternProperties:
     description: Sophgo Technology Inc.
   "^sourceparts,.*":
     description: Source Parts Inc.
+  "^spacemit,.*":
+    description: SpacemiT (Hangzhou) Technology Co. Ltd
   "^spansion,.*":
     description: Spansion Inc.
   "^sparkfun,.*":

-- 
2.45.2

[PATCH v3 02/11] dt-bindings: riscv: Add SpacemiT X60 compatibles

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1
SoC.

Link: https://www.spacemit.com/en/spacemit-x60-core/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d87dd50f1a4b5..5ad9cb4103356 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -46,6 +46,7 @@ properties:
               - sifive,u7
               - sifive,u74
               - sifive,u74-mc
+              - spacemit,x60
               - thead,c906
               - thead,c910
               - thead,c920

-- 
2.45.2

[PATCH v3 03/11] dt-bindings: riscv: add SpacemiT K1 bindings

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Add DT binding documentation for the SpacemiT K1 SoC[1] and the Banana
Pi BPi-F3 board[2] which used it.

Link: https://www.spacemit.com/en/spacemit-key-stone-2/ [1]
Link: https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 [2]
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 .../devicetree/bindings/riscv/spacemit.yaml        | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml
new file mode 100644
index 0000000000000..52e55077af1ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/spacemit.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT SoC-based boards
+
+maintainers:
+  - Yangyu Chen <cyy@cyyself.name>
+  - Yixun Lan <dlan@gentoo.org>
+
+description:
+  SpacemiT SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - bananapi,bpi-f3
+          - const: spacemit,k1
+
+additionalProperties: true
+
+...

-- 
2.45.2

[PATCH v3 04/11] dt-bindings: timer: Add SpacemiT K1 CLINT

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Add compatible string for SpacemiT K1 CLINT.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index fced6f2d8ecbb..c2e68587a806a 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -31,6 +31,7 @@ properties:
           - enum:
               - canaan,k210-clint       # Canaan Kendryte K210
               - sifive,fu540-c000-clint # SiFive FU540
+              - spacemit,k1-clint       # SpacemiT K1
               - starfive,jh7100-clint   # StarFive JH7100
               - starfive,jh7110-clint   # StarFive JH7110
               - starfive,jh8100-clint   # StarFive JH8100

-- 
2.45.2

[PATCH v3 05/11] dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Add compatible string for SpacemiT K1 PLIC.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 .../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml      | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 709b2211276bd..f473ca3479efd 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -59,6 +59,7 @@ properties:
           - enum:
               - canaan,k210-plic
               - sifive,fu540-c000-plic
+              - spacemit,k1-plic
               - starfive,jh7100-plic
               - starfive,jh7110-plic
           - const: sifive,plic-1.0.0

-- 
2.45.2

[PATCH v3 06/11] dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible

[Yixun Lan]

Found SpacemiT's K1 uart controller is compatible with
Intel's Xscale uart, but it's still worth to introduce a new compatible.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 Documentation/devicetree/bindings/serial/8250.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index 692aa05500fd5..0bde2379e8647 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -111,7 +111,9 @@ properties:
               - mediatek,mt7623-btif
           - const: mediatek,mtk-btif
       - items:
-          - const: mrvl,mmp-uart
+          - enum:
+              - mrvl,mmp-uart
+              - spacemit,k1-uart
           - const: intel,xscale-uart
       - items:
           - enum:

-- 
2.45.2

[PATCH v3 07/11] riscv: add SpacemiT SoC family Kconfig support

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

The first SoC in the SpacemiT series is K1, which contains 8 RISC-V
cores with RISC-V Vector v1.0 support.

Link: https://www.spacemit.com/en/spacemit-key-stone-2/
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 arch/riscv/Kconfig.socs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index f51bb24bc84c6..1916cf7ba450e 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -24,6 +24,11 @@ config ARCH_SOPHGO
 	help
 	  This enables support for Sophgo SoC platform hardware.
 
+config ARCH_SPACEMIT
+	bool "SpacemiT SoCs"
+	help
+	  This enables support for SpacemiT SoC platform hardware.
+
 config ARCH_STARFIVE
 	def_bool SOC_STARFIVE
 

-- 
2.45.2

[PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].

Key features:
- 4 cores per cluster, 2 clusters on chip
- UART IP is Intel XScale UART

Some key considerations:
- ISA string is inferred from vendor documentation[2]
- Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
- No coherent DMA on this board
    Inferred by taking vendor ethernet and MMC drivers to the mainline
    kernel. Without dma-noncoherent in soc node, the driver fails.
- No cache nodes now
    The parameters from vendor dts are likely to be wrong. It has 512
    sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
    When the size of the cache line is 64B, it is a directly mapped
    cache rather than a set-associative cache, the latter is commonly
    used. Thus, I didn't use the parameters from vendor dts.

Currently only support booting into console with only uart, other
features will be added soon later.

Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
 1 file changed, 376 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
new file mode 100644
index 0000000000000..a076e35855a2e
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -0,0 +1,376 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+/dts-v1/;
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "SpacemiT K1";
+	compatible = "spacemit,k1";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+		serial4 = &uart5;
+		serial5 = &uart6;
+		serial6 = &uart7;
+		serial7 = &uart8;
+		serial8 = &uart9;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <24000000>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu_0>;
+				};
+				core1 {
+					cpu = <&cpu_1>;
+				};
+				core2 {
+					cpu = <&cpu_2>;
+				};
+				core3 {
+					cpu = <&cpu_3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu_4>;
+				};
+				core1 {
+					cpu = <&cpu_5>;
+				};
+				core2 {
+					cpu = <&cpu_6>;
+				};
+				core3 {
+					cpu = <&cpu_7>;
+				};
+			};
+		};
+
+		cpu_0: cpu@0 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			mmu-type = "riscv,sv39";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_1: cpu@1 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <1>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			mmu-type = "riscv,sv39";
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_2: cpu@2 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <2>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			mmu-type = "riscv,sv39";
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_3: cpu@3 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <3>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			mmu-type = "riscv,sv39";
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_4: cpu@4 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <4>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			mmu-type = "riscv,sv39";
+
+			cpu4_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_5: cpu@5 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <5>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			mmu-type = "riscv,sv39";
+
+			cpu5_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_6: cpu@6 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <6>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			mmu-type = "riscv,sv39";
+
+			cpu6_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_7: cpu@7 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <7>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			mmu-type = "riscv,sv39";
+
+			cpu7_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-noncoherent;
+		ranges;
+
+		uart0: serial@d4017000 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017000 0x0 0x100>;
+			interrupts = <42>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart2: serial@d4017100 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017100 0x0 0x100>;
+			interrupts = <44>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart3: serial@d4017200 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017200 0x0 0x100>;
+			interrupts = <45>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart4: serial@d4017300 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017300 0x0 0x100>;
+			interrupts = <46>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart5: serial@d4017400 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017400 0x0 0x100>;
+			interrupts = <47>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart6: serial@d4017500 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017500 0x0 0x100>;
+			interrupts = <48>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart7: serial@d4017600 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017600 0x0 0x100>;
+			interrupts = <49>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart8: serial@d4017700 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017700 0x0 0x100>;
+			interrupts = <50>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart9: serial@d4017800 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017800 0x0 0x100>;
+			interrupts = <51>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		plic: interrupt-controller@e0000000 {
+			compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
+			reg = <0x0 0xe0000000 0x0 0x4000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>,
+					      <&cpu4_intc 11>, <&cpu4_intc 9>,
+					      <&cpu5_intc 11>, <&cpu5_intc 9>,
+					      <&cpu6_intc 11>, <&cpu6_intc 9>,
+					      <&cpu7_intc 11>, <&cpu7_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			riscv,ndev = <159>;
+		};
+
+		clint: timer@e4000000 {
+			compatible = "spacemit,k1-clint", "sifive,clint0";
+			reg = <0x0 0xe4000000 0x0 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>,
+					      <&cpu4_intc 3>, <&cpu4_intc 7>,
+					      <&cpu5_intc 3>, <&cpu5_intc 7>,
+					      <&cpu6_intc 3>, <&cpu6_intc 7>,
+					      <&cpu7_intc 3>, <&cpu7_intc 7>;
+		};
+	};
+};

-- 
2.45.2

[PATCH v3 09/11] riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Banana Pi BPI-F3 [1] is a industrial grade RISC-V development board, it
design with SpacemiT K1 8 core RISC-V chip [2].

Currently only support booting into console with only uart enabled,
other features will be added soon later.

Link: https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 [1]
Link: https://www.spacemit.com/en/spacemit-key-stone-2/ [2]
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 arch/riscv/boot/dts/Makefile                    |  1 +
 arch/riscv/boot/dts/spacemit/Makefile           |  2 ++
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 19 +++++++++++++++++++
 3 files changed, 22 insertions(+)

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index fdae05bbf5563..bff887d38abe4 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -5,6 +5,7 @@ subdir-y += microchip
 subdir-y += renesas
 subdir-y += sifive
 subdir-y += sophgo
+subdir-y += spacemit
 subdir-y += starfive
 subdir-y += thead
 
diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile
new file mode 100644
index 0000000000000..ac617319a5742
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SPACEMIT) += k1-bananapi-f3.dtb
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
new file mode 100644
index 0000000000000..023274189b492
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+#include "k1.dtsi"
+
+/ {
+	model = "Banana Pi BPI-F3";
+	compatible = "bananapi,bpi-f3", "spacemit,k1";
+
+	chosen {
+		stdout-path = "serial0";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};

-- 
2.45.2

[PATCH v3 10/11] riscv: defconfig: enable SpacemiT SoC

[Yixun Lan]

From: Yangyu Chen <cyy@cyyself.name>

Enable SpacemiT SoC config in defconfig to allow the default upstream
kernel to boot on Banana Pi BPI-F3 board.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 12dc8c73a8acf..5287ae81bbb78 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -29,6 +29,7 @@ CONFIG_ARCH_MICROCHIP=y
 CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_SIFIVE=y
 CONFIG_ARCH_SOPHGO=y
+CONFIG_ARCH_SPACEMIT=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_THEAD=y

-- 
2.45.2

[PATCH v3 11/11] riscv: dts: spacemit: add uart1 node for K1 SoC

[Yixun Lan]

Devices in 0xf000,0000 - 0xf080,0000 are reserved for TEE purpose,
so add uart1 here but mark its status as reserved.

Signed-off-by: Yixun Lan <dlan@gentoo.org>

---
This patch can be folded into "riscv: dts: add initial SpacemiT K1 SoC device tree",
if maintainer finds it's too trivial to have an independent patch..
---
 arch/riscv/boot/dts/spacemit/k1.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index a076e35855a2e..fee8921513c1f 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -372,5 +372,15 @@ clint: timer@e4000000 {
 					      <&cpu6_intc 3>, <&cpu6_intc 7>,
 					      <&cpu7_intc 3>, <&cpu7_intc 7>;
 		};
+
+		sec_uart1: serial@f0612000 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xf0612000 0x0 0x100>;
+			interrupts = <43>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "reserved"; /* for TEE usage */
+		};
 	};
 };

-- 
2.45.2

Re: [PATCH v3 05/11] dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 305 bytes --]

On Wed, Jul 03, 2024 at 02:55:08PM +0000, Yixun Lan wrote:
> From: Yangyu Chen <cyy@cyyself.name>
> 
> Add compatible string for SpacemiT K1 PLIC.
> 
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v3 03/11] dt-bindings: riscv: add SpacemiT K1 bindings

[Matthias Brugger]

On Wed, Jul 03, 2024 at 02:55:06PM +0000, Yixun Lan wrote:
> From: Yangyu Chen <cyy@cyyself.name>
> 
> Add DT binding documentation for the SpacemiT K1 SoC[1] and the Banana
> Pi BPi-F3 board[2] which used it.
> 
> Link: https://www.spacemit.com/en/spacemit-key-stone-2/ [1]
> Link: https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 [2]
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>

Reviewed-by: Matthias Brugger <matthias.bgg@kernel.org>

> ---
>  .../devicetree/bindings/riscv/spacemit.yaml        | 28 ++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml
> new file mode 100644
> index 0000000000000..52e55077af1ae
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml
> @@ -0,0 +1,28 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/spacemit.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SpacemiT SoC-based boards
> +
> +maintainers:
> +  - Yangyu Chen <cyy@cyyself.name>
> +  - Yixun Lan <dlan@gentoo.org>
> +
> +description:
> +  SpacemiT SoC-based boards
> +
> +properties:
> +  $nodename:
> +    const: '/'
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - bananapi,bpi-f3
> +          - const: spacemit,k1
> +
> +additionalProperties: true
> +
> +...
> 
> -- 
> 2.45.2
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v3 10/11] riscv: defconfig: enable SpacemiT SoC

[Jesse Taube]

On 7/3/24 10:55, Yixun Lan wrote:
> From: Yangyu Chen <cyy@cyyself.name>
> 
> Enable SpacemiT SoC config in defconfig to allow the default upstream
> kernel to boot on Banana Pi BPI-F3 board.
> 
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
Tested-by: Jesse Taube <jesse@rivosinc.com>

Thanks,
Jesse Taube
> ---
>   arch/riscv/configs/defconfig | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index 12dc8c73a8acf..5287ae81bbb78 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -29,6 +29,7 @@ CONFIG_ARCH_MICROCHIP=y
>   CONFIG_ARCH_RENESAS=y
>   CONFIG_ARCH_SIFIVE=y
>   CONFIG_ARCH_SOPHGO=y
> +CONFIG_ARCH_SPACEMIT=y
>   CONFIG_SOC_STARFIVE=y
>   CONFIG_ARCH_SUNXI=y
>   CONFIG_ARCH_THEAD=y
> 

Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree

[Jesse Taube]

On 7/3/24 10:55, Yixun Lan wrote:
> From: Yangyu Chen <cyy@cyyself.name>
> 
> Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> 
> Key features:
> - 4 cores per cluster, 2 clusters on chip
> - UART IP is Intel XScale UART
> 
> Some key considerations:
> - ISA string is inferred from vendor documentation[2]
> - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> - No coherent DMA on this board
>      Inferred by taking vendor ethernet and MMC drivers to the mainline
>      kernel. Without dma-noncoherent in soc node, the driver fails.
> - No cache nodes now
>      The parameters from vendor dts are likely to be wrong. It has 512
>      sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
>      When the size of the cache line is 64B, it is a directly mapped
>      cache rather than a set-associative cache, the latter is commonly
>      used. Thus, I didn't use the parameters from vendor dts.
> 
> Currently only support booting into console with only uart, other
> features will be added soon later.
> 
> Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
> ---
>   arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
>   1 file changed, 376 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> new file mode 100644
> index 0000000000000..a076e35855a2e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -0,0 +1,376 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +/dts-v1/;
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	model = "SpacemiT K1";
> +	compatible = "spacemit,k1";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart2;
> +		serial2 = &uart3;
> +		serial3 = &uart4;
> +		serial4 = &uart5;
> +		serial5 = &uart6;
> +		serial6 = &uart7;
> +		serial7 = &uart8;
> +		serial8 = &uart9;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <24000000>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu_0>;
> +				};
> +				core1 {
> +					cpu = <&cpu_1>;
> +				};
> +				core2 {
> +					cpu = <&cpu_2>;
> +				};
> +				core3 {
> +					cpu = <&cpu_3>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu_4>;
> +				};
> +				core1 {
> +					cpu = <&cpu_5>;
> +				};
> +				core2 {
> +					cpu = <&cpu_6>;
> +				};
> +				core3 {
> +					cpu = <&cpu_7>;
> +				};
> +			};
> +		};
> +
> +		cpu_0: cpu@0 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <0>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;

Is there a reson not to add the I and D cache sizes.

			i-cache-block-size = <64>;
			i-cache-size = <32768>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <32768>;
			d-cache-sets = <512>;
			next-level-cache = <&cluster0_l2_cache>;
......

		cluster0_l2_cache: l2-cache0 {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <524288>;
			cache-sets = <1024>;
			cache-unified;
		};

> +			mmu-type = "riscv,sv39";
> +
> +			cpu0_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_1: cpu@1 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <1>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu1_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_2: cpu@2 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <2>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu2_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_3: cpu@3 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <3>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu3_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_4: cpu@4 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <4>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu4_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_5: cpu@5 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <5>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu5_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_6: cpu@6 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <6>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu6_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_7: cpu@7 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <7>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu7_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		interrupt-parent = <&plic>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		dma-noncoherent;
> +		ranges;
> +
> +		uart0: serial@d4017000 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017000 0x0 0x100>;
> +			interrupts = <42>;

			interrupt-parent = <&plic>;

Thanks,
Jesse Taube

> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@d4017100 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017100 0x0 0x100>;
> +			interrupts = <44>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@d4017200 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017200 0x0 0x100>;
> +			interrupts = <45>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@d4017300 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017300 0x0 0x100>;
> +			interrupts = <46>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart5: serial@d4017400 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017400 0x0 0x100>;
> +			interrupts = <47>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart6: serial@d4017500 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017500 0x0 0x100>;
> +			interrupts = <48>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart7: serial@d4017600 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017600 0x0 0x100>;
> +			interrupts = <49>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart8: serial@d4017700 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017700 0x0 0x100>;
> +			interrupts = <50>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart9: serial@d4017800 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017800 0x0 0x100>;
> +			interrupts = <51>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		plic: interrupt-controller@e0000000 {
> +			compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> +			reg = <0x0 0xe0000000 0x0 0x4000000>;
> +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> +					      <&cpu1_intc 11>, <&cpu1_intc 9>,
> +					      <&cpu2_intc 11>, <&cpu2_intc 9>,
> +					      <&cpu3_intc 11>, <&cpu3_intc 9>,
> +					      <&cpu4_intc 11>, <&cpu4_intc 9>,
> +					      <&cpu5_intc 11>, <&cpu5_intc 9>,
> +					      <&cpu6_intc 11>, <&cpu6_intc 9>,
> +					      <&cpu7_intc 11>, <&cpu7_intc 9>;
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +			riscv,ndev = <159>;
> +		};
> +
> +		clint: timer@e4000000 {
> +			compatible = "spacemit,k1-clint", "sifive,clint0";
> +			reg = <0x0 0xe4000000 0x0 0x10000>;
> +			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> +					      <&cpu1_intc 3>, <&cpu1_intc 7>,
> +					      <&cpu2_intc 3>, <&cpu2_intc 7>,
> +					      <&cpu3_intc 3>, <&cpu3_intc 7>,
> +					      <&cpu4_intc 3>, <&cpu4_intc 7>,
> +					      <&cpu5_intc 3>, <&cpu5_intc 7>,
> +					      <&cpu6_intc 3>, <&cpu6_intc 7>,
> +					      <&cpu7_intc 3>, <&cpu7_intc 7>;
> +		};
> +	};
> +};
> 

Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree

[Yixun Lan]

Hi Jesse

On 21:17 Wed 03 Jul     , Jesse Taube wrote:
> On 7/3/24 10:55, Yixun Lan wrote:
> > From: Yangyu Chen <cyy@cyyself.name>
> > 
> > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > 
> > Key features:
> > - 4 cores per cluster, 2 clusters on chip
> > - UART IP is Intel XScale UART
> > 
> > Some key considerations:
> > - ISA string is inferred from vendor documentation[2]
> > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > - No coherent DMA on this board
> >      Inferred by taking vendor ethernet and MMC drivers to the mainline
> >      kernel. Without dma-noncoherent in soc node, the driver fails.
> > - No cache nodes now
> >      The parameters from vendor dts are likely to be wrong. It has 512
> >      sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> >      When the size of the cache line is 64B, it is a directly mapped
> >      cache rather than a set-associative cache, the latter is commonly
> >      used. Thus, I didn't use the parameters from vendor dts.
> > 
> > Currently only support booting into console with only uart, other
> > features will be added soon later.
> > 
> > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > ---
> >   arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> >   1 file changed, 376 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > new file mode 100644
> > index 0000000000000..a076e35855a2e
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > @@ -0,0 +1,376 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > + */
> > +
> > +/dts-v1/;
> > +/ {
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +	model = "SpacemiT K1";
> > +	compatible = "spacemit,k1";
> > +
> > +	aliases {
> > +		serial0 = &uart0;
> > +		serial1 = &uart2;
> > +		serial2 = &uart3;
> > +		serial3 = &uart4;
> > +		serial4 = &uart5;
> > +		serial5 = &uart6;
> > +		serial6 = &uart7;
> > +		serial7 = &uart8;
> > +		serial8 = &uart9;
> > +	};
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		timebase-frequency = <24000000>;
> > +
> > +		cpu-map {
> > +			cluster0 {
> > +				core0 {
> > +					cpu = <&cpu_0>;
> > +				};
> > +				core1 {
> > +					cpu = <&cpu_1>;
> > +				};
> > +				core2 {
> > +					cpu = <&cpu_2>;
> > +				};
> > +				core3 {
> > +					cpu = <&cpu_3>;
> > +				};
> > +			};
> > +
> > +			cluster1 {
> > +				core0 {
> > +					cpu = <&cpu_4>;
> > +				};
> > +				core1 {
> > +					cpu = <&cpu_5>;
> > +				};
> > +				core2 {
> > +					cpu = <&cpu_6>;
> > +				};
> > +				core3 {
> > +					cpu = <&cpu_7>;
> > +				};
> > +			};
> > +		};
> > +
> > +		cpu_0: cpu@0 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <0>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> 
> Is there a reson not to add the I and D cache sizes.
No specific reason..

For "not adding those properties", I think it's largely due to Yangyu is kind of
skeptical about the info from vendor dts, and he do want to test/verify before
adding them..

so, did you test all these info, and confirm they are correct?

> 
> 			i-cache-block-size = <64>;
> 			i-cache-size = <32768>;
> 			i-cache-sets = <512>;
> 			d-cache-block-size = <64>;
> 			d-cache-size = <32768>;
> 			d-cache-sets = <512>;
> 			next-level-cache = <&cluster0_l2_cache>;
> ......
> 
> 		cluster0_l2_cache: l2-cache0 {
> 			compatible = "cache";
> 			cache-block-size = <64>;
> 			cache-level = <2>;
> 			cache-size = <524288>;
> 			cache-sets = <1024>;
> 			cache-unified;
> 		};
> 
I think we probably have two options, 1) including this info in next version bump
2) leave it alone, and sending via another independent patch

I do not have strong preference, but do want to confirm before adding them.

> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu0_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_1: cpu@1 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <1>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu1_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_2: cpu@2 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <2>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu2_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_3: cpu@3 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <3>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu3_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_4: cpu@4 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <4>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu4_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_5: cpu@5 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <5>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu5_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_6: cpu@6 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <6>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu6_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_7: cpu@7 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <7>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu7_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +	};
> > +
> > +	soc {
> > +		compatible = "simple-bus";
> > +		interrupt-parent = <&plic>;
    we have interrrupt-parent info here

> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		dma-noncoherent;
> > +		ranges;
> > +
> > +		uart0: serial@d4017000 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017000 0x0 0x100>;
> > +			interrupts = <42>;
> 
> 			interrupt-parent = <&plic>;
I think if we omit this info, then this node's interrupt parent property will
inherit from its device tree parent?

But I'm not sure if this is the right way to do from dt maintainer's
perspective? or should we specify interrupt-parent explicitly?

thanks for raising this question
> 
> Thanks,
> Jesse Taube
> 
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart2: serial@d4017100 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017100 0x0 0x100>;
> > +			interrupts = <44>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart3: serial@d4017200 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017200 0x0 0x100>;
> > +			interrupts = <45>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart4: serial@d4017300 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017300 0x0 0x100>;
> > +			interrupts = <46>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart5: serial@d4017400 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017400 0x0 0x100>;
> > +			interrupts = <47>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart6: serial@d4017500 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017500 0x0 0x100>;
> > +			interrupts = <48>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart7: serial@d4017600 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017600 0x0 0x100>;
> > +			interrupts = <49>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart8: serial@d4017700 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017700 0x0 0x100>;
> > +			interrupts = <50>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart9: serial@d4017800 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017800 0x0 0x100>;
> > +			interrupts = <51>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		plic: interrupt-controller@e0000000 {
> > +			compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> > +			reg = <0x0 0xe0000000 0x0 0x4000000>;
> > +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> > +					      <&cpu1_intc 11>, <&cpu1_intc 9>,
> > +					      <&cpu2_intc 11>, <&cpu2_intc 9>,
> > +					      <&cpu3_intc 11>, <&cpu3_intc 9>,
> > +					      <&cpu4_intc 11>, <&cpu4_intc 9>,
> > +					      <&cpu5_intc 11>, <&cpu5_intc 9>,
> > +					      <&cpu6_intc 11>, <&cpu6_intc 9>,
> > +					      <&cpu7_intc 11>, <&cpu7_intc 9>;
> > +			interrupt-controller;
> > +			#address-cells = <0>;
> > +			#interrupt-cells = <1>;
> > +			riscv,ndev = <159>;
> > +		};
> > +
> > +		clint: timer@e4000000 {
> > +			compatible = "spacemit,k1-clint", "sifive,clint0";
> > +			reg = <0x0 0xe4000000 0x0 0x10000>;
> > +			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> > +					      <&cpu1_intc 3>, <&cpu1_intc 7>,
> > +					      <&cpu2_intc 3>, <&cpu2_intc 7>,
> > +					      <&cpu3_intc 3>, <&cpu3_intc 7>,
> > +					      <&cpu4_intc 3>, <&cpu4_intc 7>,
> > +					      <&cpu5_intc 3>, <&cpu5_intc 7>,
> > +					      <&cpu6_intc 3>, <&cpu6_intc 7>,
> > +					      <&cpu7_intc 3>, <&cpu7_intc 7>;
> > +		};
> > +	};
> > +};
> > 

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree

[Jisheng Zhang]

On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> From: Yangyu Chen <cyy@cyyself.name>
> 
> Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> 
> Key features:
> - 4 cores per cluster, 2 clusters on chip
> - UART IP is Intel XScale UART
> 
> Some key considerations:
> - ISA string is inferred from vendor documentation[2]
> - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> - No coherent DMA on this board
>     Inferred by taking vendor ethernet and MMC drivers to the mainline
>     kernel. Without dma-noncoherent in soc node, the driver fails.
> - No cache nodes now
>     The parameters from vendor dts are likely to be wrong. It has 512
>     sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
>     When the size of the cache line is 64B, it is a directly mapped
>     cache rather than a set-associative cache, the latter is commonly
>     used. Thus, I didn't use the parameters from vendor dts.
> 
> Currently only support booting into console with only uart, other
> features will be added soon later.
> 
> Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
> ---
>  arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
>  1 file changed, 376 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> new file mode 100644
> index 0000000000000..a076e35855a2e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -0,0 +1,376 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +/dts-v1/;
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	model = "SpacemiT K1";
> +	compatible = "spacemit,k1";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart2;
> +		serial2 = &uart3;
> +		serial3 = &uart4;
> +		serial4 = &uart5;
> +		serial5 = &uart6;
> +		serial6 = &uart7;
> +		serial7 = &uart8;
> +		serial8 = &uart9;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <24000000>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu_0>;
> +				};
> +				core1 {
> +					cpu = <&cpu_1>;
> +				};
> +				core2 {
> +					cpu = <&cpu_2>;
> +				};
> +				core3 {
> +					cpu = <&cpu_3>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu_4>;
> +				};
> +				core1 {
> +					cpu = <&cpu_5>;
> +				};
> +				core2 {
> +					cpu = <&cpu_6>;
> +				};
> +				core3 {
> +					cpu = <&cpu_7>;
> +				};
> +			};
> +		};
> +
> +		cpu_0: cpu@0 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <0>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu0_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_1: cpu@1 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <1>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu1_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_2: cpu@2 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <2>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu2_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_3: cpu@3 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <3>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu3_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_4: cpu@4 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <4>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu4_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_5: cpu@5 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <5>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu5_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_6: cpu@6 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <6>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu6_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu_7: cpu@7 {
> +			compatible = "spacemit,x60", "riscv";
> +			device_type = "cpu";
> +			reg = <7>;
> +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +			riscv,cbom-block-size = <64>;
> +			riscv,cbop-block-size = <64>;
> +			riscv,cboz-block-size = <64>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu7_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		interrupt-parent = <&plic>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		dma-noncoherent;
> +		ranges;
> +
> +		uart0: serial@d4017000 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";

no, this is not a correct hw modeling. The doc on spacemit says
all the uart support 64 bytes FIFO, declaring xscale only makes
use of 32 bytes FIFO.

IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
"mrvl,pxa-uart" or "mrvl,mmp-uart"

> +			reg = <0x0 0xd4017000 0x0 0x100>;
> +			interrupts = <42>;
> +			clock-frequency = <14857000>;

once clk is ready, you will remove this property and add clk phandles,
so why not bring clk, pinctrl, reset before hand?

> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@d4017100 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017100 0x0 0x100>;
> +			interrupts = <44>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@d4017200 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017200 0x0 0x100>;
> +			interrupts = <45>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@d4017300 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017300 0x0 0x100>;
> +			interrupts = <46>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart5: serial@d4017400 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017400 0x0 0x100>;
> +			interrupts = <47>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart6: serial@d4017500 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017500 0x0 0x100>;
> +			interrupts = <48>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart7: serial@d4017600 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017600 0x0 0x100>;
> +			interrupts = <49>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart8: serial@d4017700 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017700 0x0 0x100>;
> +			interrupts = <50>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		uart9: serial@d4017800 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xd4017800 0x0 0x100>;
> +			interrupts = <51>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +
> +		plic: interrupt-controller@e0000000 {
> +			compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> +			reg = <0x0 0xe0000000 0x0 0x4000000>;
> +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> +					      <&cpu1_intc 11>, <&cpu1_intc 9>,
> +					      <&cpu2_intc 11>, <&cpu2_intc 9>,
> +					      <&cpu3_intc 11>, <&cpu3_intc 9>,
> +					      <&cpu4_intc 11>, <&cpu4_intc 9>,
> +					      <&cpu5_intc 11>, <&cpu5_intc 9>,
> +					      <&cpu6_intc 11>, <&cpu6_intc 9>,
> +					      <&cpu7_intc 11>, <&cpu7_intc 9>;
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +			riscv,ndev = <159>;
> +		};
> +
> +		clint: timer@e4000000 {
> +			compatible = "spacemit,k1-clint", "sifive,clint0";
> +			reg = <0x0 0xe4000000 0x0 0x10000>;
> +			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> +					      <&cpu1_intc 3>, <&cpu1_intc 7>,
> +					      <&cpu2_intc 3>, <&cpu2_intc 7>,
> +					      <&cpu3_intc 3>, <&cpu3_intc 7>,
> +					      <&cpu4_intc 3>, <&cpu4_intc 7>,
> +					      <&cpu5_intc 3>, <&cpu5_intc 7>,
> +					      <&cpu6_intc 3>, <&cpu6_intc 7>,
> +					      <&cpu7_intc 3>, <&cpu7_intc 7>;
> +		};
> +	};
> +};
> 
> -- 
> 2.45.2
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v3 06/11] dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible

[Jisheng Zhang]

On Wed, Jul 03, 2024 at 02:55:09PM +0000, Yixun Lan wrote:
> Found SpacemiT's K1 uart controller is compatible with
> Intel's Xscale uart, but it's still worth to introduce a new compatible.

Per vendor's kernel source code, all the uarts support 64Bytes FIFO.
So if it's compatible with Xscale, it's a xscale uart 64 Bytes FIFO.
From this PoV, the uart isn't a Xscale but a mrvl pxa.

But I have one question: is the uart really a mrvl/intel pxa uart? or is just
reg programming compatible with pxa?

> 
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
> ---
>  Documentation/devicetree/bindings/serial/8250.yaml | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
> index 692aa05500fd5..0bde2379e8647 100644
> --- a/Documentation/devicetree/bindings/serial/8250.yaml
> +++ b/Documentation/devicetree/bindings/serial/8250.yaml
> @@ -111,7 +111,9 @@ properties:
>                - mediatek,mt7623-btif
>            - const: mediatek,mtk-btif
>        - items:
> -          - const: mrvl,mmp-uart
> +          - enum:
> +              - mrvl,mmp-uart
> +              - spacemit,k1-uart
>            - const: intel,xscale-uart
>        - items:
>            - enum:
> 
> -- 
> 2.45.2
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v3 11/11] riscv: dts: spacemit: add uart1 node for K1 SoC

[Jisheng Zhang]

On Wed, Jul 03, 2024 at 02:55:14PM +0000, Yixun Lan wrote:
> Devices in 0xf000,0000 - 0xf080,0000 are reserved for TEE purpose,
> so add uart1 here but mark its status as reserved.

This patch doesn't deserve a seperate patch, it's better to fold it
into the dtsi one.

> 
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
> 
> ---
> This patch can be folded into "riscv: dts: add initial SpacemiT K1 SoC device tree",
> if maintainer finds it's too trivial to have an independent patch..
> ---
>  arch/riscv/boot/dts/spacemit/k1.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index a076e35855a2e..fee8921513c1f 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -372,5 +372,15 @@ clint: timer@e4000000 {
>  					      <&cpu6_intc 3>, <&cpu6_intc 7>,
>  					      <&cpu7_intc 3>, <&cpu7_intc 7>;
>  		};
> +
> +		sec_uart1: serial@f0612000 {
> +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +			reg = <0x0 0xf0612000 0x0 0x100>;
> +			interrupts = <43>;
> +			clock-frequency = <14857000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "reserved"; /* for TEE usage */
> +		};
>  	};
>  };
> 
> -- 
> 2.45.2
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree

[Jisheng Zhang]

On Thu, Jul 04, 2024 at 09:48:01PM +0800, Jisheng Zhang wrote:
> On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > From: Yangyu Chen <cyy@cyyself.name>
> > 
> > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > 
> > Key features:
> > - 4 cores per cluster, 2 clusters on chip
> > - UART IP is Intel XScale UART
> > 
> > Some key considerations:
> > - ISA string is inferred from vendor documentation[2]
> > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > - No coherent DMA on this board
> >     Inferred by taking vendor ethernet and MMC drivers to the mainline
> >     kernel. Without dma-noncoherent in soc node, the driver fails.
> > - No cache nodes now
> >     The parameters from vendor dts are likely to be wrong. It has 512
> >     sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> >     When the size of the cache line is 64B, it is a directly mapped
> >     cache rather than a set-associative cache, the latter is commonly
> >     used. Thus, I didn't use the parameters from vendor dts.
> > 
> > Currently only support booting into console with only uart, other
> > features will be added soon later.
> > 
> > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > ---
> >  arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> >  1 file changed, 376 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > new file mode 100644
> > index 0000000000000..a076e35855a2e
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > @@ -0,0 +1,376 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > + */
> > +
> > +/dts-v1/;
> > +/ {
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +	model = "SpacemiT K1";
> > +	compatible = "spacemit,k1";
> > +
> > +	aliases {
> > +		serial0 = &uart0;
> > +		serial1 = &uart2;
> > +		serial2 = &uart3;
> > +		serial3 = &uart4;
> > +		serial4 = &uart5;
> > +		serial5 = &uart6;
> > +		serial6 = &uart7;
> > +		serial7 = &uart8;
> > +		serial8 = &uart9;
> > +	};
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		timebase-frequency = <24000000>;
> > +
> > +		cpu-map {
> > +			cluster0 {
> > +				core0 {
> > +					cpu = <&cpu_0>;
> > +				};
> > +				core1 {
> > +					cpu = <&cpu_1>;
> > +				};
> > +				core2 {
> > +					cpu = <&cpu_2>;
> > +				};
> > +				core3 {
> > +					cpu = <&cpu_3>;
> > +				};
> > +			};
> > +
> > +			cluster1 {
> > +				core0 {
> > +					cpu = <&cpu_4>;
> > +				};
> > +				core1 {
> > +					cpu = <&cpu_5>;
> > +				};
> > +				core2 {
> > +					cpu = <&cpu_6>;
> > +				};
> > +				core3 {
> > +					cpu = <&cpu_7>;
> > +				};
> > +			};
> > +		};
> > +
> > +		cpu_0: cpu@0 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <0>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu0_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_1: cpu@1 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <1>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu1_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_2: cpu@2 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <2>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu2_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_3: cpu@3 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <3>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu3_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_4: cpu@4 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <4>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu4_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_5: cpu@5 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <5>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu5_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_6: cpu@6 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <6>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu6_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_7: cpu@7 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <7>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu7_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +	};
> > +
> > +	soc {
> > +		compatible = "simple-bus";
> > +		interrupt-parent = <&plic>;
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		dma-noncoherent;
> > +		ranges;
> > +
> > +		uart0: serial@d4017000 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> 
> no, this is not a correct hw modeling.

Vendor's linux kernel source code also clearly indicates the FIFO size
is 64B.

> 
> IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> "mrvl,pxa-uart" or "mrvl,mmp-uart"
> 
> > +			reg = <0x0 0xd4017000 0x0 0x100>;
> > +			interrupts = <42>;
> > +			clock-frequency = <14857000>;
> 
> once clk is ready, you will remove this property and add clk phandles,
> so why not bring clk, pinctrl, reset before hand?
> 

Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree

[张猛]

Hi, Yixun Lan,
> From: "Yixun Lan"<dlan@gentoo.org>
> Date:  Wed, Jul 3, 2024, 22:57
> Subject:  [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
> To: "Rob Herring"<robh@kernel.org>, "Krzysztof Kozlowski"<krzk+dt@kernel.org>, "Conor Dooley"<conor+dt@kernel.org>, "Conor Dooley"<conor@kernel.org>, "Paul Walmsley"<paul.walmsley@sifive.com>, "Palmer Dabbelt"<palmer@dabbelt.com>, "Albert Ou"<aou@eecs.berkeley.edu>, "Daniel Lezcano"<daniel.lezcano@linaro.org>, "Thomas Gleixner"<tglx@linutronix.de>, "Samuel Holland"<samuel.holland@sifive.com>, "Anup Patel"<anup@brainfault.org>, "Greg Kroah-Hartman"<gregkh@linuxfoundation.org>, "Jiri Slaby"<jirislaby@kernel.org>, "Lubomir Rintel"<lkundrak@v3.sk>
> Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-serial@vger.kernel.org>, "Inochi Amaoto"<inochiama@outlook.com>, "Icenowy Zheng"<uwu@icenowy.me>, "Meng Zhang"<zhangmeng.kevin@spacemit.com>, "Yangyu Chen"<cyy@cyyself.name>, "Yixun Lan"<dlan@gentoo.org>
> From: Yangyu Chen <cyy@cyyself.name>
> 
> Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> 
> Key features:
> - 4 cores per cluster, 2 clusters on chip
> - UART IP is Intel XScale UART
> 
> Some key considerations:
> - ISA string is inferred from vendor documentation[2]
> - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> - No coherent DMA on this board
>     Inferred by taking vendor ethernet and MMC drivers to the mainline
>     kernel. Without dma-noncoherent in soc node, the driver fails.
> - No cache nodes now
>     The parameters from vendor dts are likely to be wrong. It has 512
>     sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
>     When the size of the cache line is 64B, it is a directly mapped
>     cache rather than a set-associative cache, the latter is commonly
>     used. Thus, I didn't use the parameters from vendor dts.
> 
> Currently only support booting into console with only uart, other
> features will be added soon later.
> 
> Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
> ---
>  arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
>  1 file changed, 376 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> new file mode 100644
> index 0000000000000..a076e35855a2e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -0,0 +1,376 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +/dts-v1/;
> +/ {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +        model = "SpacemiT K1";
> +        compatible = "spacemit,k1";
> +
> +        aliases {
> +                serial0 = &uart0;
> +                serial1 = &uart2;
> +                serial2 = &uart3;
> +                serial3 = &uart4;
> +                serial4 = &uart5;
> +                serial5 = &uart6;
> +                serial6 = &uart7;
> +                serial7 = &uart8;
> +                serial8 = &uart9;
> +        };
> +
> +        cpus {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +                timebase-frequency = <24000000>;
> +
> +                cpu-map {
> +                        cluster0 {
> +                                core0 {
> +                                        cpu = <&cpu_0>;
> +                                };
> +                                core1 {
> +                                        cpu = <&cpu_1>;
> +                                };
> +                                core2 {
> +                                        cpu = <&cpu_2>;
> +                                };
> +                                core3 {
> +                                        cpu = <&cpu_3>;
> +                                };
> +                        };
> +
> +                        cluster1 {
> +                                core0 {
> +                                        cpu = <&cpu_4>;
> +                                };
> +                                core1 {
> +                                        cpu = <&cpu_5>;
> +                                };
> +                                core2 {
> +                                        cpu = <&cpu_6>;
> +                                };
> +                                core3 {
> +                                        cpu = <&cpu_7>;
> +                                };
> +                        };
> +                };
> +
> +                cpu_0: cpu@0 {
> +                        compatible = "spacemit,x60", "riscv";
> +                        device_type = "cpu";
> +                        reg = <0>;
> +                        riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
Linux 6.7 kernel modifies the definition of the "riscv, isa" property, and describes the extended features in the "riscv, isa-extensions". So, can the definition of "riscv, isa" be simplified here?
Defined as ：  riscv,isa = "rv64imafdcv";

> +                        riscv,isa-base = "rv64i";
> +                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                               "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                               "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                               "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                               "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                        riscv,cbom-block-size = <64>;
> +                        riscv,cbop-block-size = <64>;
> +                        riscv,cboz-block-size = <64>;
> +                        mmu-type = "riscv,sv39";
> +
> +                        cpu0_intc: interrupt-controller {
> +                                compatible = "riscv,cpu-intc";
> +                                interrupt-controller;
> +                                #interrupt-cells = <1>;
> +                        };
> +                };
> +
> +                cpu_1: cpu@1 {
> +                        compatible = "spacemit,x60", "riscv";
> +                        device_type = "cpu";
> +                        reg = <1>;
> +                        riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                        riscv,isa-base = "rv64i";
> +                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                               "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                               "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                               "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                               "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                        riscv,cbom-block-size = <64>;
> +                        riscv,cbop-block-size = <64>;
> +                        riscv,cboz-block-size = <64>;
> +                        mmu-type = "riscv,sv39";
> +
> +                        cpu1_intc: interrupt-controller {
> +                                compatible = "riscv,cpu-intc";
> +                                interrupt-controller;
> +                                #interrupt-cells = <1>;
> +                        };
> +                };
> +
> +                cpu_2: cpu@2 {
> +                        compatible = "spacemit,x60", "riscv";
> +                        device_type = "cpu";
> +                        reg = <2>;
> +                        riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                        riscv,isa-base = "rv64i";
> +                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                               "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                               "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                               "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                               "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                        riscv,cbom-block-size = <64>;
> +                        riscv,cbop-block-size = <64>;
> +                        riscv,cboz-block-size = <64>;
> +                        mmu-type = "riscv,sv39";
> +
> +                        cpu2_intc: interrupt-controller {
> +                                compatible = "riscv,cpu-intc";
> +                                interrupt-controller;
> +                                #interrupt-cells = <1>;
> +                        };
> +                };
> +
> +                cpu_3: cpu@3 {
> +                        compatible = "spacemit,x60", "riscv";
> +                        device_type = "cpu";
> +                        reg = <3>;
> +                        riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                        riscv,isa-base = "rv64i";
> +                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                               "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                               "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                               "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                               "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                        riscv,cbom-block-size = <64>;
> +                        riscv,cbop-block-size = <64>;
> +                        riscv,cboz-block-size = <64>;
> +                        mmu-type = "riscv,sv39";
> +
> +                        cpu3_intc: interrupt-controller {
> +                                compatible = "riscv,cpu-intc";
> +                                interrupt-controller;
> +                                #interrupt-cells = <1>;
> +                        };
> +                };
> +
> +                cpu_4: cpu@4 {
> +                        compatible = "spacemit,x60", "riscv";
> +                        device_type = "cpu";
> +                        reg = <4>;
> +                        riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                        riscv,isa-base = "rv64i";
> +                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                               "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                               "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                               "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                               "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                        riscv,cbom-block-size = <64>;
> +                        riscv,cbop-block-size = <64>;
> +                        riscv,cboz-block-size = <64>;
> +                        mmu-type = "riscv,sv39";
> +
> +                        cpu4_intc: interrupt-controller {
> +                                compatible = "riscv,cpu-intc";
> +                                interrupt-controller;
> +                                #interrupt-cells = <1>;
> +                        };
> +                };
> +
> +                cpu_5: cpu@5 {
> +                        compatible = "spacemit,x60", "riscv";
> +                        device_type = "cpu";
> +                        reg = <5>;
> +                        riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                        riscv,isa-base = "rv64i";
> +                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                               "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                               "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                               "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                               "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                        riscv,cbom-block-size = <64>;
> +                        riscv,cbop-block-size = <64>;
> +                        riscv,cboz-block-size = <64>;
> +                        mmu-type = "riscv,sv39";
> +
> +                        cpu5_intc: interrupt-controller {
> +                                compatible = "riscv,cpu-intc";
> +                                interrupt-controller;
> +                                #interrupt-cells = <1>;
> +                        };
> +                };
> +
> +                cpu_6: cpu@6 {
> +                        compatible = "spacemit,x60", "riscv";
> +                        device_type = "cpu";
> +                        reg = <6>;
> +                        riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                        riscv,isa-base = "rv64i";
> +                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                               "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                               "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                               "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                               "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                        riscv,cbom-block-size = <64>;
> +                        riscv,cbop-block-size = <64>;
> +                        riscv,cboz-block-size = <64>;
> +                        mmu-type = "riscv,sv39";
> +
> +                        cpu6_intc: interrupt-controller {
> +                                compatible = "riscv,cpu-intc";
> +                                interrupt-controller;
> +                                #interrupt-cells = <1>;
> +                        };
> +                };
> +
> +                cpu_7: cpu@7 {
> +                        compatible = "spacemit,x60", "riscv";
> +                        device_type = "cpu";
> +                        reg = <7>;
> +                        riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> +                        riscv,isa-base = "rv64i";
> +                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> +                                               "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> +                                               "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> +                                               "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> +                                               "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> +                        riscv,cbom-block-size = <64>;
> +                        riscv,cbop-block-size = <64>;
> +                        riscv,cboz-block-size = <64>;
> +                        mmu-type = "riscv,sv39";
> +
> +                        cpu7_intc: interrupt-controller {
> +                                compatible = "riscv,cpu-intc";
> +                                interrupt-controller;
> +                                #interrupt-cells = <1>;
> +                        };
> +                };
> +
> +        };
> +
> +        soc {
> +                compatible = "simple-bus";
> +                interrupt-parent = <&plic>;
> +                #address-cells = <2>;
> +                #size-cells = <2>;
> +                dma-noncoherent;
> +                ranges;
> +
> +                uart0: serial@d4017000 {
> +                        compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                        reg = <0x0 0xd4017000 0x0 0x100>;
> +                        interrupts = <42>;
> +                        clock-frequency = <14857000>;
> +                        reg-shift = <2>;
> +                        reg-io-width = <4>;
> +                        status = "disabled";
> +                };
> +
> +                uart2: serial@d4017100 {
> +                        compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                        reg = <0x0 0xd4017100 0x0 0x100>;
> +                        interrupts = <44>;
> +                        clock-frequency = <14857000>;
> +                        reg-shift = <2>;
> +                        reg-io-width = <4>;
> +                        status = "disabled";
> +                };
> +
> +                uart3: serial@d4017200 {
> +                        compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                        reg = <0x0 0xd4017200 0x0 0x100>;
> +                        interrupts = <45>;
> +                        clock-frequency = <14857000>;
> +                        reg-shift = <2>;
> +                        reg-io-width = <4>;
> +                        status = "disabled";
> +                };
> +
> +                uart4: serial@d4017300 {
> +                        compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                        reg = <0x0 0xd4017300 0x0 0x100>;
> +                        interrupts = <46>;
> +                        clock-frequency = <14857000>;
> +                        reg-shift = <2>;
> +                        reg-io-width = <4>;
> +                        status = "disabled";
> +                };
> +
> +                uart5: serial@d4017400 {
> +                        compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                        reg = <0x0 0xd4017400 0x0 0x100>;
> +                        interrupts = <47>;
> +                        clock-frequency = <14857000>;
> +                        reg-shift = <2>;
> +                        reg-io-width = <4>;
> +                        status = "disabled";
> +                };
> +
> +                uart6: serial@d4017500 {
> +                        compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                        reg = <0x0 0xd4017500 0x0 0x100>;
> +                        interrupts = <48>;
> +                        clock-frequency = <14857000>;
> +                        reg-shift = <2>;
> +                        reg-io-width = <4>;
> +                        status = "disabled";
> +                };
> +
> +                uart7: serial@d4017600 {
> +                        compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                        reg = <0x0 0xd4017600 0x0 0x100>;
> +                        interrupts = <49>;
> +                        clock-frequency = <14857000>;
> +                        reg-shift = <2>;
> +                        reg-io-width = <4>;
> +                        status = "disabled";
> +                };
> +
> +                uart8: serial@d4017700 {
> +                        compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                        reg = <0x0 0xd4017700 0x0 0x100>;
> +                        interrupts = <50>;
> +                        clock-frequency = <14857000>;
> +                        reg-shift = <2>;
> +                        reg-io-width = <4>;
> +                        status = "disabled";
> +                };
> +
> +                uart9: serial@d4017800 {
> +                        compatible = "spacemit,k1-uart", "intel,xscale-uart";
> +                        reg = <0x0 0xd4017800 0x0 0x100>;
> +                        interrupts = <51>;
> +                        clock-frequency = <14857000>;
> +                        reg-shift = <2>;
> +                        reg-io-width = <4>;
> +                        status = "disabled";
> +                };
> +
> +                plic: interrupt-controller@e0000000 {
> +                        compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> +                        reg = <0x0 0xe0000000 0x0 0x4000000>;
> +                        interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> +                                              <&cpu1_intc 11>, <&cpu1_intc 9>,
> +                                              <&cpu2_intc 11>, <&cpu2_intc 9>,
> +                                              <&cpu3_intc 11>, <&cpu3_intc 9>,
> +                                              <&cpu4_intc 11>, <&cpu4_intc 9>,
> +                                              <&cpu5_intc 11>, <&cpu5_intc 9>,
> +                                              <&cpu6_intc 11>, <&cpu6_intc 9>,
> +                                              <&cpu7_intc 11>, <&cpu7_intc 9>;
> +                        interrupt-controller;
> +                        #address-cells = <0>;
> +                        #interrupt-cells = <1>;
> +                        riscv,ndev = <159>;
> +                };
> +
> +                clint: timer@e4000000 {
> +                        compatible = "spacemit,k1-clint", "sifive,clint0";
> +                        reg = <0x0 0xe4000000 0x0 0x10000>;
> +                        interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> +                                              <&cpu1_intc 3>, <&cpu1_intc 7>,
> +                                              <&cpu2_intc 3>, <&cpu2_intc 7>,
> +                                              <&cpu3_intc 3>, <&cpu3_intc 7>,
> +                                              <&cpu4_intc 3>, <&cpu4_intc 7>,
> +                                              <&cpu5_intc 3>, <&cpu5_intc 7>,
> +                                              <&cpu6_intc 3>, <&cpu6_intc 7>,
> +                                              <&cpu7_intc 3>, <&cpu7_intc 7>;
> +                };
> +        };
> +};
> 
> -- 
> 2.45.2


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本邮件及其任何附件具有保密性质，并可能受其他保护或不允许被披露给第三方。如阁下误收到本邮件，敬请立即以回复电子邮件的方式通知发件人，并将本邮件及其任何附件从阁下系统中予以删除。如阁下并非本邮件写明之收件人，敬请切勿使用、复制、披露本邮件或其任何内容，亦请切勿依本邮件或其任何内容而采取任何行动。电子邮件无法保证是一种安全和不会出现任何差错的通信方式，可能会被拦截、修改、丢失或损坏，收件人需自行负责做好安全检查。

Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree

[Conor Dooley]

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On Fri, Jul 05, 2024 at 01:55:43PM +0800, 张猛 wrote:

> > +                        riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> Linux 6.7 kernel modifies the definition of the "riscv, isa" property, and describes the extended features in the "riscv, isa-extensions". So, can the definition of "riscv, isa" be simplified here?
> Defined as ：  riscv,isa = "rv64imafdcv";

No, they should match, other than vendor extensions. Not every project
supports the new property.

> This message and any attachment are confidential and may be privileged or otherwise protected from disclosure. If you are not an intended recipient of this message, please delete it and any attachment from your system and notify the sender immediately by reply e-mail. Unintended recipients should not use, copy, disclose or take any action based on this message or any information contained in this message. Emails cannot be guaranteed to be secure or error free as they can be intercepted, amended, lost or destroyed, and you should take full responsibility for security checking. 
>  
> 本邮件及其任何附件具有保密性质，并可能受其他保护或不允许被披露给第三方。如阁下误收到本邮件，敬请立即以回复电子邮件的方式通知发件人，并将本邮件及其任何附件从阁下系统中予以删除。如阁下并非本邮件写明之收件人，敬请切勿使用、复制、披露本邮件或其任何内容，亦请切勿依本邮件或其任何内容而采取任何行动。电子邮件无法保证是一种安全和不会出现任何差错的通信方式，可能会被拦截、修改、丢失或损坏，收件人需自行负责做好安全检查。

Please fix your mail client/system to not append this. Such footers are
incompatible with kernel development.

Thanks,
Conor.

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Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree

[Yixun Lan]

On 21:46 Thu 04 Jul     , Jisheng Zhang wrote:
> On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > From: Yangyu Chen <cyy@cyyself.name>
> > 
> > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > 
> > Key features:
> > - 4 cores per cluster, 2 clusters on chip
> > - UART IP is Intel XScale UART
> > 
> > Some key considerations:
> > - ISA string is inferred from vendor documentation[2]
> > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > - No coherent DMA on this board
> >     Inferred by taking vendor ethernet and MMC drivers to the mainline
> >     kernel. Without dma-noncoherent in soc node, the driver fails.
> > - No cache nodes now
> >     The parameters from vendor dts are likely to be wrong. It has 512
> >     sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> >     When the size of the cache line is 64B, it is a directly mapped
> >     cache rather than a set-associative cache, the latter is commonly
> >     used. Thus, I didn't use the parameters from vendor dts.
> > 
> > Currently only support booting into console with only uart, other
> > features will be added soon later.
> > 
> > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > ---
> >  arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> >  1 file changed, 376 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > new file mode 100644
> > index 0000000000000..a076e35855a2e
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > @@ -0,0 +1,376 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > + */
> > +
> > +/dts-v1/;
> > +/ {
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +	model = "SpacemiT K1";
> > +	compatible = "spacemit,k1";
> > +
> > +	aliases {
> > +		serial0 = &uart0;
> > +		serial1 = &uart2;
> > +		serial2 = &uart3;
> > +		serial3 = &uart4;
> > +		serial4 = &uart5;
> > +		serial5 = &uart6;
> > +		serial6 = &uart7;
> > +		serial7 = &uart8;
> > +		serial8 = &uart9;
> > +	};
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		timebase-frequency = <24000000>;
> > +
> > +		cpu-map {
> > +			cluster0 {
> > +				core0 {
> > +					cpu = <&cpu_0>;
> > +				};
> > +				core1 {
> > +					cpu = <&cpu_1>;
> > +				};
> > +				core2 {
> > +					cpu = <&cpu_2>;
> > +				};
> > +				core3 {
> > +					cpu = <&cpu_3>;
> > +				};
> > +			};
> > +
> > +			cluster1 {
> > +				core0 {
> > +					cpu = <&cpu_4>;
> > +				};
> > +				core1 {
> > +					cpu = <&cpu_5>;
> > +				};
> > +				core2 {
> > +					cpu = <&cpu_6>;
> > +				};
> > +				core3 {
> > +					cpu = <&cpu_7>;
> > +				};
> > +			};
> > +		};
> > +
> > +		cpu_0: cpu@0 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <0>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu0_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_1: cpu@1 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <1>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu1_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_2: cpu@2 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <2>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu2_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_3: cpu@3 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <3>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu3_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_4: cpu@4 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <4>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu4_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_5: cpu@5 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <5>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu5_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_6: cpu@6 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <6>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu6_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +		cpu_7: cpu@7 {
> > +			compatible = "spacemit,x60", "riscv";
> > +			device_type = "cpu";
> > +			reg = <7>;
> > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > +			riscv,isa-base = "rv64i";
> > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > +			riscv,cbom-block-size = <64>;
> > +			riscv,cbop-block-size = <64>;
> > +			riscv,cboz-block-size = <64>;
> > +			mmu-type = "riscv,sv39";
> > +
> > +			cpu7_intc: interrupt-controller {
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> > +	};
> > +
> > +	soc {
> > +		compatible = "simple-bus";
> > +		interrupt-parent = <&plic>;
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		dma-noncoherent;
> > +		ranges;
> > +
> > +		uart0: serial@d4017000 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> 
> no, this is not a correct hw modeling. The doc on spacemit says
> all the uart support 64 bytes FIFO, declaring xscale only makes
> use of 32 bytes FIFO.
yes, I also noticed it's 64 bytes FIFO

> 
> IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> "mrvl,pxa-uart" or "mrvl,mmp-uart"


for mrvl,pxa-uart, I think you imply to use drivers/tty/serial/8250/8250_pxa.c,
which turn out doesn't work on k1 SoC, for the record, we need to adjust
 drivers/tty/serial/8250/Kconfig to enable the driver for ARCH_SPACEMIT,
 and change uart compatible to "spacemit,k1-uart", "mrvl,pxa-uart"

for mrvl,mmp-uart, I see two choices, one using 8250_pxa.c which has same result
as mrvl,pxa-uart, another choice would using the driver of 8250_of.c 
and it work as same as "intel,xscale-uart", I don't see any difference..

P.S: there is possibly a side problem that "mrvl,mmp-uart" from 8250_of.c doesn't 
really compatile with "mrvl,mmp-uart" from 8250_pxa.c, but I think it's another story

> 
> > +			reg = <0x0 0xd4017000 0x0 0x100>;
> > +			interrupts = <42>;
> > +			clock-frequency = <14857000>;
> 
> once clk is ready, you will remove this property and add clk phandles,
yes, this is exactly the plan

> so why not bring clk, pinctrl, reset before hand?
> 
No, we want to have an initial minimal working environment with initramfs + console,
and start from there to work with clk, pinctrl, reset, it will help us to debug and 
work in parallel

Note, I have no objection, if maintainer consider to merge this patch series on condition that
clk, pinctrl, reset are also ready..


> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart2: serial@d4017100 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017100 0x0 0x100>;
> > +			interrupts = <44>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart3: serial@d4017200 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017200 0x0 0x100>;
> > +			interrupts = <45>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart4: serial@d4017300 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017300 0x0 0x100>;
> > +			interrupts = <46>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart5: serial@d4017400 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017400 0x0 0x100>;
> > +			interrupts = <47>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart6: serial@d4017500 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017500 0x0 0x100>;
> > +			interrupts = <48>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart7: serial@d4017600 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017600 0x0 0x100>;
> > +			interrupts = <49>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart8: serial@d4017700 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017700 0x0 0x100>;
> > +			interrupts = <50>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart9: serial@d4017800 {
> > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > +			reg = <0x0 0xd4017800 0x0 0x100>;
> > +			interrupts = <51>;
> > +			clock-frequency = <14857000>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			status = "disabled";
> > +		};
> > +
> > +		plic: interrupt-controller@e0000000 {
> > +			compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> > +			reg = <0x0 0xe0000000 0x0 0x4000000>;
> > +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> > +					      <&cpu1_intc 11>, <&cpu1_intc 9>,
> > +					      <&cpu2_intc 11>, <&cpu2_intc 9>,
> > +					      <&cpu3_intc 11>, <&cpu3_intc 9>,
> > +					      <&cpu4_intc 11>, <&cpu4_intc 9>,
> > +					      <&cpu5_intc 11>, <&cpu5_intc 9>,
> > +					      <&cpu6_intc 11>, <&cpu6_intc 9>,
> > +					      <&cpu7_intc 11>, <&cpu7_intc 9>;
> > +			interrupt-controller;
> > +			#address-cells = <0>;
> > +			#interrupt-cells = <1>;
> > +			riscv,ndev = <159>;
> > +		};
> > +
> > +		clint: timer@e4000000 {
> > +			compatible = "spacemit,k1-clint", "sifive,clint0";
> > +			reg = <0x0 0xe4000000 0x0 0x10000>;
> > +			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> > +					      <&cpu1_intc 3>, <&cpu1_intc 7>,
> > +					      <&cpu2_intc 3>, <&cpu2_intc 7>,
> > +					      <&cpu3_intc 3>, <&cpu3_intc 7>,
> > +					      <&cpu4_intc 3>, <&cpu4_intc 7>,
> > +					      <&cpu5_intc 3>, <&cpu5_intc 7>,
> > +					      <&cpu6_intc 3>, <&cpu6_intc 7>,
> > +					      <&cpu7_intc 3>, <&cpu7_intc 7>;
> > +		};
> > +	};
> > +};
> > 
> > -- 
> > 2.45.2
> > 
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

Re: [PATCH v3 06/11] dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible

[Yixun Lan]

On 22:03 Thu 04 Jul     , Jisheng Zhang wrote:
> On Wed, Jul 03, 2024 at 02:55:09PM +0000, Yixun Lan wrote:
> > Found SpacemiT's K1 uart controller is compatible with
> > Intel's Xscale uart, but it's still worth to introduce a new compatible.
> 
> Per vendor's kernel source code, all the uarts support 64Bytes FIFO.
> So if it's compatible with Xscale, it's a xscale uart 64 Bytes FIFO.
yes, I agree

further question would how to implement specific support for spacemit's k1 SoC
one possible option to add a PORT_SPACEMIT compatible data to 8250_port.c - uart_config[]


> >From this PoV, the uart isn't a Xscale but a mrvl pxa.
see my previous comment, probably need further clarification/investigation..

> 
> But I have one question: is the uart really a mrvl/intel pxa uart? or is just
No, I'm unable to answer this, I'm not an employee of SpacemiT
All informations are based on public available source + docs..

> reg programming compatible with pxa?
> 
To my knowledge, it's compatible with pxa, but it would be great that vendor can clarify this

> > 
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > ---
> >  Documentation/devicetree/bindings/serial/8250.yaml | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
> > index 692aa05500fd5..0bde2379e8647 100644
> > --- a/Documentation/devicetree/bindings/serial/8250.yaml
> > +++ b/Documentation/devicetree/bindings/serial/8250.yaml
> > @@ -111,7 +111,9 @@ properties:
> >                - mediatek,mt7623-btif
> >            - const: mediatek,mtk-btif
> >        - items:
> > -          - const: mrvl,mmp-uart
> > +          - enum:
> > +              - mrvl,mmp-uart
> > +              - spacemit,k1-uart
> >            - const: intel,xscale-uart
> >        - items:
> >            - enum:
> > 
> > -- 
> > 2.45.2
> > 
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

Re: [PATCH v3 11/11] riscv: dts: spacemit: add uart1 node for K1 SoC

[Yixun Lan]

On 22:05 Thu 04 Jul     , Jisheng Zhang wrote:
> On Wed, Jul 03, 2024 at 02:55:14PM +0000, Yixun Lan wrote:
> > Devices in 0xf000,0000 - 0xf080,0000 are reserved for TEE purpose,
> > so add uart1 here but mark its status as reserved.
> 
> This patch doesn't deserve a seperate patch, it's better to fold it
> into the dtsi one.

fine, I will address it in next revision

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree

[Jisheng Zhang]

On Fri, Jul 05, 2024 at 06:38:39AM +0000, Yixun Lan wrote:
> 
> On 21:46 Thu 04 Jul     , Jisheng Zhang wrote:
> > On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > > From: Yangyu Chen <cyy@cyyself.name>
> > > 
> > > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > > 
> > > Key features:
> > > - 4 cores per cluster, 2 clusters on chip
> > > - UART IP is Intel XScale UART
> > > 
> > > Some key considerations:
> > > - ISA string is inferred from vendor documentation[2]
> > > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > > - No coherent DMA on this board
> > >     Inferred by taking vendor ethernet and MMC drivers to the mainline
> > >     kernel. Without dma-noncoherent in soc node, the driver fails.
> > > - No cache nodes now
> > >     The parameters from vendor dts are likely to be wrong. It has 512
> > >     sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > >     When the size of the cache line is 64B, it is a directly mapped
> > >     cache rather than a set-associative cache, the latter is commonly
> > >     used. Thus, I didn't use the parameters from vendor dts.
> > > 
> > > Currently only support booting into console with only uart, other
> > > features will be added soon later.
> > > 
> > > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > > ---
> > >  arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > >  1 file changed, 376 insertions(+)
> > > 
> > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > new file mode 100644
> > > index 0000000000000..a076e35855a2e
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > @@ -0,0 +1,376 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > +/*
> > > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > > + */
> > > +
> > > +/dts-v1/;
> > > +/ {
> > > +	#address-cells = <2>;
> > > +	#size-cells = <2>;
> > > +	model = "SpacemiT K1";
> > > +	compatible = "spacemit,k1";
> > > +
> > > +	aliases {
> > > +		serial0 = &uart0;
> > > +		serial1 = &uart2;
> > > +		serial2 = &uart3;
> > > +		serial3 = &uart4;
> > > +		serial4 = &uart5;
> > > +		serial5 = &uart6;
> > > +		serial6 = &uart7;
> > > +		serial7 = &uart8;
> > > +		serial8 = &uart9;
> > > +	};
> > > +
> > > +	cpus {
> > > +		#address-cells = <1>;
> > > +		#size-cells = <0>;
> > > +		timebase-frequency = <24000000>;
> > > +
> > > +		cpu-map {
> > > +			cluster0 {
> > > +				core0 {
> > > +					cpu = <&cpu_0>;
> > > +				};
> > > +				core1 {
> > > +					cpu = <&cpu_1>;
> > > +				};
> > > +				core2 {
> > > +					cpu = <&cpu_2>;
> > > +				};
> > > +				core3 {
> > > +					cpu = <&cpu_3>;
> > > +				};
> > > +			};
> > > +
> > > +			cluster1 {
> > > +				core0 {
> > > +					cpu = <&cpu_4>;
> > > +				};
> > > +				core1 {
> > > +					cpu = <&cpu_5>;
> > > +				};
> > > +				core2 {
> > > +					cpu = <&cpu_6>;
> > > +				};
> > > +				core3 {
> > > +					cpu = <&cpu_7>;
> > > +				};
> > > +			};
> > > +		};
> > > +
> > > +		cpu_0: cpu@0 {
> > > +			compatible = "spacemit,x60", "riscv";
> > > +			device_type = "cpu";
> > > +			reg = <0>;
> > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > +			riscv,isa-base = "rv64i";
> > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > +			riscv,cbom-block-size = <64>;
> > > +			riscv,cbop-block-size = <64>;
> > > +			riscv,cboz-block-size = <64>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu0_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu_1: cpu@1 {
> > > +			compatible = "spacemit,x60", "riscv";
> > > +			device_type = "cpu";
> > > +			reg = <1>;
> > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > +			riscv,isa-base = "rv64i";
> > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > +			riscv,cbom-block-size = <64>;
> > > +			riscv,cbop-block-size = <64>;
> > > +			riscv,cboz-block-size = <64>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu1_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu_2: cpu@2 {
> > > +			compatible = "spacemit,x60", "riscv";
> > > +			device_type = "cpu";
> > > +			reg = <2>;
> > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > +			riscv,isa-base = "rv64i";
> > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > +			riscv,cbom-block-size = <64>;
> > > +			riscv,cbop-block-size = <64>;
> > > +			riscv,cboz-block-size = <64>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu2_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu_3: cpu@3 {
> > > +			compatible = "spacemit,x60", "riscv";
> > > +			device_type = "cpu";
> > > +			reg = <3>;
> > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > +			riscv,isa-base = "rv64i";
> > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > +			riscv,cbom-block-size = <64>;
> > > +			riscv,cbop-block-size = <64>;
> > > +			riscv,cboz-block-size = <64>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu3_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu_4: cpu@4 {
> > > +			compatible = "spacemit,x60", "riscv";
> > > +			device_type = "cpu";
> > > +			reg = <4>;
> > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > +			riscv,isa-base = "rv64i";
> > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > +			riscv,cbom-block-size = <64>;
> > > +			riscv,cbop-block-size = <64>;
> > > +			riscv,cboz-block-size = <64>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu4_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu_5: cpu@5 {
> > > +			compatible = "spacemit,x60", "riscv";
> > > +			device_type = "cpu";
> > > +			reg = <5>;
> > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > +			riscv,isa-base = "rv64i";
> > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > +			riscv,cbom-block-size = <64>;
> > > +			riscv,cbop-block-size = <64>;
> > > +			riscv,cboz-block-size = <64>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu5_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu_6: cpu@6 {
> > > +			compatible = "spacemit,x60", "riscv";
> > > +			device_type = "cpu";
> > > +			reg = <6>;
> > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > +			riscv,isa-base = "rv64i";
> > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > +			riscv,cbom-block-size = <64>;
> > > +			riscv,cbop-block-size = <64>;
> > > +			riscv,cboz-block-size = <64>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu6_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu_7: cpu@7 {
> > > +			compatible = "spacemit,x60", "riscv";
> > > +			device_type = "cpu";
> > > +			reg = <7>;
> > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > +			riscv,isa-base = "rv64i";
> > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > +			riscv,cbom-block-size = <64>;
> > > +			riscv,cbop-block-size = <64>;
> > > +			riscv,cboz-block-size = <64>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu7_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +	};
> > > +
> > > +	soc {
> > > +		compatible = "simple-bus";
> > > +		interrupt-parent = <&plic>;
> > > +		#address-cells = <2>;
> > > +		#size-cells = <2>;
> > > +		dma-noncoherent;
> > > +		ranges;
> > > +
> > > +		uart0: serial@d4017000 {
> > > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > 
> > no, this is not a correct hw modeling. The doc on spacemit says
> > all the uart support 64 bytes FIFO, declaring xscale only makes
> > use of 32 bytes FIFO.
> yes, I also noticed it's 64 bytes FIFO
> 
> > 
> > IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> > "mrvl,pxa-uart" or "mrvl,mmp-uart"
> 
> 
> for mrvl,pxa-uart, I think you imply to use drivers/tty/serial/8250/8250_pxa.c,
> which turn out doesn't work on k1 SoC, for the record, we need to adjust

Really? I just tried "mrvl,pxa-uart" with rc6, it works perfectly, and the FIFO
in the driver logic is 64bytes now. Am I misssing something or you never tried it?

>  drivers/tty/serial/8250/Kconfig to enable the driver for ARCH_SPACEMIT,
>  and change uart compatible to "spacemit,k1-uart", "mrvl,pxa-uart"
> 
> for mrvl,mmp-uart, I see two choices, one using 8250_pxa.c which has same result
> as mrvl,pxa-uart, another choice would using the driver of 8250_of.c 
> and it work as same as "intel,xscale-uart", I don't see any difference..
> 
> P.S: there is possibly a side problem that "mrvl,mmp-uart" from 8250_of.c doesn't 
> really compatile with "mrvl,mmp-uart" from 8250_pxa.c, but I think it's another story

Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree

[Yixun Lan]

On 12:12 Sat 06 Jul     , Jisheng Zhang wrote:
> On Fri, Jul 05, 2024 at 06:38:39AM +0000, Yixun Lan wrote:
> > 
> > On 21:46 Thu 04 Jul     , Jisheng Zhang wrote:
> > > On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > > > From: Yangyu Chen <cyy@cyyself.name>
> > > > 
> > > > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > > > 
> > > > Key features:
> > > > - 4 cores per cluster, 2 clusters on chip
> > > > - UART IP is Intel XScale UART
> > > > 
> > > > Some key considerations:
> > > > - ISA string is inferred from vendor documentation[2]
> > > > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > > > - No coherent DMA on this board
> > > >     Inferred by taking vendor ethernet and MMC drivers to the mainline
> > > >     kernel. Without dma-noncoherent in soc node, the driver fails.
> > > > - No cache nodes now
> > > >     The parameters from vendor dts are likely to be wrong. It has 512
> > > >     sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > > >     When the size of the cache line is 64B, it is a directly mapped
> > > >     cache rather than a set-associative cache, the latter is commonly
> > > >     used. Thus, I didn't use the parameters from vendor dts.
> > > > 
> > > > Currently only support booting into console with only uart, other
> > > > features will be added soon later.
> > > > 
> > > > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > > > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > > > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > > > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > > > ---
> > > >  arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > > >  1 file changed, 376 insertions(+)
> > > > 
> > > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > new file mode 100644
> > > > index 0000000000000..a076e35855a2e
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > @@ -0,0 +1,376 @@
> > > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > > +/*
> > > > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > > > + */
> > > > +
> > > > +/dts-v1/;
> > > > +/ {
> > > > +	#address-cells = <2>;
> > > > +	#size-cells = <2>;
> > > > +	model = "SpacemiT K1";
> > > > +	compatible = "spacemit,k1";
> > > > +
> > > > +	aliases {
> > > > +		serial0 = &uart0;
> > > > +		serial1 = &uart2;
> > > > +		serial2 = &uart3;
> > > > +		serial3 = &uart4;
> > > > +		serial4 = &uart5;
> > > > +		serial5 = &uart6;
> > > > +		serial6 = &uart7;
> > > > +		serial7 = &uart8;
> > > > +		serial8 = &uart9;
> > > > +	};
> > > > +
> > > > +	cpus {
> > > > +		#address-cells = <1>;
> > > > +		#size-cells = <0>;
> > > > +		timebase-frequency = <24000000>;
> > > > +
> > > > +		cpu-map {
> > > > +			cluster0 {
> > > > +				core0 {
> > > > +					cpu = <&cpu_0>;
> > > > +				};
> > > > +				core1 {
> > > > +					cpu = <&cpu_1>;
> > > > +				};
> > > > +				core2 {
> > > > +					cpu = <&cpu_2>;
> > > > +				};
> > > > +				core3 {
> > > > +					cpu = <&cpu_3>;
> > > > +				};
> > > > +			};
> > > > +
> > > > +			cluster1 {
> > > > +				core0 {
> > > > +					cpu = <&cpu_4>;
> > > > +				};
> > > > +				core1 {
> > > > +					cpu = <&cpu_5>;
> > > > +				};
> > > > +				core2 {
> > > > +					cpu = <&cpu_6>;
> > > > +				};
> > > > +				core3 {
> > > > +					cpu = <&cpu_7>;
> > > > +				};
> > > > +			};
> > > > +		};
> > > > +
> > > > +		cpu_0: cpu@0 {
> > > > +			compatible = "spacemit,x60", "riscv";
> > > > +			device_type = "cpu";
> > > > +			reg = <0>;
> > > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > +			riscv,isa-base = "rv64i";
> > > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > +			riscv,cbom-block-size = <64>;
> > > > +			riscv,cbop-block-size = <64>;
> > > > +			riscv,cboz-block-size = <64>;
> > > > +			mmu-type = "riscv,sv39";
> > > > +
> > > > +			cpu0_intc: interrupt-controller {
> > > > +				compatible = "riscv,cpu-intc";
> > > > +				interrupt-controller;
> > > > +				#interrupt-cells = <1>;
> > > > +			};
> > > > +		};
> > > > +
> > > > +		cpu_1: cpu@1 {
> > > > +			compatible = "spacemit,x60", "riscv";
> > > > +			device_type = "cpu";
> > > > +			reg = <1>;
> > > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > +			riscv,isa-base = "rv64i";
> > > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > +			riscv,cbom-block-size = <64>;
> > > > +			riscv,cbop-block-size = <64>;
> > > > +			riscv,cboz-block-size = <64>;
> > > > +			mmu-type = "riscv,sv39";
> > > > +
> > > > +			cpu1_intc: interrupt-controller {
> > > > +				compatible = "riscv,cpu-intc";
> > > > +				interrupt-controller;
> > > > +				#interrupt-cells = <1>;
> > > > +			};
> > > > +		};
> > > > +
> > > > +		cpu_2: cpu@2 {
> > > > +			compatible = "spacemit,x60", "riscv";
> > > > +			device_type = "cpu";
> > > > +			reg = <2>;
> > > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > +			riscv,isa-base = "rv64i";
> > > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > +			riscv,cbom-block-size = <64>;
> > > > +			riscv,cbop-block-size = <64>;
> > > > +			riscv,cboz-block-size = <64>;
> > > > +			mmu-type = "riscv,sv39";
> > > > +
> > > > +			cpu2_intc: interrupt-controller {
> > > > +				compatible = "riscv,cpu-intc";
> > > > +				interrupt-controller;
> > > > +				#interrupt-cells = <1>;
> > > > +			};
> > > > +		};
> > > > +
> > > > +		cpu_3: cpu@3 {
> > > > +			compatible = "spacemit,x60", "riscv";
> > > > +			device_type = "cpu";
> > > > +			reg = <3>;
> > > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > +			riscv,isa-base = "rv64i";
> > > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > +			riscv,cbom-block-size = <64>;
> > > > +			riscv,cbop-block-size = <64>;
> > > > +			riscv,cboz-block-size = <64>;
> > > > +			mmu-type = "riscv,sv39";
> > > > +
> > > > +			cpu3_intc: interrupt-controller {
> > > > +				compatible = "riscv,cpu-intc";
> > > > +				interrupt-controller;
> > > > +				#interrupt-cells = <1>;
> > > > +			};
> > > > +		};
> > > > +
> > > > +		cpu_4: cpu@4 {
> > > > +			compatible = "spacemit,x60", "riscv";
> > > > +			device_type = "cpu";
> > > > +			reg = <4>;
> > > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > +			riscv,isa-base = "rv64i";
> > > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > +			riscv,cbom-block-size = <64>;
> > > > +			riscv,cbop-block-size = <64>;
> > > > +			riscv,cboz-block-size = <64>;
> > > > +			mmu-type = "riscv,sv39";
> > > > +
> > > > +			cpu4_intc: interrupt-controller {
> > > > +				compatible = "riscv,cpu-intc";
> > > > +				interrupt-controller;
> > > > +				#interrupt-cells = <1>;
> > > > +			};
> > > > +		};
> > > > +
> > > > +		cpu_5: cpu@5 {
> > > > +			compatible = "spacemit,x60", "riscv";
> > > > +			device_type = "cpu";
> > > > +			reg = <5>;
> > > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > +			riscv,isa-base = "rv64i";
> > > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > +			riscv,cbom-block-size = <64>;
> > > > +			riscv,cbop-block-size = <64>;
> > > > +			riscv,cboz-block-size = <64>;
> > > > +			mmu-type = "riscv,sv39";
> > > > +
> > > > +			cpu5_intc: interrupt-controller {
> > > > +				compatible = "riscv,cpu-intc";
> > > > +				interrupt-controller;
> > > > +				#interrupt-cells = <1>;
> > > > +			};
> > > > +		};
> > > > +
> > > > +		cpu_6: cpu@6 {
> > > > +			compatible = "spacemit,x60", "riscv";
> > > > +			device_type = "cpu";
> > > > +			reg = <6>;
> > > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > +			riscv,isa-base = "rv64i";
> > > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > +			riscv,cbom-block-size = <64>;
> > > > +			riscv,cbop-block-size = <64>;
> > > > +			riscv,cboz-block-size = <64>;
> > > > +			mmu-type = "riscv,sv39";
> > > > +
> > > > +			cpu6_intc: interrupt-controller {
> > > > +				compatible = "riscv,cpu-intc";
> > > > +				interrupt-controller;
> > > > +				#interrupt-cells = <1>;
> > > > +			};
> > > > +		};
> > > > +
> > > > +		cpu_7: cpu@7 {
> > > > +			compatible = "spacemit,x60", "riscv";
> > > > +			device_type = "cpu";
> > > > +			reg = <7>;
> > > > +			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > +			riscv,isa-base = "rv64i";
> > > > +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > +					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > +					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > +					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > +					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > +			riscv,cbom-block-size = <64>;
> > > > +			riscv,cbop-block-size = <64>;
> > > > +			riscv,cboz-block-size = <64>;
> > > > +			mmu-type = "riscv,sv39";
> > > > +
> > > > +			cpu7_intc: interrupt-controller {
> > > > +				compatible = "riscv,cpu-intc";
> > > > +				interrupt-controller;
> > > > +				#interrupt-cells = <1>;
> > > > +			};
> > > > +		};
> > > > +
> > > > +	};
> > > > +
> > > > +	soc {
> > > > +		compatible = "simple-bus";
> > > > +		interrupt-parent = <&plic>;
> > > > +		#address-cells = <2>;
> > > > +		#size-cells = <2>;
> > > > +		dma-noncoherent;
> > > > +		ranges;
> > > > +
> > > > +		uart0: serial@d4017000 {
> > > > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > > 
> > > no, this is not a correct hw modeling. The doc on spacemit says
> > > all the uart support 64 bytes FIFO, declaring xscale only makes
> > > use of 32 bytes FIFO.
> > yes, I also noticed it's 64 bytes FIFO
> > 
> > > 
> > > IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> > > "mrvl,pxa-uart" or "mrvl,mmp-uart"
> > 
> > 
> > for mrvl,pxa-uart, I think you imply to use drivers/tty/serial/8250/8250_pxa.c,
> > which turn out doesn't work on k1 SoC, for the record, we need to adjust
> 
> Really? I just tried "mrvl,pxa-uart" with rc6, it works perfectly, and the FIFO
> in the driver logic is 64bytes now. Am I misssing something or you never tried it?
> 
Ok, I realised it's the clock issue

still, I'm not fully convinced about using "mrvl,pxa-uart",
e.g this driver hardcoded tz_loadsz to 32, not sure if K1 suffer same problem
5208e7ced520 ("serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level")

also, what's the preference when choosing driver between 8250_pxa.c vs 8250_of.c?
it occur to me that 8250_pxa.c is more specially tailored for pxa hardware, while
8250_of.c is more generic.. besides, should we consider one more step if we want to
support DMA mode in the future (vendor uart driver has DMA support)?


> >  drivers/tty/serial/8250/Kconfig to enable the driver for ARCH_SPACEMIT,
> >  and change uart compatible to "spacemit,k1-uart", "mrvl,pxa-uart"
> > 
> > for mrvl,mmp-uart, I see two choices, one using 8250_pxa.c which has same result
> > as mrvl,pxa-uart, another choice would using the driver of 8250_of.c 
> > and it work as same as "intel,xscale-uart", I don't see any difference..
> > 
> > P.S: there is possibly a side problem that "mrvl,mmp-uart" from 8250_of.c doesn't 
> > really compatile with "mrvl,mmp-uart" from 8250_pxa.c, but I think it's another story

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

Re: [PATCH v3 06/11] dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible

[张猛]

> From: "Yixun Lan"<dlan@gentoo.org>
> Date:  Fri, Jul 5, 2024, 14:47
> Subject:  Re: [PATCH v3 06/11] dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible
> To: "Jisheng Zhang"<jszhang@kernel.org>
> Cc: "Rob Herring"<robh@kernel.org>, "Krzysztof Kozlowski"<krzk+dt@kernel.org>, "Conor Dooley"<conor+dt@kernel.org>, "Conor Dooley"<conor@kernel.org>, "Paul Walmsley"<paul.walmsley@sifive.com>, "Palmer Dabbelt"<palmer@dabbelt.com>, "Albert Ou"<aou@eecs.berkeley.edu>, "Daniel Lezcano"<daniel.lezcano@linaro.org>, "Thomas Gleixner"<tglx@linutronix.de>, "Samuel Holland"<samuel.holland@sifive.com>, "Anup Patel"<anup@brainfault.org>, "Greg Kroah-Hartman"<gregkh@linuxfoundation.org>, "Jiri Slaby"<jirislaby@kernel.org>, "Lubomir Rintel"<lkundrak@v3.sk>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, "Yangyu Chen"<cyy@cyyself.name>, "Conor Dooley"<conor.dooley@microchip.com>, "Inochi Amaoto"<inochiama@outlook.com>, <linux-serial@vger.kernel.org>, <linux-riscv@lists.infradead.org>, "Meng Zhang"<zhangmeng.kevin@spacemit.com>
> On 22:03 Thu 04 Jul     , Jisheng Zhang wrote:
> > On Wed, Jul 03, 2024 at 02:55:09PM +0000, Yixun Lan wrote:
> > > Found SpacemiT's K1 uart controller is compatible with
> > > Intel's Xscale uart, but it's still worth to introduce a new compatible.
> > 
> > Per vendor's kernel source code, all the uarts support 64Bytes FIFO.
> > So if it's compatible with Xscale, it's a xscale uart 64 Bytes FIFO.
> yes, I agree
> 
> further question would how to implement specific support for spacemit's k1 SoC
> one possible option to add a PORT_SPACEMIT compatible data to 8250_port.c - uart_config[]
> 
> 
> > >From this PoV, the uart isn't a Xscale but a mrvl pxa.
> see my previous comment, probably need further clarification/investigation..
> 
> > 
> > But I have one question: is the uart really a mrvl/intel pxa uart? or is just
> No, I'm unable to answer this, I'm not an employee of SpacemiT
> All informations are based on public available source + docs..
> 
> > reg programming compatible with pxa?
> > 
> To my knowledge, it's compatible with pxa, but it would be great that vendor can clarify this
Yes, the programming model is compatible with pxa.
> 
> > > 
> > > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > > ---
> > >  Documentation/devicetree/bindings/serial/8250.yaml | 4 +++-
> > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
> > > index 692aa05500fd5..0bde2379e8647 100644
> > > --- a/Documentation/devicetree/bindings/serial/8250.yaml
> > > +++ b/Documentation/devicetree/bindings/serial/8250.yaml
> > > @@ -111,7 +111,9 @@ properties:
> > >                - mediatek,mt7623-btif
> > >            - const: mediatek,mtk-btif
> > >        - items:
> > > -          - const: mrvl,mmp-uart
> > > +          - enum:
> > > +              - mrvl,mmp-uart
> > > +              - spacemit,k1-uart
> > >            - const: intel,xscale-uart
> > >        - items:
> > >            - enum:
> > > 
> > > -- 
> > > 2.45.2
> > > 
> > > 
> > > _______________________________________________
> > > linux-riscv mailing list
> > > linux-riscv@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv
> 
> -- 
> Yixun Lan (dlan)
> Gentoo Linux Developer
> GPG Key ID AABEFD55


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Re: [PATCH v3 06/11] dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible

[Greg Kroah-Hartman]

On Sat, Jul 06, 2024 at 04:02:57PM +0800, 张猛 wrote:
> This message and any attachment are confidential and may be privileged or otherwise protected from disclosure. If you are not an intended recipient of this message, please delete it and any attachment from your system and notify the sender immediately by reply e-mail. Unintended recipients should not use, copy, disclose or take any action based on this message or any information contained in this message. Emails cannot be guaranteed to be secure or error free as they can be intercepted, amended, lost or destroyed, and you should take full responsibility for security checking. 

Now deleted.

Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree

[Jisheng Zhang]

On Sat, Jul 06, 2024 at 05:05:56AM +0000, Yixun Lan wrote:
> 
> On 12:12 Sat 06 Jul     , Jisheng Zhang wrote:
> > On Fri, Jul 05, 2024 at 06:38:39AM +0000, Yixun Lan wrote:
> > > 
> > > On 21:46 Thu 04 Jul     , Jisheng Zhang wrote:
> > > > On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > > > > From: Yangyu Chen <cyy@cyyself.name>
> > > > > 
> > > > > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > > > > 
> > > > > Key features:
> > > > > - 4 cores per cluster, 2 clusters on chip
> > > > > - UART IP is Intel XScale UART
> > > > > 
> > > > > Some key considerations:
> > > > > - ISA string is inferred from vendor documentation[2]
> > > > > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > > > > - No coherent DMA on this board
> > > > >     Inferred by taking vendor ethernet and MMC drivers to the mainline
> > > > >     kernel. Without dma-noncoherent in soc node, the driver fails.
> > > > > - No cache nodes now
> > > > >     The parameters from vendor dts are likely to be wrong. It has 512
> > > > >     sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > > > >     When the size of the cache line is 64B, it is a directly mapped
> > > > >     cache rather than a set-associative cache, the latter is commonly
> > > > >     used. Thus, I didn't use the parameters from vendor dts.
> > > > > 
> > > > > Currently only support booting into console with only uart, other
> > > > > features will be added soon later.
> > > > > 
> > > > > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > > > > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > > > > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > > > > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > > > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > > > > ---
> > > > >  arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > > > >  1 file changed, 376 insertions(+)
> > > > > 
> > > > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > > new file mode 100644
> > > > > index 0000000000000..a076e35855a2e
> > > > > --- /dev/null
> > > > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > > @@ -0,0 +1,376 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > > > +/*
> > > > > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > > > > + */
> > > > > +
> > > > > +/dts-v1/;
> > > > > +/ {
> > > > > +	#address-cells = <2>;
> > > > > +	#size-cells = <2>;
> > > > > +	model = "SpacemiT K1";
> > > > > +	compatible = "spacemit,k1";
> > > > > +
> > > > > +
...
> > > > > +	soc {
> > > > > +		compatible = "simple-bus";
> > > > > +		interrupt-parent = <&plic>;
> > > > > +		#address-cells = <2>;
> > > > > +		#size-cells = <2>;
> > > > > +		dma-noncoherent;
> > > > > +		ranges;
> > > > > +
> > > > > +		uart0: serial@d4017000 {
> > > > > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > > > 
> > > > no, this is not a correct hw modeling. The doc on spacemit says
> > > > all the uart support 64 bytes FIFO, declaring xscale only makes
> > > > use of 32 bytes FIFO.
> > > yes, I also noticed it's 64 bytes FIFO
> > > 
> > > > 
> > > > IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> > > > "mrvl,pxa-uart" or "mrvl,mmp-uart"
> > > 
> > > 
> > > for mrvl,pxa-uart, I think you imply to use drivers/tty/serial/8250/8250_pxa.c,
> > > which turn out doesn't work on k1 SoC, for the record, we need to adjust
> > 
> > Really? I just tried "mrvl,pxa-uart" with rc6, it works perfectly, and the FIFO
> > in the driver logic is 64bytes now. Am I misssing something or you never tried it?
> > 
> Ok, I realised it's the clock issue
> 
> still, I'm not fully convinced about using "mrvl,pxa-uart",
> e.g this driver hardcoded tz_loadsz to 32, not sure if K1 suffer same problem
> 5208e7ced520 ("serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level")

I believe the problem commit 5208e7ced520 tries to solve is: the
mmp|pxa-uart only support threshold up to 32Bytes, tz_loadsz will be
fifo size by default, this will cause probleme with 64Bytes FIFO.

> 
> also, what's the preference when choosing driver between 8250_pxa.c vs 8250_of.c?

Good question. I have no preference. But there are two problems with
8250_of, I have sent out patches[1][2] to address them.

After these two patches, both the earlycon and uart FIFO logic work too
with below dts properties:
		uart0: serial@d4017000 {
			compatible = "mrvl,mmp-uart";
			...
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        tx-threshold = <32>;
                        fifo-size = <64>;
                        no-loopback-test;
			...
		}

Link: https://lore.kernel.org/linux-riscv/20240706082928.2238-1-jszhang@kernel.org/ [1]
Link: https://lore.kernel.org/linux-riscv/20240706101856.3077-1-jszhang@kernel.org/ [2]

> it occur to me that 8250_pxa.c is more specially tailored for pxa hardware, while
> 8250_of.c is more generic.. besides, should we consider one more step if we want to

there's a work around for Erratum #74 in 8250_pxa, while I believe the
Errata doesn't exisit in K1, so from this PoV it seems 8250_of is
better, no?

> support DMA mode in the future (vendor uart driver has DMA support)?

Adding dma engine support to 8250_of is doable.

> 
> 
> > >  drivers/tty/serial/8250/Kconfig to enable the driver for ARCH_SPACEMIT,
> > >  and change uart compatible to "spacemit,k1-uart", "mrvl,pxa-uart"
> > > 
> > > for mrvl,mmp-uart, I see two choices, one using 8250_pxa.c which has same result
> > > as mrvl,pxa-uart, another choice would using the driver of 8250_of.c 
> > > and it work as same as "intel,xscale-uart", I don't see any difference..
> > > 
> > > P.S: there is possibly a side problem that "mrvl,mmp-uart" from 8250_of.c doesn't 
> > > really compatile with "mrvl,mmp-uart" from 8250_pxa.c, but I think it's another story
> 
> -- 
> Yixun Lan (dlan)
> Gentoo Linux Developer
> GPG Key ID AABEFD55

Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree

[Yixun Lan]

On 18:40 Sat 06 Jul     , Jisheng Zhang wrote:
> On Sat, Jul 06, 2024 at 05:05:56AM +0000, Yixun Lan wrote:
> > 
> > On 12:12 Sat 06 Jul     , Jisheng Zhang wrote:
> > > On Fri, Jul 05, 2024 at 06:38:39AM +0000, Yixun Lan wrote:
> > > > 
> > > > On 21:46 Thu 04 Jul     , Jisheng Zhang wrote:
> > > > > On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > > > > > From: Yangyu Chen <cyy@cyyself.name>
> > > > > > 
> > > > > > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > > > > > 
> > > > > > Key features:
> > > > > > - 4 cores per cluster, 2 clusters on chip
> > > > > > - UART IP is Intel XScale UART
> > > > > > 
> > > > > > Some key considerations:
> > > > > > - ISA string is inferred from vendor documentation[2]
> > > > > > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > > > > > - No coherent DMA on this board
> > > > > >     Inferred by taking vendor ethernet and MMC drivers to the mainline
> > > > > >     kernel. Without dma-noncoherent in soc node, the driver fails.
> > > > > > - No cache nodes now
> > > > > >     The parameters from vendor dts are likely to be wrong. It has 512
> > > > > >     sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > > > > >     When the size of the cache line is 64B, it is a directly mapped
> > > > > >     cache rather than a set-associative cache, the latter is commonly
> > > > > >     used. Thus, I didn't use the parameters from vendor dts.
> > > > > > 
> > > > > > Currently only support booting into console with only uart, other
> > > > > > features will be added soon later.
> > > > > > 
> > > > > > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > > > > > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > > > > > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > > > > > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > > > > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > > > > > ---
> > > > > >  arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > > > > >  1 file changed, 376 insertions(+)
> > > > > > 
> > > > > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > > > new file mode 100644
> > > > > > index 0000000000000..a076e35855a2e
> > > > > > --- /dev/null
> > > > > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > > > @@ -0,0 +1,376 @@
> > > > > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > > > > +/*
> > > > > > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > > > > > + */
> > > > > > +
> > > > > > +/dts-v1/;
> > > > > > +/ {
> > > > > > +	#address-cells = <2>;
> > > > > > +	#size-cells = <2>;
> > > > > > +	model = "SpacemiT K1";
> > > > > > +	compatible = "spacemit,k1";
> > > > > > +
> > > > > > +
> ...
> > > > > > +	soc {
> > > > > > +		compatible = "simple-bus";
> > > > > > +		interrupt-parent = <&plic>;
> > > > > > +		#address-cells = <2>;
> > > > > > +		#size-cells = <2>;
> > > > > > +		dma-noncoherent;
> > > > > > +		ranges;
> > > > > > +
> > > > > > +		uart0: serial@d4017000 {
> > > > > > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > > > > 
> > > > > no, this is not a correct hw modeling. The doc on spacemit says
> > > > > all the uart support 64 bytes FIFO, declaring xscale only makes
> > > > > use of 32 bytes FIFO.
> > > > yes, I also noticed it's 64 bytes FIFO
> > > > 
> > > > > 
> > > > > IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> > > > > "mrvl,pxa-uart" or "mrvl,mmp-uart"
> > > > 
> > > > 
> > > > for mrvl,pxa-uart, I think you imply to use drivers/tty/serial/8250/8250_pxa.c,
> > > > which turn out doesn't work on k1 SoC, for the record, we need to adjust
> > > 
> > > Really? I just tried "mrvl,pxa-uart" with rc6, it works perfectly, and the FIFO
> > > in the driver logic is 64bytes now. Am I misssing something or you never tried it?
> > > 
> > Ok, I realised it's the clock issue
> > 
> > still, I'm not fully convinced about using "mrvl,pxa-uart",
> > e.g this driver hardcoded tz_loadsz to 32, not sure if K1 suffer same problem
> > 5208e7ced520 ("serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level")
> 
> I believe the problem commit 5208e7ced520 tries to solve is: the
> mmp|pxa-uart only support threshold up to 32Bytes, tz_loadsz will be
> fifo size by default, this will cause probleme with 64Bytes FIFO.
> 
yes, exactly

> > 
> > also, what's the preference when choosing driver between 8250_pxa.c vs 8250_of.c?
> 
> Good question. I have no preference. But there are two problems with
> 8250_of, I have sent out patches[1][2] to address them.
> 
> After these two patches, both the earlycon and uart FIFO logic work too
> with below dts properties:
> 		uart0: serial@d4017000 {
> 			compatible = "mrvl,mmp-uart";
to be precise, I think here should be compatible = "mrvl,mmp-uart", "intel,xscale-uart"

but can you check this patch below? it should be ok with your two proposed patches applied
https://lore.kernel.org/all/20240703-k1-01-basic-dt-v3-6-12f73b47461e@gentoo.org/

> 			...
>                         reg-shift = <2>;
>                         reg-io-width = <4>;
>                         tx-threshold = <32>;
>                         fifo-size = <64>;
..
>                         no-loopback-test;
            need to check, from vendor docs, there is a loopback mode
            see 16.2.4.1 SSCR register description, bit12

https://developer.spacemit.com/#/documentation?token=Rn9Kw3iFHirAMgkIpTAcV2Arnkf
> 			...
> 		}
> 
> Link: https://lore.kernel.org/linux-riscv/20240706082928.2238-1-jszhang@kernel.org/ [1]
I have some comments for this patch, and I believe it's a valid fix,
without this patch, K1 will also have problem duo to "UART_CAP_UUE | UART_CAP_RTOIE" lost

> Link: https://lore.kernel.org/linux-riscv/20240706101856.3077-1-jszhang@kernel.org/ [2]
> 
> > it occur to me that 8250_pxa.c is more specially tailored for pxa hardware, while
> > 8250_of.c is more generic.. besides, should we consider one more step if we want to
> 
> there's a work around for Erratum #74 in 8250_pxa, while I believe the
do you have any link for this Erratum? let's double check it..

> Errata doesn't exisit in K1, so from this PoV it seems 8250_of is
> better, no?
> 
> > support DMA mode in the future (vendor uart driver has DMA support)?
> 
> Adding dma engine support to 8250_of is doable.
Ok, sounds good to me
> 
> > 
> > 
> > > >  drivers/tty/serial/8250/Kconfig to enable the driver for ARCH_SPACEMIT,
> > > >  and change uart compatible to "spacemit,k1-uart", "mrvl,pxa-uart"
> > > > 
> > > > for mrvl,mmp-uart, I see two choices, one using 8250_pxa.c which has same result
> > > > as mrvl,pxa-uart, another choice would using the driver of 8250_of.c 
> > > > and it work as same as "intel,xscale-uart", I don't see any difference..
> > > > 
> > > > P.S: there is possibly a side problem that "mrvl,mmp-uart" from 8250_of.c doesn't 
> > > > really compatile with "mrvl,mmp-uart" from 8250_pxa.c, but I think it's another story
> > 
> > -- 
> > Yixun Lan (dlan)
> > Gentoo Linux Developer
> > GPG Key ID AABEFD55

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55

Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree

[Jisheng Zhang]

On Sat, Jul 06, 2024 at 02:24:03PM +0000, Yixun Lan wrote:
> On 18:40 Sat 06 Jul     , Jisheng Zhang wrote:
> > On Sat, Jul 06, 2024 at 05:05:56AM +0000, Yixun Lan wrote:
> > > 
> > > On 12:12 Sat 06 Jul     , Jisheng Zhang wrote:
> > > > On Fri, Jul 05, 2024 at 06:38:39AM +0000, Yixun Lan wrote:
> > > > > 
> > > > > On 21:46 Thu 04 Jul     , Jisheng Zhang wrote:
> > > > > > On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > > > > > > From: Yangyu Chen <cyy@cyyself.name>
> > > > > > > 
> > > > > > > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > > > > > > 
> > > > > > > Key features:
> > > > > > > - 4 cores per cluster, 2 clusters on chip
> > > > > > > - UART IP is Intel XScale UART
> > > > > > > 
> > > > > > > Some key considerations:
> > > > > > > - ISA string is inferred from vendor documentation[2]
> > > > > > > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > > > > > > - No coherent DMA on this board
> > > > > > >     Inferred by taking vendor ethernet and MMC drivers to the mainline
> > > > > > >     kernel. Without dma-noncoherent in soc node, the driver fails.
> > > > > > > - No cache nodes now
> > > > > > >     The parameters from vendor dts are likely to be wrong. It has 512
> > > > > > >     sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > > > > > >     When the size of the cache line is 64B, it is a directly mapped
> > > > > > >     cache rather than a set-associative cache, the latter is commonly
> > > > > > >     used. Thus, I didn't use the parameters from vendor dts.
> > > > > > > 
> > > > > > > Currently only support booting into console with only uart, other
> > > > > > > features will be added soon later.
> > > > > > > 
> > > > > > > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > > > > > > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > > > > > > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > > > > > > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > > > > > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > > > > > > ---
> > > > > > >  arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > > > > > >  1 file changed, 376 insertions(+)
> > > > > > > 
> > > > > > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > > > > new file mode 100644
> > > > > > > index 0000000000000..a076e35855a2e
> > > > > > > --- /dev/null
> > > > > > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > > > > @@ -0,0 +1,376 @@
> > > > > > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > > > > > +/*
> > > > > > > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > > > > > > + */
> > > > > > > +
> > > > > > > +/dts-v1/;
> > > > > > > +/ {
> > > > > > > +	#address-cells = <2>;
> > > > > > > +	#size-cells = <2>;
> > > > > > > +	model = "SpacemiT K1";
> > > > > > > +	compatible = "spacemit,k1";
> > > > > > > +
> > > > > > > +
> > ...
> > > > > > > +	soc {
> > > > > > > +		compatible = "simple-bus";
> > > > > > > +		interrupt-parent = <&plic>;
> > > > > > > +		#address-cells = <2>;
> > > > > > > +		#size-cells = <2>;
> > > > > > > +		dma-noncoherent;
> > > > > > > +		ranges;
> > > > > > > +
> > > > > > > +		uart0: serial@d4017000 {
> > > > > > > +			compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > > > > > 
> > > > > > no, this is not a correct hw modeling. The doc on spacemit says
> > > > > > all the uart support 64 bytes FIFO, declaring xscale only makes
> > > > > > use of 32 bytes FIFO.
> > > > > yes, I also noticed it's 64 bytes FIFO
> > > > > 
> > > > > > 
> > > > > > IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> > > > > > "mrvl,pxa-uart" or "mrvl,mmp-uart"
> > > > > 
> > > > > 
> > > > > for mrvl,pxa-uart, I think you imply to use drivers/tty/serial/8250/8250_pxa.c,
> > > > > which turn out doesn't work on k1 SoC, for the record, we need to adjust
> > > > 
> > > > Really? I just tried "mrvl,pxa-uart" with rc6, it works perfectly, and the FIFO
> > > > in the driver logic is 64bytes now. Am I misssing something or you never tried it?
> > > > 
> > > Ok, I realised it's the clock issue
> > > 
> > > still, I'm not fully convinced about using "mrvl,pxa-uart",
> > > e.g this driver hardcoded tz_loadsz to 32, not sure if K1 suffer same problem
> > > 5208e7ced520 ("serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level")
> > 
> > I believe the problem commit 5208e7ced520 tries to solve is: the
> > mmp|pxa-uart only support threshold up to 32Bytes, tz_loadsz will be
> > fifo size by default, this will cause probleme with 64Bytes FIFO.
> > 
> yes, exactly
> 
> > > 
> > > also, what's the preference when choosing driver between 8250_pxa.c vs 8250_of.c?
> > 
> > Good question. I have no preference. But there are two problems with
> > 8250_of, I have sent out patches[1][2] to address them.
> > 
> > After these two patches, both the earlycon and uart FIFO logic work too
> > with below dts properties:
> > 		uart0: serial@d4017000 {
> > 			compatible = "mrvl,mmp-uart";
> to be precise, I think here should be compatible = "mrvl,mmp-uart", "intel,xscale-uart"

see below.

> 
> but can you check this patch below? it should be ok with your two proposed patches applied
> https://lore.kernel.org/all/20240703-k1-01-basic-dt-v3-6-12f73b47461e@gentoo.org/
> 
> > 			...
> >                         reg-shift = <2>;
> >                         reg-io-width = <4>;
> >                         tx-threshold = <32>;
> >                         fifo-size = <64>;

I just tried, the previous "spacemit,k1-uart", "intel,xscale-uart"; with above properties
work too, and the fifo size in driver logic seems correct as well.

> ..
> >                         no-loopback-test;
>             need to check, from vendor docs, there is a loopback mode

oh, this property is from the UPF_SKIP_TEST of 8250_pxa.c. This
property can be removed.

>             see 16.2.4.1 SSCR register description, bit12
> 
> https://developer.spacemit.com/#/documentation?token=Rn9Kw3iFHirAMgkIpTAcV2Arnkf
> > 			...
> > 		}
> > 
> > Link: https://lore.kernel.org/linux-riscv/20240706082928.2238-1-jszhang@kernel.org/ [1]
> I have some comments for this patch, and I believe it's a valid fix,
> without this patch, K1 will also have problem duo to "UART_CAP_UUE | UART_CAP_RTOIE" lost
> 
> > Link: https://lore.kernel.org/linux-riscv/20240706101856.3077-1-jszhang@kernel.org/ [2]
> > 
> > > it occur to me that 8250_pxa.c is more specially tailored for pxa hardware, while
> > > 8250_of.c is more generic.. besides, should we consider one more step if we want to
> > 
> > there's a work around for Erratum #74 in 8250_pxa, while I believe the
> do you have any link for this Erratum? let's double check it..

I can't find any link now :(

> 
> > Errata doesn't exisit in K1, so from this PoV it seems 8250_of is
> > better, no?
> > 
> > > support DMA mode in the future (vendor uart driver has DMA support)?
> > 
> > Adding dma engine support to 8250_of is doable.
> Ok, sounds good to me
> > 
> > > 
> > > 
> > > > >  drivers/tty/serial/8250/Kconfig to enable the driver for ARCH_SPACEMIT,
> > > > >  and change uart compatible to "spacemit,k1-uart", "mrvl,pxa-uart"
> > > > > 
> > > > > for mrvl,mmp-uart, I see two choices, one using 8250_pxa.c which has same result
> > > > > as mrvl,pxa-uart, another choice would using the driver of 8250_of.c 
> > > > > and it work as same as "intel,xscale-uart", I don't see any difference..
> > > > > 
> > > > > P.S: there is possibly a side problem that "mrvl,mmp-uart" from 8250_of.c doesn't 
> > > > > really compatile with "mrvl,mmp-uart" from 8250_pxa.c, but I think it's another story
> > > 
> > > -- 
> > > Yixun Lan (dlan)
> > > Gentoo Linux Developer
> > > GPG Key ID AABEFD55
> 
> -- 
> Yixun Lan (dlan)
> Gentoo Linux Developer
> GPG Key ID AABEFD55