From: Jisheng Zhang <jszhang@kernel.org>
To: Yixun Lan <dlan@gentoo.org>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Conor Dooley <conor@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Samuel Holland <samuel.holland@sifive.com>,
Anup Patel <anup@brainfault.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
Lubomir Rintel <lkundrak@v3.sk>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Yangyu Chen <cyy@cyyself.name>,
Inochi Amaoto <inochiama@outlook.com>,
linux-serial@vger.kernel.org, linux-riscv@lists.infradead.org,
Meng Zhang <zhangmeng.kevin@spacemit.com>
Subject: Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
Date: Sat, 6 Jul 2024 12:12:00 +0800 [thread overview]
Message-ID: <ZojEEAdUwxPJwqIS@xhacker> (raw)
In-Reply-To: <20240705063839.GA3042186@ofsar>
On Fri, Jul 05, 2024 at 06:38:39AM +0000, Yixun Lan wrote:
>
> On 21:46 Thu 04 Jul , Jisheng Zhang wrote:
> > On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > > From: Yangyu Chen <cyy@cyyself.name>
> > >
> > > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > >
> > > Key features:
> > > - 4 cores per cluster, 2 clusters on chip
> > > - UART IP is Intel XScale UART
> > >
> > > Some key considerations:
> > > - ISA string is inferred from vendor documentation[2]
> > > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > > - No coherent DMA on this board
> > > Inferred by taking vendor ethernet and MMC drivers to the mainline
> > > kernel. Without dma-noncoherent in soc node, the driver fails.
> > > - No cache nodes now
> > > The parameters from vendor dts are likely to be wrong. It has 512
> > > sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > > When the size of the cache line is 64B, it is a directly mapped
> > > cache rather than a set-associative cache, the latter is commonly
> > > used. Thus, I didn't use the parameters from vendor dts.
> > >
> > > Currently only support booting into console with only uart, other
> > > features will be added soon later.
> > >
> > > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > > ---
> > > arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > > 1 file changed, 376 insertions(+)
> > >
> > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > new file mode 100644
> > > index 0000000000000..a076e35855a2e
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > @@ -0,0 +1,376 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > +/*
> > > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > > + */
> > > +
> > > +/dts-v1/;
> > > +/ {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + model = "SpacemiT K1";
> > > + compatible = "spacemit,k1";
> > > +
> > > + aliases {
> > > + serial0 = &uart0;
> > > + serial1 = &uart2;
> > > + serial2 = &uart3;
> > > + serial3 = &uart4;
> > > + serial4 = &uart5;
> > > + serial5 = &uart6;
> > > + serial6 = &uart7;
> > > + serial7 = &uart8;
> > > + serial8 = &uart9;
> > > + };
> > > +
> > > + cpus {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + timebase-frequency = <24000000>;
> > > +
> > > + cpu-map {
> > > + cluster0 {
> > > + core0 {
> > > + cpu = <&cpu_0>;
> > > + };
> > > + core1 {
> > > + cpu = <&cpu_1>;
> > > + };
> > > + core2 {
> > > + cpu = <&cpu_2>;
> > > + };
> > > + core3 {
> > > + cpu = <&cpu_3>;
> > > + };
> > > + };
> > > +
> > > + cluster1 {
> > > + core0 {
> > > + cpu = <&cpu_4>;
> > > + };
> > > + core1 {
> > > + cpu = <&cpu_5>;
> > > + };
> > > + core2 {
> > > + cpu = <&cpu_6>;
> > > + };
> > > + core3 {
> > > + cpu = <&cpu_7>;
> > > + };
> > > + };
> > > + };
> > > +
> > > + cpu_0: cpu@0 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <0>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu0_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_1: cpu@1 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <1>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu1_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_2: cpu@2 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <2>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu2_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_3: cpu@3 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <3>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu3_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_4: cpu@4 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <4>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu4_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_5: cpu@5 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <5>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu5_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_6: cpu@6 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <6>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu6_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_7: cpu@7 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <7>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu7_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + };
> > > +
> > > + soc {
> > > + compatible = "simple-bus";
> > > + interrupt-parent = <&plic>;
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + dma-noncoherent;
> > > + ranges;
> > > +
> > > + uart0: serial@d4017000 {
> > > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> >
> > no, this is not a correct hw modeling. The doc on spacemit says
> > all the uart support 64 bytes FIFO, declaring xscale only makes
> > use of 32 bytes FIFO.
> yes, I also noticed it's 64 bytes FIFO
>
> >
> > IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> > "mrvl,pxa-uart" or "mrvl,mmp-uart"
>
>
> for mrvl,pxa-uart, I think you imply to use drivers/tty/serial/8250/8250_pxa.c,
> which turn out doesn't work on k1 SoC, for the record, we need to adjust
Really? I just tried "mrvl,pxa-uart" with rc6, it works perfectly, and the FIFO
in the driver logic is 64bytes now. Am I misssing something or you never tried it?
> drivers/tty/serial/8250/Kconfig to enable the driver for ARCH_SPACEMIT,
> and change uart compatible to "spacemit,k1-uart", "mrvl,pxa-uart"
>
> for mrvl,mmp-uart, I see two choices, one using 8250_pxa.c which has same result
> as mrvl,pxa-uart, another choice would using the driver of 8250_of.c
> and it work as same as "intel,xscale-uart", I don't see any difference..
>
> P.S: there is possibly a side problem that "mrvl,mmp-uart" from 8250_of.c doesn't
> really compatile with "mrvl,mmp-uart" from 8250_pxa.c, but I think it's another story
next prev parent reply other threads:[~2024-07-06 4:26 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-03 14:55 [PATCH v3 00/11] riscv: add initial support for SpacemiT K1 Yixun Lan
2024-07-03 14:55 ` [PATCH v3 01/11] dt-bindings: vendor-prefixes: add spacemit Yixun Lan
2024-07-03 14:55 ` [PATCH v3 02/11] dt-bindings: riscv: Add SpacemiT X60 compatibles Yixun Lan
2024-07-03 14:55 ` [PATCH v3 03/11] dt-bindings: riscv: add SpacemiT K1 bindings Yixun Lan
2024-07-03 16:35 ` Matthias Brugger
2024-07-03 14:55 ` [PATCH v3 04/11] dt-bindings: timer: Add SpacemiT K1 CLINT Yixun Lan
2024-07-03 14:55 ` [PATCH v3 05/11] dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC Yixun Lan
2024-07-03 16:00 ` Conor Dooley
2024-07-03 14:55 ` [PATCH v3 06/11] dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible Yixun Lan
2024-07-04 14:03 ` Jisheng Zhang
2024-07-05 6:47 ` Yixun Lan
2024-07-06 8:02 ` 张猛
2024-07-06 8:05 ` Greg Kroah-Hartman
2024-07-03 14:55 ` [PATCH v3 07/11] riscv: add SpacemiT SoC family Kconfig support Yixun Lan
2024-07-03 14:55 ` [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree Yixun Lan
2024-07-04 1:17 ` Jesse Taube
2024-07-04 11:39 ` Yixun Lan
2024-07-04 13:46 ` Jisheng Zhang
2024-07-04 14:18 ` Jisheng Zhang
2024-07-05 6:38 ` Yixun Lan
2024-07-06 4:12 ` Jisheng Zhang [this message]
2024-07-06 5:05 ` Yixun Lan
2024-07-06 10:40 ` Jisheng Zhang
2024-07-06 14:24 ` Yixun Lan
2024-07-08 12:31 ` Jisheng Zhang
2024-07-05 5:55 ` 张猛
2024-07-05 6:28 ` Conor Dooley
2024-07-03 14:55 ` [PATCH v3 09/11] riscv: dts: spacemit: add Banana Pi BPI-F3 board " Yixun Lan
2024-07-03 14:55 ` [PATCH v3 10/11] riscv: defconfig: enable SpacemiT SoC Yixun Lan
2024-07-04 0:48 ` Jesse Taube
2024-07-03 14:55 ` [PATCH v3 11/11] riscv: dts: spacemit: add uart1 node for K1 SoC Yixun Lan
2024-07-04 14:05 ` Jisheng Zhang
2024-07-05 6:49 ` Yixun Lan
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