Re: [PATCH] arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe

[Johan Hovold <johan@kernel.org>]

On Thu, Jul 11, 2024 at 10:11:53PM +0530, Manivannan Sadhasivam wrote:
> On Thu, Jul 11, 2024 at 09:49:52PM +0530, Manivannan Sadhasivam wrote:
> > On Thu, Jul 11, 2024 at 05:01:15PM +0200, Johan Hovold wrote:

> > > > Also note that the errors happen also without this patch applied, they
> > > > are just being reported now.

> > > Perhaps something is off because we're running the link at half width?
> > 
> > My hunch is the PHY settings. But Abel cross checked the PHY settings with
> > internal documentation and they seem to match. Also, Qcom submitted a series
> > that is supposed to fix stability issues with Gen4 [1]. With this series, Gen 4
> > x4 setup is working on SA8775P-RIDE board as reported by Qcom. But Abel
> > confirmed that it didn't help him with the link downgrade issue.
> > 
> > Perhaps you can give it a try and see if it makes any difference for
> > this issue?

If there are known issues with running at Gen4 speed without that
series, then it seems quite likely that doing so anyway could also cause
correctable errors.

Unfortunately, I get a hypervisor reset when I tried booting with that
series so there appears to be some implicit dependency on something
else (e.g. the 4l stuff).

> One thing I confirmed is, we definitely need different PHY sequence for using
> 2L. The current PHY settings are for 4L, so limiting the lane count from the
> controller is going to be problematic. And AER errors might be due to that as
> well.

Another good point. But we currently use the
"qcom,x1e80100-qmp-gen4x2-pcie-phy" settings. Shouldn't those be for x2,
and then Abel has another series that adds the x4 settings? Or are you
saying that the currently merged "gen4x2" settings are really for 4l?

Johan