[PATCH 0/7] arm64: dts: qcom: x1e80100: PCIe fixes and CRD modem support

[PATCH 0/7] arm64: dts: qcom: x1e80100: PCIe fixes and CRD modem support

[Johan Hovold]

This series fixes some issues with the current x1e80100 PCIe support,
adds the PCIe5 nodes and enables the modem on the CRD.

The fixes should go into 6.11, but the modem support depends on them so
I decided to send everything in one series.

Johan


Johan Hovold (7):
  arm64: dts: qcom: x1e80100-crd: fix PCIe4 PHY supply
  arm64: dts: qcom: x1e80100: fix PCIe domain numbers
  arm64: dts: qcom: x1e80100-crd: fix up PCIe6a pinctrl node
  arm64: dts: qcom: x1e80100-crd: disable PCIe6A perst pull down
  arm64: dts: qcom: x1e80100-crd: fix missing PCIe4 gpios
  arm64: dts: qcom: x1e80100: add PCIe5 nodes
  arm64: dts: qcom: x1e80100-crd: enable SDX65 modem

 arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 110 +++++++++++++++++--
 arch/arm64/boot/dts/qcom/x1e80100.dtsi    | 125 +++++++++++++++++++++-
 2 files changed, 224 insertions(+), 11 deletions(-)

-- 
2.44.2

[PATCH 1/7] arm64: dts: qcom: x1e80100-crd: fix PCIe4 PHY supply

[Johan Hovold]

The PCIe4 PHY is powered by vreg_l3i (not vreg_l3j).

Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support")
Cc: stable@vger.kernel.org	# 6.9
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
index f97c80b4077c..6aa2ec1e7919 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
@@ -788,7 +788,7 @@ &pcie4 {
 };
 
 &pcie4_phy {
-	vdda-phy-supply = <&vreg_l3j_0p8>;
+	vdda-phy-supply = <&vreg_l3i_0p8>;
 	vdda-pll-supply = <&vreg_l3e_1p2>;
 
 	status = "okay";
-- 
2.44.2

Re: [PATCH 1/7] arm64: dts: qcom: x1e80100-crd: fix PCIe4 PHY supply

[Konrad Dybcio]

On 19.07.2024 3:17 PM, Johan Hovold wrote:
> The PCIe4 PHY is powered by vreg_l3i (not vreg_l3j).
> 
> Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support")
> Cc: stable@vger.kernel.org	# 6.9
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---

Mind fixing that up on all laptops?

Most of them are 80-85% CRD copypaste designs and regulators for
precise things like PHYs are generally predefined for a set of PMICs

Konrad

Re: [PATCH 1/7] arm64: dts: qcom: x1e80100-crd: fix PCIe4 PHY supply

[Johan Hovold]

On Fri, Jul 19, 2024 at 08:34:27PM +0200, Konrad Dybcio wrote:
> On 19.07.2024 3:17 PM, Johan Hovold wrote:
> > The PCIe4 PHY is powered by vreg_l3i (not vreg_l3j).
> > 
> > Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support")
> > Cc: stable@vger.kernel.org	# 6.9
> > Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> > ---
> 
> Mind fixing that up on all laptops?
> 
> Most of them are 80-85% CRD copypaste designs and regulators for
> precise things like PHYs are generally predefined for a set of PMICs

Sure. I worry that this blind fate in copy-pasting is going to bite
people, but it seems like at least the PCIe PHY regulators were shared
on sc8280xp too.

Johan

[PATCH 2/7] arm64: dts: qcom: x1e80100: fix PCIe domain numbers

[Johan Hovold]

The current PCIe domain numbers are off by one and do not match the
numbers that the UEFI firmware (and Windows) uses.

Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes")
Cc: stable@vger.kernel.org	# 6.9
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index c7aec564a318..07e00f1d1768 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -2916,7 +2916,7 @@ pcie6a: pci@1bf8000 {
 
 			dma-coherent;
 
-			linux,pci-domain = <7>;
+			linux,pci-domain = <6>;
 			num-lanes = <2>;
 
 			interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
@@ -3037,7 +3037,7 @@ pcie4: pci@1c08000 {
 
 			dma-coherent;
 
-			linux,pci-domain = <5>;
+			linux,pci-domain = <4>;
 			num-lanes = <2>;
 
 			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.44.2

Re: [PATCH 2/7] arm64: dts: qcom: x1e80100: fix PCIe domain numbers

[Konrad Dybcio]

On 19.07.2024 3:17 PM, Johan Hovold wrote:
> The current PCIe domain numbers are off by one and do not match the
> numbers that the UEFI firmware (and Windows) uses.
> 
> Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes")
> Cc: stable@vger.kernel.org	# 6.9
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---

can confirm dsdt calls them this

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad

[PATCH 3/7] arm64: dts: qcom: x1e80100-crd: fix up PCIe6a pinctrl node

[Johan Hovold]

The PCIe6a pinctrl node appears to have been copied from the sc8280xp
CRD dts, which has the NVMe on pcie2a and uses some funny indentation.

Fix up the node name to match the x1e80100 use and label and use only
tabs for indentation.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
index 6aa2ec1e7919..41d05ce01cbb 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
@@ -975,7 +975,7 @@ nvme_reg_en: nvme-reg-en-state {
 		bias-disable;
 	};
 
-	pcie6a_default: pcie2a-default-state {
+	pcie6a_default: pcie6a-default-state {
 		clkreq-n-pins {
 			pins = "gpio153";
 			function = "pcie6a_clk";
@@ -991,11 +991,11 @@ perst-n-pins {
 		};
 
 		wake-n-pins {
-		       pins = "gpio154";
-		       function = "gpio";
-		       drive-strength = <2>;
-		       bias-pull-up;
-	       };
+			pins = "gpio154";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
 	};
 
 	tpad_default: tpad-default-state {
-- 
2.44.2

Re: [PATCH 3/7] arm64: dts: qcom: x1e80100-crd: fix up PCIe6a pinctrl node

[Konrad Dybcio]

On 19.07.2024 3:17 PM, Johan Hovold wrote:
> The PCIe6a pinctrl node appears to have been copied from the sc8280xp
> CRD dts, which has the NVMe on pcie2a and uses some funny indentation.
> 
> Fix up the node name to match the x1e80100 use and label and use only
> tabs for indentation.
> 
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad

[PATCH 4/7] arm64: dts: qcom: x1e80100-crd: disable PCIe6a perst pull down

[Johan Hovold]

Disable the PCIe6a perst pull-down resistor to save some power.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
index 41d05ce01cbb..7406f1ad9c55 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
@@ -987,7 +987,7 @@ perst-n-pins {
 			pins = "gpio152";
 			function = "gpio";
 			drive-strength = <2>;
-			bias-pull-down;
+			bias-disable;
 		};
 
 		wake-n-pins {
-- 
2.44.2

Re: [PATCH 4/7] arm64: dts: qcom: x1e80100-crd: disable PCIe6a perst pull down

[Konrad Dybcio]

On 19.07.2024 3:17 PM, Johan Hovold wrote:
> Disable the PCIe6a perst pull-down resistor to save some power.
> 
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad

[PATCH 5/7] arm64: dts: qcom: x1e80100-crd: fix missing PCIe4 gpios

[Johan Hovold]

Add the missing PCIe4 perst, wake and clkreq GPIOs.

Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support")
Cc: stable@vger.kernel.org	# 6.9
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 29 +++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
index 7406f1ad9c55..72d9feec907b 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
@@ -784,6 +784,12 @@ &mdss_dp3_phy {
 };
 
 &pcie4 {
+	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie4_default>;
+
 	status = "okay";
 };
 
@@ -975,6 +981,29 @@ nvme_reg_en: nvme-reg-en-state {
 		bias-disable;
 	};
 
+	pcie4_default: pcie4-default-state {
+		clkreq-n-pins {
+			pins = "gpio147";
+			function = "pcie4_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio146";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio148";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
 	pcie6a_default: pcie6a-default-state {
 		clkreq-n-pins {
 			pins = "gpio153";
-- 
2.44.2

Re: [PATCH 5/7] arm64: dts: qcom: x1e80100-crd: fix missing PCIe4 gpios

[Konrad Dybcio]

On 19.07.2024 3:17 PM, Johan Hovold wrote:
> Add the missing PCIe4 perst, wake and clkreq GPIOs.
> 
> Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support")
> Cc: stable@vger.kernel.org	# 6.9
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---
>  arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 29 +++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> index 7406f1ad9c55..72d9feec907b 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> @@ -784,6 +784,12 @@ &mdss_dp3_phy {
>  };
>  
>  &pcie4 {
> +	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> +	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> +
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie4_default>;

property-n
property-names

please

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad

Re: [PATCH 5/7] arm64: dts: qcom: x1e80100-crd: fix missing PCIe4 gpios

[Johan Hovold]

On Fri, Jul 19, 2024 at 08:36:33PM +0200, Konrad Dybcio wrote:
> On 19.07.2024 3:17 PM, Johan Hovold wrote:
> > Add the missing PCIe4 perst, wake and clkreq GPIOs.
> > 
> > Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support")
> > Cc: stable@vger.kernel.org	# 6.9
> > Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> > ---
> >  arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 29 +++++++++++++++++++++++
> >  1 file changed, 29 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> > index 7406f1ad9c55..72d9feec907b 100644
> > --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> > +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> > @@ -784,6 +784,12 @@ &mdss_dp3_phy {
> >  };
> >  
> >  &pcie4 {
> > +	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> > +	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> > +
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pcie4_default>;
> 
> property-n
> property-names

This would make the x1e80100 pcie nodes inconsistent as this pattern is
already used for pcie6a as well as the vast majority of all our upstream
devicetrees (13k vs 3k) and bindings.

I know this is a pet peeve of yours, but perhaps it's better to just
accept this exception (naming multiple pinctrl-N properties is also
different from naming individual cells like in reg-names, if you need
more motivation).

Johan

[PATCH 6/7] arm64: dts: qcom: x1e80100: add PCIe5 nodes

[Johan Hovold]

Describe the fifth PCIe controller and its PHY.

Note that using the GIC ITS with PCIe5 does not work currently so the
ITS mapping is left unspecified for now.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 121 ++++++++++++++++++++++++-
 1 file changed, 120 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 07e00f1d1768..e8acb1180857 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -760,7 +760,7 @@ gcc: clock-controller@100000 {
 				 <&sleep_clk>,
 				 <0>,
 				 <&pcie4_phy>,
-				 <0>,
+				 <&pcie5_phy>,
 				 <&pcie6a_phy>,
 				 <0>,
 				 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
@@ -3014,6 +3014,125 @@ pcie6a_phy: phy@1bfc000 {
 			status = "disabled";
 		};
 
+		pcie5: pci@1c00000 {
+			device_type = "pci";
+			compatible = "qcom,pcie-x1e80100";
+			reg = <0 0x01c00000 0 0x3000>,
+			      <0 0x7e000000 0 0xf1d>,
+			      <0 0x7e000f40 0 0xa8>,
+			      <0 0x7e001000 0 0x1000>,
+			      <0 0x7e100000 0 0x100000>,
+			      <0 0x01c03000 0 0x1000>;
+			reg-names = "parf",
+				    "dbi",
+				    "elbi",
+				    "atu",
+				    "config",
+				    "mhi";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>;
+			bus-range = <0x00 0xff>;
+
+			dma-coherent;
+
+			linux,pci-domain = <5>;
+			num-lanes = <2>;
+
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
+				 <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_5_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
+				 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
+			clock-names = "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "noc_aggr",
+				      "cnoc_sf_axi";
+
+			assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
+			assigned-clock-rates = <19200000>;
+
+			interconnects = <&pcie_south_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "pcie-mem",
+					     "cpu-pcie";
+
+			resets = <&gcc GCC_PCIE_5_BCR>,
+				 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>;
+			reset-names = "pci",
+				      "link_down";
+
+			power-domains = <&gcc GCC_PCIE_5_GDSC>;
+
+			phys = <&pcie5_phy>;
+			phy-names = "pciephy";
+
+			status = "disabled";
+		};
+
+		pcie5_phy: phy@1c06000 {
+			compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
+			reg = <0 0x01c06000 0 0x2000>;
+
+			clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
+				 <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>,
+				 <&gcc GCC_PCIE_5_PIPE_CLK>;
+			clock-names = "aux",
+				      "cfg_ahb",
+				      "ref",
+				      "rchng",
+				      "pipe";
+
+			resets = <&gcc GCC_PCIE_5_PHY_BCR>;
+			reset-names = "phy";
+
+			assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "pcie5_pipe_clk";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
 		pcie4: pci@1c08000 {
 			device_type = "pci";
 			compatible = "qcom,pcie-x1e80100";
-- 
2.44.2

Re: [PATCH 6/7] arm64: dts: qcom: x1e80100: add PCIe5 nodes

[Konrad Dybcio]

On 19.07.2024 3:17 PM, Johan Hovold wrote:
> Describe the fifth PCIe controller and its PHY.
> 
> Note that using the GIC ITS with PCIe5 does not work currently so the
> ITS mapping is left unspecified for now.
> 
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

feel free to also add

required-opps = <&rpmhpd_opp_nom>;

under all PCIe hosts, or wait for [1] to land

Konrad

[1] https://lore.kernel.org/linux-arm-msm/20240518-opp_support-v13-4-78c73edf50de@quicinc.com/

Re: [PATCH 6/7] arm64: dts: qcom: x1e80100: add PCIe5 nodes

[Johan Hovold]

On Fri, Jul 19, 2024 at 08:39:05PM +0200, Konrad Dybcio wrote:
> On 19.07.2024 3:17 PM, Johan Hovold wrote:
> > Describe the fifth PCIe controller and its PHY.
> > 
> > Note that using the GIC ITS with PCIe5 does not work currently so the
> > ITS mapping is left unspecified for now.
> > 
> > Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> > ---
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> 
> feel free to also add
> 
> required-opps = <&rpmhpd_opp_nom>;

Sure, thanks for the reminder.

Johan

[PATCH 7/7] arm64: dts: qcom: x1e80100-crd: enable SDX65 modem

[Johan Hovold]

Enable PCIe5 and the SDX65 modem.

Note that the modem may need to be flashed with firmware before use.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 65 +++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
index 72d9feec907b..e7bc283a0da9 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
@@ -301,6 +301,22 @@ vreg_nvme: regulator-nvme {
 		pinctrl-names = "default";
 		pinctrl-0 = <&nvme_reg_en>;
 	};
+
+	vreg_wwan: regulator-wwan {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDX_VPH_PWR";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&wwan_sw_en>;
+
+		regulator-boot-on;
+	};
 };
 
 &apps_rsc {
@@ -800,6 +816,25 @@ &pcie4_phy {
 	status = "okay";
 };
 
+&pcie5 {
+	perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_wwan>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie5_default>;
+
+	status = "okay";
+};
+
+&pcie5_phy {
+	vdda-phy-supply = <&vreg_l3i_0p8>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
 &pcie6a {
 	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
 	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
@@ -1004,6 +1039,29 @@ wake-n-pins {
 		};
 	};
 
+	pcie5_default: pcie5-default-state {
+		clkreq-n-pins {
+			pins = "gpio150";
+			function = "pcie5_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio149";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio151";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
 	pcie6a_default: pcie6a-default-state {
 		clkreq-n-pins {
 			pins = "gpio153";
@@ -1055,6 +1113,13 @@ wcd_default: wcd-reset-n-active-state {
 		bias-disable;
 		output-low;
 	};
+
+	wwan_sw_en: wwan-sw-en-state {
+		pins = "gpio221";
+		function = "gpio";
+		drive-strength = <4>;
+		bias-disable;
+	};
 };
 
 &uart21 {
-- 
2.44.2

Re: [PATCH 7/7] arm64: dts: qcom: x1e80100-crd: enable SDX65 modem

[Konrad Dybcio]

On 19.07.2024 3:17 PM, Johan Hovold wrote:
> Enable PCIe5 and the SDX65 modem.
> 
> Note that the modem may need to be flashed with firmware before use.
> 
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> ---
>  arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 65 +++++++++++++++++++++++
>  1 file changed, 65 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> index 72d9feec907b..e7bc283a0da9 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> @@ -301,6 +301,22 @@ vreg_nvme: regulator-nvme {
>  		pinctrl-names = "default";
>  		pinctrl-0 = <&nvme_reg_en>;
>  	};
> +
> +	vreg_wwan: regulator-wwan {
> +		compatible = "regulator-fixed";
> +
> +		regulator-name = "SDX_VPH_PWR";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +
> +		gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&wwan_sw_en>;

property-n
property-names

here and below, please

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad

Re: [PATCH 0/7] arm64: dts: qcom: x1e80100: PCIe fixes and CRD modem support

[Rob Herring (Arm)]

On Fri, 19 Jul 2024 15:17:15 +0200, Johan Hovold wrote:
> This series fixes some issues with the current x1e80100 PCIe support,
> adds the PCIe5 nodes and enables the modem on the CRD.
> 
> The fixes should go into 6.11, but the modem support depends on them so
> I decided to send everything in one series.
> 
> Johan
> 
> 
> Johan Hovold (7):
>   arm64: dts: qcom: x1e80100-crd: fix PCIe4 PHY supply
>   arm64: dts: qcom: x1e80100: fix PCIe domain numbers
>   arm64: dts: qcom: x1e80100-crd: fix up PCIe6a pinctrl node
>   arm64: dts: qcom: x1e80100-crd: disable PCIe6A perst pull down
>   arm64: dts: qcom: x1e80100-crd: fix missing PCIe4 gpios
>   arm64: dts: qcom: x1e80100: add PCIe5 nodes
>   arm64: dts: qcom: x1e80100-crd: enable SDX65 modem
> 
>  arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 110 +++++++++++++++++--
>  arch/arm64/boot/dts/qcom/x1e80100.dtsi    | 125 +++++++++++++++++++++-
>  2 files changed, 224 insertions(+), 11 deletions(-)
> 
> --
> 2.44.2
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y qcom/x1e80100-crd.dtb' for 20240719131722.8343-1-johan+linaro@kernel.org:

arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: pci@1c00000: Unevaluated properties are not allowed ('vddpe-3v3-supply' was unexpected)
	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#

Re: [PATCH 0/7] arm64: dts: qcom: x1e80100: PCIe fixes and CRD modem support

[Johan Hovold]

On Mon, Jul 22, 2024 at 08:57:30PM -0600, Rob Herring wrote:
> On Fri, 19 Jul 2024 15:17:15 +0200, Johan Hovold wrote:
> > This series fixes some issues with the current x1e80100 PCIe support,
> > adds the PCIe5 nodes and enables the modem on the CRD.
> > 
> > The fixes should go into 6.11, but the modem support depends on them so
> > I decided to send everything in one series.

> > Johan Hovold (7):
> >   arm64: dts: qcom: x1e80100-crd: fix PCIe4 PHY supply
> >   arm64: dts: qcom: x1e80100: fix PCIe domain numbers
> >   arm64: dts: qcom: x1e80100-crd: fix up PCIe6a pinctrl node
> >   arm64: dts: qcom: x1e80100-crd: disable PCIe6A perst pull down
> >   arm64: dts: qcom: x1e80100-crd: fix missing PCIe4 gpios
> >   arm64: dts: qcom: x1e80100: add PCIe5 nodes
> >   arm64: dts: qcom: x1e80100-crd: enable SDX65 modem
> > 
> >  arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 110 +++++++++++++++++--
> >  arch/arm64/boot/dts/qcom/x1e80100.dtsi    | 125 +++++++++++++++++++++-
> >  2 files changed, 224 insertions(+), 11 deletions(-)

> My bot found new DTB warnings on the .dts files added or changed in this
> series.

> New warnings running 'make CHECK_DTBS=y qcom/x1e80100-crd.dtb' for 20240719131722.8343-1-johan+linaro@kernel.org:
> 
> arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: pci@1c00000: Unevaluated properties are not allowed ('vddpe-3v3-supply' was unexpected)
> 	from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#

I was surprised about this as this property is already used by this DT
in the upcoming 6.11-rc1 (for the NVMe).

I found this thread were Abel tried to add the property to the new
dedicated x1e80100 schema, but received some push back:

	https://lore.kernel.org/lkml/20240604235806.GA1903493-robh@kernel.org/

Looking at the back story for this, the alternate name 'vpcie3v3' has
been used by some non-Qualcomm controllers since 2016, while Qualcomm DT
has been using 'vddpe-3v3' since 2018. And it's been clearly documented
as part of the bindings the whole time.

Earlier this year, 'vddpe-3v3' was incorrectly removed from the Qualcomm
binding, which results in a checker warnings for a bunch old Qualcomm
DTs. I've just sent a patch to restore this Qualcomm name here:

	https://lore.kernel.org/lkml/20240723151328.684-1-johan+linaro@kernel.org/

If we want to replace the Qualcomm specific name with the alternate name
then this would need to be done by deprecating the current name, while
adding backward compatibility support for the old name to the driver.
I'm not sure anyone cares enough about this inconsistency to actually
pursue this.

Johan