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Date: Sat, 10 Aug 2024 19:18:52 +0200
From: Lorenzo Bianconi <lorenzo@kernel.org>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: linux-pwm@vger.kernel.org, ukleinek@kernel.org,
	lorenzo.bianconi83@gmail.com, krzk+dt@kernel.org, robh@kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	upstream@airoha.com, angelogioacchino.delregno@collabora.com,
	benjamin.larsson@genexis.eu, conor+dt@kernel.org,
	ansuelsmth@gmail.com
Subject: Re: [PATCH 1/2] dt-bindings: pwm: Document Airoha EN7581 PWM
Message-ID: <Zreg_OGH5ndPbTYT@lore-rh-laptop>
References: <cover.1723264979.git.lorenzo@kernel.org>
 <6a95b1d7fb90045a51a0cf51b9fafff26790904b.1723264979.git.lorenzo@kernel.org>
 <4c63b64b-b6f2-4e72-95c5-5555681f6d10@kernel.org>
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On Aug 10, Krzysztof Kozlowski wrote:
> On 10/08/2024 06:48, Lorenzo Bianconi wrote:
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    pwm@1fbf0224 {
> > +        compatible =3D "airoha,en7581-pwm";
> > +        reg =3D <0x1fbf0224 0x10>,
> > +              <0x1fbf0238 0x28>,
> > +              <0x1fbf0298 0x8>;
>=20
> These look almost continuous, so I wonder what's in between? E.g.
> between 0x1fbf0224+10=3D0x1fbf0234 and 0x1fbf0238?

register 0x1fbf0234 will be used by pinctrl driver (I will post it soon) for
pwm muxing. The issue here is clock, pinctrl, gpio, pwm and (future) serdes
registers are all interleaved in a non-regular fashion in the following
IO space:

- <0x1fa20000 - 0x1fa20384>=20
- <0x1fb00000 - 0x1fb0096c>
- <0x1fbf0200 - 0x1fbf02bc>

So in order to avoid conflicts we need a sparse mapping.

Regards,
Lorenzo

>=20
> Rest looks good.
>=20
> Best regards,
> Krzysztof
>=20

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