[PATCH 00/14] TQMa93xx improvements

[PATCH 00/14] TQMa93xx improvements

[Alexander Stein]

Hi all,

this series add improvements for the TQMa93xx series.
Despite changes for pad configuration as requested form hardware team, this also
adds the PMIC node which allows to specify correct supplies for e.g. eMMC.
Also GPIO lin enames are added for userspace usage using e.g. libgpiod.
This series also includes a workaround for USDHCI errata.

Best regards,
Alexander

Alexander Stein (4):
  arm64: dts: freescale: imx93-tqma9352: Add PMIC node
  arm64: dts: freescale: imx93-tqma9352: add eMMC regulators
  arm64: dts: freescale: imx93-tqma9352-mba91xxla: Add ethernet aliases
  arm64: dts: freescale: imx93-tqma9352-mba91xxca: Add ethernet aliases

Markus Niebel (10):
  arm64: dts: freescale: imx93-tqma9352: fix CMA alloc-ranges
  arm64: dts: freescale: imx93-tqma9352: improve pad configuration
  arm64: dts: freescale: imx93-tqma9352-mba93xxla: fix typo
  arm64: dts: freescale: imx93-tqma9352-mba93xxla: improve pad
    configuration
  arm64: dts: freescale: imx93-tqma9352-mba93xxla: add irq for temp
    sensor
  arm64: dts: freescale: imx93-tqma9352-mba93xxla: add GPIO line names
  arm64: dts: freescale: imx93-tqma9352-mba93xxca: improve pad
    configuration
  arm64: dts: freescale: imx93-tqma9352-mba93xxca: add RTC / temp sensor
    IRQ
  arm64: dts: freescale: imx93-tqma9352-mba93xxca: add GPIO line names
  arm64: dts: freescale: imx93-tqma9352: set SION for cmd and data pad
    of USDHC

 .../freescale/imx93-tqma9352-mba93xxca.dts    | 299 ++++++++++++-----
 .../freescale/imx93-tqma9352-mba93xxla.dts    | 308 +++++++++++++-----
 .../boot/dts/freescale/imx93-tqma9352.dtsi    | 174 +++++++---
 3 files changed, 581 insertions(+), 200 deletions(-)

-- 
2.34.1

[PATCH 01/14] arm64: dts: freescale: imx93-tqma9352: fix CMA alloc-ranges

[Alexander Stein]

From: Markus Niebel <Markus.Niebel@ew.tq-group.com>

DRAM starts at 0x80000000.

Fixes: c982ecfa7992 ("arm64: dts: freescale: add initial device tree for MBa93xxLA SBC board")
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
index edbd8cad35bc..17ccf38ebd56 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
@@ -19,7 +19,7 @@ reserved-memory {
 		linux,cma {
 			compatible = "shared-dma-pool";
 			reusable;
-			alloc-ranges = <0 0x60000000 0 0x40000000>;
+			alloc-ranges = <0 0x80000000 0 0x40000000>;
 			size = <0 0x10000000>;
 			linux,cma-default;
 		};
-- 
2.34.1

[PATCH 02/14] arm64: dts: freescale: imx93-tqma9352: improve pad configuration

[Alexander Stein]

From: Markus Niebel <Markus.Niebel@ew.tq-group.com>

- disable PU/PD if already done with external resistors
- do not configure Schmitt Trigger for outputs
- do not configure DSE / FSEL for inputs

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 .../boot/dts/freescale/imx93-tqma9352.dtsi    | 56 +++++++++++--------
 1 file changed, 32 insertions(+), 24 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
index 17ccf38ebd56..d07eca6526db 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
@@ -162,55 +162,63 @@ &wdog3 {
 &iomuxc {
 	pinctrl_flexspi1: flexspi1grp {
 		fsl,pins = <
-			MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B	0x3fe
-			MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK	0x3fe
-			MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00	0x3fe
-			MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01	0x3fe
-			MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02	0x3fe
-			MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03	0x3fe
+			/* FSEL 3  | DSE X6 */
+			MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B	0x01fe
+			MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK	0x01fe
+			/* HYS | PU | FSEL 3  | DSE X6 */
+			MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00	0x13fe
+			MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01	0x13fe
+			/* HYS | FSEL 3  | DSE X6 (external PU) */
+			MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02	0x11fe
+			MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03	0x11fe
 		>;
 	};
 
 	pinctrl_lpi2c1: lpi2c1grp {
 		fsl,pins = <
-			MX93_PAD_I2C1_SCL__LPI2C1_SCL		0x40000b9e
-			MX93_PAD_I2C1_SDA__LPI2C1_SDA		0x40000b9e
+			/* SION | OD | FSEL 3 | DSE X4 */
+			MX93_PAD_I2C1_SCL__LPI2C1_SCL		0x4000199e
+			MX93_PAD_I2C1_SDA__LPI2C1_SDA		0x4000199e
 		>;
 	};
 
 	pinctrl_pca9451: pca9451grp {
 		fsl,pins = <
-			MX93_PAD_I2C2_SDA__GPIO1_IO03		0x1306
+			/* HYS | PU */
+			MX93_PAD_I2C2_SDA__GPIO1_IO03		0x1200
 		>;
 	};
 
 	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 		fsl,pins = <
-			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x1306
+			/* FSEL 2 | DSE X2 */
+			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x106
 		>;
 	};
 
 	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <
-			/* HYS | PU | PD | FSEL_3 | X5 */
-			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
-			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x17be
-			/* HYS | PU | FSEL_3 | X5 */
-			MX93_PAD_SD1_CMD__USDHC1_CMD		0x13be
-			/* HYS | PU | FSEL_3 | X4 */
-			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x139e
-			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x139e
-			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x139e
-			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x139e
-			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x139e
-			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x139e
-			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x139e
-			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x139e
+			/* PD | FSEL 3 | DSE X5 */
+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x5be
+			/* HYS | FSEL 0 | no drive */
+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x1000
+			/* HYS | FSEL 3 | X5 */
+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x11be
+			/* HYS | FSEL 3 | X4 */
+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x119e
+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x119e
+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x119e
+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x119e
+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x119e
+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x119e
+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x119e
+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x119e
 		>;
 	};
 
 	pinctrl_wdog: wdoggrp {
 		fsl,pins = <
+			/* PU | FSEL 1 | DSE X4 */
 			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e
 		>;
 	};
-- 
2.34.1

[PATCH 03/14] arm64: dts: freescale: imx93-tqma9352: Add PMIC node

[Alexander Stein]

With driver support in place add the PMIC node and remove the
fixed-regulators for rails provided by PMIC.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 .../boot/dts/freescale/imx93-tqma9352.dtsi    | 113 ++++++++++++++----
 1 file changed, 92 insertions(+), 21 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
index d07eca6526db..ddb4f452ba2d 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
@@ -25,20 +25,6 @@ linux,cma {
 		};
 	};
 
-	reg_v1v8: regulator-v1v8 {
-		compatible = "regulator-fixed";
-		regulator-name = "V_1V8";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-	};
-
-	reg_v3v3: regulator-v3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "V_3V3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-
 	/* SD2 RST# via PMIC SW_EN */
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
@@ -47,14 +33,14 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
 		regulator-name = "VSD_3V3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
-		vin-supply = <&reg_v3v3>;
+		vin-supply = <&buck4>;
 		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 	};
 };
 
 &adc1 {
-	vref-supply = <&reg_v1v8>;
+	vref-supply = <&buck5>;
 };
 
 &flexspi1 {
@@ -105,6 +91,91 @@ se97_som: temperature-sensor@1b {
 		reg = <0x1b>;
 	};
 
+	pca9451a: pmic@25 {
+		compatible = "nxp,pca9451a";
+		reg = <0x25>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pca9451>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+		regulators {
+			/* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */
+			buck1: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			/* V_DDRQ - 1.1 LPDDR4 or 0.6 LPDDR4X */
+			buck2: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			/* V_3V3 - EEPROM, RTC, ... */
+			buck4: BUCK4{
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* V_1V8 - SPI NOR, eMMC, RAM VDD1... */
+			buck5: BUCK5{
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* V_1V1 - RAM VDD2*/
+			buck6: BUCK6 {
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* V_1V8_BBSM, fix 1.8 */
+			ldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* V_0V8_ANA */
+			ldo4: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* V_SD2 - 3.3/1.8V USDHC2 io Voltage */
+			ldo5: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+
 	pcf85063: rtc@51 {
 		compatible = "nxp,pcf85063a";
 		reg = <0x51>;
@@ -116,28 +187,28 @@ eeprom0: eeprom@53 {
 		reg = <0x53>;
 		pagesize = <16>;
 		read-only;
-		vcc-supply = <&reg_v3v3>;
+		vcc-supply = <&buck4>;
 	};
 
 	eeprom1: eeprom@57 {
 		compatible = "atmel,24c64";
 		reg = <0x57>;
 		pagesize = <32>;
-		vcc-supply = <&reg_v3v3>;
+		vcc-supply = <&buck4>;
 	};
 
 	/* protectable identification memory (part of M24C64-D @57) */
 	eeprom@5f {
 		compatible = "atmel,24c64d-wl";
 		reg = <0x5f>;
-		vcc-supply = <&reg_v3v3>;
+		vcc-supply = <&buck4>;
 	};
 
 	imu@6a {
 		compatible = "st,ism330dhcx";
 		reg = <0x6a>;
-		vdd-supply = <&reg_v3v3>;
-		vddio-supply = <&reg_v3v3>;
+		vdd-supply = <&buck4>;
+		vddio-supply = <&buck4>;
 	};
 };
 
-- 
2.34.1

[PATCH 04/14] arm64: dts: freescale: imx93-tqma9352: add eMMC regulators

[Alexander Stein]

With PMIC node in place, add the correct regulators for eMMC.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
index ddb4f452ba2d..63b02552c55d 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
@@ -217,6 +217,8 @@ &usdhc1 {
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	pinctrl-1 = <&pinctrl_usdhc1>;
 	pinctrl-2 = <&pinctrl_usdhc1>;
+	vmmc-supply = <&buck4>;
+	vqmmc-supply = <&buck5>;
 	bus-width = <8>;
 	non-removable;
 	no-sdio;
-- 
2.34.1

[PATCH 05/14] arm64: dts: freescale: imx93-tqma9352-mba93xxla: fix typo

[Alexander Stein]

From: Markus Niebel <Markus.Niebel@ew.tq-group.com>

Fix typo in assignment of SD-Card cd-gpios.

Fixes: c982ecfa7992 ("arm64: dts: freescale: add initial
device tree for MBa93xxLA SBC board")

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
index da8f19a646a9..e2ee9f5a042c 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
@@ -499,7 +499,7 @@ &usdhc2 {
 	pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
 	pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
 	pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
-	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+	cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 	vmmc-supply = <&reg_usdhc2_vmmc>;
 	bus-width = <4>;
 	no-sdio;
-- 
2.34.1

[PATCH 06/14] arm64: dts: freescale: imx93-tqma9352-mba93xxla: improve pad configuration

[Alexander Stein]

From: Markus Niebel <Markus.Niebel@ew.tq-group.com>

- disable PU/PD if already done with external resistors
- do not configure Schmitt Trigger for outputs
- do not configure DSE / FSEL for inputs
- add missing pad groups
- assign muxed GPIO pads for X1 to gpio2 node

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 .../freescale/imx93-tqma9352-mba93xxla.dts    | 237 ++++++++++++------
 1 file changed, 164 insertions(+), 73 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
index e2ee9f5a042c..c663b6585c3a 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
@@ -222,6 +222,11 @@ rtc-irq-hog {
 	};
 };
 
+&gpio2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio2>;
+};
+
 &gpio3 {
 	ethphy-eqos-irq-hog {
 		gpio-hog;
@@ -509,25 +514,39 @@ &usdhc2 {
 };
 
 &iomuxc {
+	pinctrl_afe: afegrp {
+		fsl,pins = <
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO07__GPIO2_IO07			0x011e
+			/* PD | FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO08__GPIO2_IO08			0x051e
+			/* HYS | PD */
+			MX93_PAD_GPIO_IO09__GPIO2_IO09			0x1400
+			/* HYS */
+			MX93_PAD_GPIO_IO24__GPIO2_IO24			0x1000
+		>;
+	};
+
 	pinctrl_eqos: eqosgrp {
 		fsl,pins = <
 			/* PD | FSEL_2 | DSE X4 */
-			MX93_PAD_ENET1_MDC__ENET_QOS_MDC		0x51e
-			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO		0x4000051e
-			/* PD | FSEL_2 | DSE X6 */
-			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0		0x57e
-			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1		0x57e
-			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2		0x57e
-			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3		0x57e
-			/* PD | FSEL_3 | DSE X6 */
-			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x5fe
-			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x57e
+			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x51e
+			/* SION | HYS | FSEL_2 | DSE X4 */
+			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x4000111e
+			/* HYS | FSEL_0 | DSE no drive */
+			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x1000
+			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x1000
+			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x1000
+			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x1000
+			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x1000
+			/* HYS | PD | FSEL_0 | DSE no drive */
+			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x1400
 			/* PD | FSEL_2 | DSE X4 */
-			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0		0x51e
-			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1		0x51e
-			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2		0x51e
-			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3		0x51e
-			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x51e
+			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x51e
+			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x51e
+			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x51e
+			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x51e
+			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x51e
 			/* PD | FSEL_3 | DSE X3 */
 			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e
 		>;
@@ -535,7 +554,8 @@ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e
 
 	pinctrl_eqos_phy: eqosphygrp {
 		fsl,pins = <
-			MX93_PAD_CCM_CLKO1__GPIO3_IO26		0x1306
+			/* HYS | FSEL_0 | DSE no drive */
+			MX93_PAD_CCM_CLKO1__GPIO3_IO26			0x1000
 		>;
 	};
 
@@ -543,15 +563,16 @@ pinctrl_fec: fecgrp {
 		fsl,pins = <
 			/* PD | FSEL_2 | DSE X4 */
 			MX93_PAD_ENET2_MDC__ENET1_MDC			0x51e
-			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000051e
-			/* PD | FSEL_2 | DSE X6 */
-			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e
-			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e
-			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e
-			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e
-			/* PD | FSEL_3 | DSE X6 */
-			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x5fe
-			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e
+			/* SION | HYS | FSEL_2 | DSE X4 */
+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000111e
+			/* HYS | FSEL_0 | DSE no drive */
+			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x1000
+			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x1000
+			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x1000
+			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x1000
+			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x1000
+			/* HYS | PD | FSEL_0 | DSE no drive */
+			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x1400
 			/* PD | FSEL_2 | DSE X4 */
 			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x51e
 			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x51e
@@ -565,139 +586,209 @@ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x58e
 
 	pinctrl_fec_phy: fecphygrp {
 		fsl,pins = <
-			MX93_PAD_CCM_CLKO2__GPIO3_IO27		0x1306
+			/* HYS | FSEL_0 | DSE no drive */
+			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x1000
 		>;
 	};
 
 	pinctrl_flexcan1: flexcan1grp {
 		fsl,pins = <
-			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e
-			MX93_PAD_PDM_CLK__CAN1_TX		0x139e
+			/* HYS | PU | FSEL_0 | DSE no drive */
+			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX		0x1200
+			/* PU | FSEL_3 | DSE X4 */
+			MX93_PAD_PDM_CLK__CAN1_TX			0x039e
 		>;
 	};
 
 	pinctrl_flexcan2: flexcan2grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO25__CAN2_TX		0x139e
-			MX93_PAD_GPIO_IO27__CAN2_RX		0x139e
+			/* HYS | PU | FSEL_0 | DSE no drive */
+			MX93_PAD_GPIO_IO27__CAN2_RX			0x1200
+			/* PU | FSEL_3 | DSE X4 */
+			MX93_PAD_GPIO_IO25__CAN2_TX			0x039e
+		>;
+	};
+
+	pinctrl_gpio2: gpio2grp {
+		fsl,pins = <
+			/* HYS | PD | FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO16__GPIO2_IO16			0x151e
+			MX93_PAD_GPIO_IO17__GPIO2_IO17			0x151e
+			MX93_PAD_GPIO_IO18__GPIO2_IO18			0x151e
+			MX93_PAD_GPIO_IO19__GPIO2_IO19			0x151e
+			MX93_PAD_GPIO_IO20__GPIO2_IO20			0x151e
+			MX93_PAD_GPIO_IO21__GPIO2_IO21			0x151e
+			MX93_PAD_GPIO_IO26__GPIO2_IO26			0x151e
+		>;
+	};
+
+	pinctrl_jtag: jtaggrp {
+		fsl,pins = <
+			MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK		0x051e
+			MX93_PAD_DAP_TDI__JTAG_MUX_TDI			0x1200
+			MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO		0x031e
+			MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS		0x1200
 		>;
 	};
 
 	pinctrl_lpi2c3: lpi2c3grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO28__LPI2C3_SDA		0x40000b9e
-			MX93_PAD_GPIO_IO29__LPI2C3_SCL		0x40000b9e
+			/* SION | HYS | OD | FSEL_3 | DSE X4 */
+			MX93_PAD_GPIO_IO28__LPI2C3_SDA			0x4000199e
+			MX93_PAD_GPIO_IO29__LPI2C3_SCL			0x4000199e
 		>;
 	};
 
 	pinctrl_lpi2c5: lpi2c5grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO22__LPI2C5_SDA		0x40000b9e
-			MX93_PAD_GPIO_IO23__LPI2C5_SCL		0x40000b9e
+			/* SION | HYS | OD | FSEL_3 | DSE X4 */
+			MX93_PAD_GPIO_IO22__LPI2C5_SDA			0x4000199e
+			MX93_PAD_GPIO_IO23__LPI2C5_SCL			0x4000199e
+		>;
+	};
+
+	pinctrl_lpspi6: lpspi6grp {
+		fsl,pins = <
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO00__LPSPI6_PCS0			0x011e
+			/* HYS | PD | FSEL_0 | DSE no drive */
+			MX93_PAD_GPIO_IO01__LPSPI6_SIN			0x1400
+			/* PD | FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO02__LPSPI6_SOUT			0x051e
+			MX93_PAD_GPIO_IO03__LPSPI6_SCK			0x051e
+		>;
+	};
+
+	pinctrl_mipi_csi: mipicsigrp {
+		fsl,pins = <
+			MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3		0x051e /* MCLK */
+			MX93_PAD_GPIO_IO10__GPIO2_IO10			0x051e /* TRIGGER */
+			MX93_PAD_GPIO_IO11__GPIO2_IO11			0x1400 /* SYNC */
 		>;
 	};
 
 	pinctrl_pcf85063: pcf85063grp {
 		fsl,pins = <
-			MX93_PAD_SAI1_RXD0__GPIO1_IO14		0x1306
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_SAI1_RXD0__GPIO1_IO14			0x1000
 		>;
 	};
 
 	pinctrl_pexp_irq: pexpirqgrp {
 		fsl,pins = <
-			MX93_PAD_SAI1_TXC__GPIO1_IO12		0x1306
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_SAI1_TXC__GPIO1_IO12			0x1000
 		>;
 	};
 
 	pinctrl_tc9595: tc9595-grp {
 		fsl,pins = <
-			/* DP_IRQ */
-			MX93_PAD_CCM_CLKO4__GPIO4_IO29		0x1306
+			/* HYS | PD | FSEL_0 | no DSE */
+			MX93_PAD_CCM_CLKO4__GPIO4_IO29			0x1400
+		>;
+	};
+
+	pinctrl_temp_sensor_som: tempsensorsomgrp {
+		fsl,pins = <
+			/* HYS | FSEL_0 | no DSE */
+			MX93_PAD_SAI1_TXFS__GPIO1_IO11			0x1000
 		>;
 	};
 
 	pinctrl_tpm5: tpm5grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO06__TPM5_CH0		0x57e
+			MX93_PAD_GPIO_IO06__TPM5_CH0			0x57e
 		>;
 	};
 
 	pinctrl_typec: typecgrp {
 		fsl,pins = <
-			MX93_PAD_I2C2_SCL__GPIO1_IO02		0x1306
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_I2C2_SCL__GPIO1_IO02			0x1000
 		>;
 	};
 
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
-			MX93_PAD_UART1_RXD__LPUART1_RX		0x31e
-			MX93_PAD_UART1_TXD__LPUART1_TX		0x31e
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_UART1_RXD__LPUART1_RX			0x1000
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_UART1_TXD__LPUART1_TX			0x011e
 		>;
 	};
 
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
-			MX93_PAD_UART2_TXD__LPUART2_TX		0x31e
-			MX93_PAD_UART2_RXD__LPUART2_RX		0x31e
-			MX93_PAD_SAI1_TXD0__LPUART2_RTS_B	0x51e
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_UART2_RXD__LPUART2_RX			0x1000
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_UART2_TXD__LPUART2_TX			0x011e
+			MX93_PAD_SAI1_TXD0__LPUART2_RTS_B		0x011e
 		>;
 	};
 
 	pinctrl_uart3: uart3grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO14__LPUART3_TX		0x31e
-			MX93_PAD_GPIO_IO15__LPUART3_RX		0x31e
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_GPIO_IO15__LPUART3_RX			0x1000
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO14__LPUART3_TX			0x011e
 		>;
 	};
 
 	pinctrl_uart6: uart6grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO04__LPUART6_TX		0x31e
-			MX93_PAD_GPIO_IO05__LPUART6_RX		0x31e
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_GPIO_IO05__LPUART6_RX			0x1000
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO04__LPUART6_TX			0x011e
 		>;
 	};
 
 	pinctrl_uart8: uart8grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO12__LPUART8_TX		0x31e
-			MX93_PAD_GPIO_IO13__LPUART8_RX		0x31e
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_GPIO_IO13__LPUART8_RX			0x1000
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO12__LPUART8_TX			0x011e
 		>;
 	};
 
 	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 		fsl,pins = <
-			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_SD2_CD_B__GPIO3_IO00			0x1000
 		>;
 	};
 
 	pinctrl_usdhc2_hs: usdhc2hsgrp {
 		fsl,pins = <
-			/* HYS | PD | PU | FSEL_3 | DSE X5 */
-			MX93_PAD_SD2_CLK__USDHC2_CLK		0x17be
-			/* HYS | PD | PU | FSEL_3 | DSE X4 */
-			MX93_PAD_SD2_CMD__USDHC2_CMD		0x139e
-			/* HYS | PD | PU | FSEL_3 | DSE X3 */
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x138e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x138e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x138e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x138e
-			/* PD | PU | FSEL_2 | DSE X3 */
-			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x50e
+			/* PD | FSEL_3 | DSE X5 */
+			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05be
+			/* HYS | PU | FSEL_3 | DSE X4 */
+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x139e
+			/* HYS | PU | FSEL_3 | DSE X3 */
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x138e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x138e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x138e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x138e
+			/* FSEL_2 | DSE X3 */
+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e
 		>;
 	};
 
 	pinctrl_usdhc2_uhs: usdhc2uhsgrp {
 		fsl,pins = <
-			/* HYS | PD | PU | FSEL_3 | DSE X6 */
-			MX93_PAD_SD2_CLK__USDHC2_CLK		0x17fe
-			/* HYS | PD | PU | FSEL_3 | DSE X4 */
-			MX93_PAD_SD2_CMD__USDHC2_CMD		0x139e
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x139e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x139e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x139e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x139e
-			/* PD | PU | FSEL_2 | DSE X3 */
-			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x50e
+			/* PD | FSEL_3 | DSE X6 */
+			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05fe
+			/* HYS | PU | FSEL_3 | DSE X4 */
+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x139e
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x139e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x139e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x139e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x139e
+			/* FSEL_2 | DSE X3 */
+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e
 		>;
 	};
 };
-- 
2.34.1

[PATCH 07/14] arm64: dts: freescale: imx93-tqma9352-mba93xxla: add irq for temp sensor

[Alexander Stein]

From: Markus Niebel <Markus.Niebel@ew.tq-group.com>

This adds muxing and configuration of the irq output of the temp
sensor on TQMa93xx that is connected to a GPIO line on MBa93xxLA

While at it, add comment for RTC_EVENT for pcf85063 since the IRQ line
of both devices on SoM are routed to CPU GPIO on MBa93xxLA.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 .../boot/dts/freescale/imx93-tqma9352-mba93xxla.dts    | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
index c663b6585c3a..3038c94a1184 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
@@ -452,13 +452,21 @@ &lpuart8 {
 };
 
 &pcf85063 {
-	/* RTC_EVENT# is connected on MBa93xxLA */
+	/* RTC_EVENT# from SoM is connected on mainboard */
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcf85063>;
 	interrupt-parent = <&gpio1>;
 	interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
 };
 
+&se97_som {
+	/* TEMP_EVENT# from SoM is connected on mainboard */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_temp_sensor_som>;
+	interrupt-parent = <&gpio1>;
+	interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+};
+
 &tpm5 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_tpm5>;
-- 
2.34.1

[PATCH 08/14] arm64: dts: freescale: imx93-tqma9352-mba91xxla: Add ethernet aliases

[Alexander Stein]

They are used by systemd to rename network interfaces to predictable
interface names, e.g. end0 & end1.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
index 3038c94a1184..a8870544514f 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
@@ -26,6 +26,8 @@ chosen {
 
 	aliases {
 		eeprom0 = &eeprom0;
+		ethernet0 = &fec;
+		ethernet1 = &eqos;
 		rtc0 = &pcf85063;
 		rtc1 = &bbnsm_rtc;
 	};
-- 
2.34.1

[PATCH 09/14] arm64: dts: freescale: imx93-tqma9352-mba93xxla: add GPIO line names

[Alexander Stein]

From: Markus Niebel <Markus.Niebel@ew.tq-group.com>

Provide GPIO line names for userspace usage, e.g. libgpiod.

While at it, correct the line-name property for ENET[1,2]_INT# gpio hog
and LCD_BLT_EN.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 .../freescale/imx93-tqma9352-mba93xxla.dts    | 55 ++++++++++++++++++-
 1 file changed, 52 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
index a8870544514f..b9a22d6c1de2 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
@@ -209,6 +209,16 @@ &flexcan2 {
 };
 
 &gpio1 {
+	gpio-line-names =
+		/* 00 */ "", "", "USB_C_ALERT#", "PMIC_IRQ#",
+		/* 04 */ "", "", "", "",
+		/* 08 */ "", "", "", "BM2_TEMP_EVENT_MOD#",
+		/* 12 */ "PEX_INT#", "", "RTC_EVENT#", "",
+		/* 16 */ "", "", "", "",
+		/* 20 */ "", "", "", "",
+		/* 24 */ "", "", "", "",
+		/* 28 */ "", "", "", "";
+
 	expander-irq-hog {
 		gpio-hog;
 		gpios = <12 GPIO_ACTIVE_LOW>;
@@ -227,21 +237,60 @@ rtc-irq-hog {
 &gpio2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpio2>;
+
+	gpio-line-names =
+		/* 00 */ "", "", "", "",
+		/* 04 */ "", "", "", "AFE_RESET#",
+		/* 08 */ "AFE_SYNC", "AFE_DRDY", "MIPI_CSI_TRIGGER", "MIPI_CSI_SYNC",
+		/* 12 */ "", "", "", "",
+		/* 16 */ "X1_19", "X1_29", "X1_25", "X1_21",
+		/* 20 */ "X1_23", "X1_17", "", "",
+		/* 24 */ "AFE_INT#", "", "X1_15", "",
+		/* 28 */ "", "", "", "";
 };
 
 &gpio3 {
+	gpio-line-names =
+		/* 00 */ "SD2_CD#", "", "", "",
+		/* 04 */ "", "", "", "SD2_RST#",
+		/* 08 */ "", "", "", "",
+		/* 12 */ "", "", "", "",
+		/* 16 */ "", "", "", "",
+		/* 20 */ "", "", "", "",
+		/* 24 */ "", "", "ENET1_INT#", "ENET2_INT#",
+		/* 28 */ "", "", "", "";
+
 	ethphy-eqos-irq-hog {
 		gpio-hog;
 		gpios = <26 GPIO_ACTIVE_LOW>;
 		input;
-		line-name = "ENET0_IRQ#";
+		line-name = "ENET1_INT#";
 	};
 
 	ethphy-fec-irq-hog {
 		gpio-hog;
 		gpios = <27 GPIO_ACTIVE_LOW>;
 		input;
-		line-name = "ENET1_IRQ#";
+		line-name = "ENET2_INT#";
+	};
+};
+
+&gpio4 {
+	gpio-line-names =
+		/* 00 */ "", "", "", "",
+		/* 04 */ "", "", "", "",
+		/* 08 */ "", "", "", "",
+		/* 12 */ "", "", "", "",
+		/* 16 */ "", "", "", "",
+		/* 20 */ "", "", "", "",
+		/* 24 */ "", "", "", "",
+		/* 28 */ "", "DP_INT", "", "";
+
+	dp-int-hog {
+		gpio-hog;
+		gpios = <29 GPIO_ACTIVE_LOW>;
+		input;
+		line-name = "DP_INT";
 	};
 };
 
@@ -378,7 +427,7 @@ expander2: gpio@72 {
 		#gpio-cells = <2>;
 		vcc-supply = <&reg_3v3>;
 		gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
-				  "LCD_BL_EN", "DP_EN",
+				  "LCD_BLT_EN", "DP_EN",
 				  "MIPI_CSI_EN", "MIPI_CSI_RST#",
 				  "USER_LED1", "USER_LED2";
 	};
-- 
2.34.1

[PATCH 10/14] arm64: dts: freescale: imx93-tqma9352-mba93xxca: improve pad configuration

[Alexander Stein]

From: Markus Niebel <Markus.Niebel@ew.tq-group.com>

- disable PU/PD if already done with external resistors
- do not configure Schmitt Trigger for outputs
- do not configure DSE / FSEL for inputs
- add missing pad groups
- assign muxed GPIO pads for X1 to gpio2 node

Pad config changes suggested by hardware team.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 .../freescale/imx93-tqma9352-mba93xxca.dts    | 235 ++++++++++++------
 1 file changed, 159 insertions(+), 76 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
index 852dd3d2eac7..99a0b6b9e304 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
@@ -289,6 +289,11 @@ tcpc-irq-hog {
 	};
 };
 
+&gpio2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio2>;
+};
+
 &lpi2c3 {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -559,22 +564,23 @@ &iomuxc {
 	pinctrl_eqos: eqosgrp {
 		fsl,pins = <
 			/* PD | FSEL_2 | DSE X4 */
-			MX93_PAD_ENET1_MDC__ENET_QOS_MDC		0x51e
-			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO		0x4000051e
-			/* PD | FSEL_2 | DSE X6 */
-			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0		0x57e
-			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1		0x57e
-			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2		0x57e
-			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3		0x57e
-			/* PD | FSEL_3 | DSE X6 */
-			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x5fe
-			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x57e
+			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x51e
+			/* SION | HYS | FSEL_2 | DSE X4 */
+			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x4000111e
+			/* HYS | FSEL_0 | DSE no drive */
+			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x1000
+			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x1000
+			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x1000
+			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x1000
+			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x1000
+			/* HYS | PD | FSEL_0 | DSE no drive */
+			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x1400
 			/* PD | FSEL_2 | DSE X4 */
-			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0		0x51e
-			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1		0x51e
-			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2		0x51e
-			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3		0x51e
-			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x51e
+			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x51e
+			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x51e
+			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x51e
+			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x51e
+			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x51e
 			/* PD | FSEL_3 | DSE X3 */
 			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e
 		>;
@@ -582,7 +588,8 @@ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e
 
 	pinctrl_eqos_phy: eqosphygrp {
 		fsl,pins = <
-			MX93_PAD_CCM_CLKO1__GPIO3_IO26		0x1306
+			/* HYS | FSEL_0 | DSE no drive */
+			MX93_PAD_CCM_CLKO1__GPIO3_IO26			0x1000
 		>;
 	};
 
@@ -590,15 +597,16 @@ pinctrl_fec: fecgrp {
 		fsl,pins = <
 			/* PD | FSEL_2 | DSE X4 */
 			MX93_PAD_ENET2_MDC__ENET1_MDC			0x51e
-			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000051e
-			/* PD | FSEL_2 | DSE X6 */
-			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e
-			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e
-			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e
-			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e
-			/* PD | FSEL_3 | DSE X6 */
-			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x5fe
-			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e
+			/* SION | HYS | FSEL_2 | DSE X4 */
+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000111e
+			/* HYS | FSEL_0 | DSE no drive */
+			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x1000
+			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x1000
+			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x1000
+			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x1000
+			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x1000
+			/* HYS | PD | FSEL_0 | DSE no drive */
+			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x1400
 			/* PD | FSEL_2 | DSE X4 */
 			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x51e
 			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x51e
@@ -612,147 +620,222 @@ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x58e
 
 	pinctrl_fec_phy: fecphygrp {
 		fsl,pins = <
-			MX93_PAD_CCM_CLKO2__GPIO3_IO27		0x1306
+			/* HYS | FSEL_0 | DSE no drive */
+			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x1000
 		>;
 	};
 
 	pinctrl_flexcan1: flexcan1grp {
 		fsl,pins = <
-			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e
-			MX93_PAD_PDM_CLK__CAN1_TX		0x139e
+			/* HYS | PU | FSEL_0 | DSE no drive */
+			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX		0x1200
+			/* PU | FSEL_3 | DSE X4 */
+			MX93_PAD_PDM_CLK__CAN1_TX			0x039e
 		>;
 	};
 
 	pinctrl_flexcan2: flexcan2grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO25__CAN2_TX		0x139e
-			MX93_PAD_GPIO_IO27__CAN2_RX		0x139e
+			/* HYS | PU | FSEL_0 | DSE no drive */
+			MX93_PAD_GPIO_IO27__CAN2_RX			0x1200
+			/* PU | FSEL_3 | DSE X4 */
+			MX93_PAD_GPIO_IO25__CAN2_TX			0x039e
+		>;
+	};
+
+	pinctrl_gpio2: gpio2grp {
+		fsl,pins = <
+			/* HYS | PD | FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO16__GPIO2_IO16			0x151e
+			MX93_PAD_GPIO_IO17__GPIO2_IO17			0x151e
+			MX93_PAD_GPIO_IO18__GPIO2_IO18			0x151e
+			MX93_PAD_GPIO_IO19__GPIO2_IO19			0x151e
+			MX93_PAD_GPIO_IO20__GPIO2_IO20			0x151e
+			MX93_PAD_GPIO_IO21__GPIO2_IO21			0x151e
+			MX93_PAD_GPIO_IO26__GPIO2_IO26			0x151e
+		>;
+	};
+
+	pinctrl_jtag: jtaggrp {
+		fsl,pins = <
+			MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK		0x051e
+			MX93_PAD_DAP_TDI__JTAG_MUX_TDI			0x1200
+			MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO		0x031e
+			MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS		0x1200
 		>;
 	};
 
 	pinctrl_lpi2c3: lpi2c3grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO28__LPI2C3_SDA		0x40000b9e
-			MX93_PAD_GPIO_IO29__LPI2C3_SCL		0x40000b9e
+			/* SION | HYS | OD | FSEL_3 | DSE X4 */
+			MX93_PAD_GPIO_IO28__LPI2C3_SDA			0x4000199e
+			MX93_PAD_GPIO_IO29__LPI2C3_SCL			0x4000199e
 		>;
 	};
 
 	pinctrl_lpi2c5: lpi2c5grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO22__LPI2C5_SDA		0x40000b9e
-			MX93_PAD_GPIO_IO23__LPI2C5_SCL		0x40000b9e
+			/* SION | HYS | OD | FSEL_3 | DSE X4 */
+			MX93_PAD_GPIO_IO22__LPI2C5_SDA			0x4000199e
+			MX93_PAD_GPIO_IO23__LPI2C5_SCL			0x4000199e
 		>;
 	};
 
 	pinctrl_lpspi6: lpspi6grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO00__LPSPI6_PCS0		0x3fe
-			MX93_PAD_GPIO_IO01__LPSPI6_SIN		0x3fe
-			MX93_PAD_GPIO_IO02__LPSPI6_SOUT		0x3fe
-			MX93_PAD_GPIO_IO03__LPSPI6_SCK		0x3fe
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO00__LPSPI6_PCS0			0x011e
+			/* HYS | PD | FSEL_0 | DSE no drive */
+			MX93_PAD_GPIO_IO01__LPSPI6_SIN			0x1400
+			/* PD | FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO02__LPSPI6_SOUT			0x051e
+			MX93_PAD_GPIO_IO03__LPSPI6_SCK			0x051e
+		>;
+	};
+
+	pinctrl_mipi_csi: mipicsigrp {
+		fsl,pins = <
+			MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3		0x051e /* MCLK */
+			MX93_PAD_GPIO_IO10__GPIO2_IO10			0x051e /* TRIGGER */
+			MX93_PAD_GPIO_IO11__GPIO2_IO11			0x1400 /* SYNC */
+		>;
+	};
+
+	pinctrl_pcf85063: pcf85063grp {
+		fsl,pins = <
+			MX93_PAD_SAI1_RXD0__GPIO1_IO14			0x1000
 		>;
 	};
 
 	pinctrl_pexp_irq: pexpirqgrp {
 		fsl,pins = <
-			MX93_PAD_SAI1_TXC__GPIO1_IO12		0x1306
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_SAI1_TXC__GPIO1_IO12			0x1000
 		>;
 	};
 
 	pinctrl_pwmfan: pwmfangrp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO09__GPIO2_IO09		0x1306
+			/* HYS | PU | FSEL_0 | no DSE */
+			MX93_PAD_GPIO_IO09__GPIO2_IO09			0x1200
+		>;
+	};
+
+	pinctrl_tc9595: tc9595-grp {
+		fsl,pins = <
+			/* HYS | PD | FSEL_0 | no DSE */
+			MX93_PAD_CCM_CLKO4__GPIO4_IO29			0x1400
+		>;
+	};
+
+	pinctrl_temp_sensor_som: tempsensorsomgrp {
+		fsl,pins = <
+			/* HYS | FSEL_0 | no DSE */
+			MX93_PAD_SAI1_TXFS__GPIO1_IO11			0x1000
 		>;
 	};
 
 	pinctrl_tpm5: tpm5grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO06__TPM5_CH0		0x57e
+			MX93_PAD_GPIO_IO06__TPM5_CH0			0x57e
 		>;
 	};
 
 	pinctrl_tpm6: tpm6grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO08__TPM6_CH0		0x57e
+			MX93_PAD_GPIO_IO08__TPM6_CH0			0x57e
 		>;
 	};
 
 	pinctrl_typec: typecgrp {
 		fsl,pins = <
-			MX93_PAD_I2C2_SCL__GPIO1_IO02		0x1306
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_I2C2_SCL__GPIO1_IO02			0x1000
 		>;
 	};
 
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
-			MX93_PAD_UART1_RXD__LPUART1_RX		0x31e
-			MX93_PAD_UART1_TXD__LPUART1_TX		0x31e
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_UART1_RXD__LPUART1_RX			0x1000
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_UART1_TXD__LPUART1_TX			0x011e
 		>;
 	};
 
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
-			MX93_PAD_UART2_TXD__LPUART2_TX		0x31e
-			MX93_PAD_UART2_RXD__LPUART2_RX		0x31e
-			MX93_PAD_SAI1_TXD0__LPUART2_RTS_B   0x51e
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_UART2_RXD__LPUART2_RX			0x1000
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_UART2_TXD__LPUART2_TX			0x011e
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_SAI1_TXD0__LPUART2_RTS_B		0x011e
 		>;
 	};
 
 	pinctrl_uart3: uart3grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO14__LPUART3_TX		0x31e
-			MX93_PAD_GPIO_IO15__LPUART3_RX		0x31e
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_GPIO_IO15__LPUART3_RX			0x1000
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO14__LPUART3_TX			0x011e
 		>;
 	};
 
 	pinctrl_uart6: uart6grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO04__LPUART6_TX		0x31e
-			MX93_PAD_GPIO_IO05__LPUART6_RX		0x31e
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_GPIO_IO05__LPUART6_RX			0x1000
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO04__LPUART6_TX			0x011e
 		>;
 	};
 
 	pinctrl_uart8: uart8grp {
 		fsl,pins = <
-			MX93_PAD_GPIO_IO12__LPUART8_TX		0x31e
-			MX93_PAD_GPIO_IO13__LPUART8_RX		0x31e
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_GPIO_IO13__LPUART8_RX			0x1000
+			/* FSEL_2 | DSE X4 */
+			MX93_PAD_GPIO_IO12__LPUART8_TX			0x011e
 		>;
 	};
 
 	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 		fsl,pins = <
-			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
+			/* HYS | FSEL_0 | No DSE */
+			MX93_PAD_SD2_CD_B__GPIO3_IO00			0x1000
 		>;
 	};
 
 	pinctrl_usdhc2_hs: usdhc2hsgrp {
 		fsl,pins = <
-			/* HYS | PD | PU | FSEL_3 | DSE X5 */
-			MX93_PAD_SD2_CLK__USDHC2_CLK		0x17be
-			/* HYS | PD | PU | FSEL_3 | DSE X4 */
-			MX93_PAD_SD2_CMD__USDHC2_CMD		0x139e
-			/* HYS | PD | PU | FSEL_3 | DSE X3 */
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x138e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x138e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x138e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x138e
-			/* PD | PU | FSEL_2 | DSE X3 */
-			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x50e
+			/* PD | FSEL_3 | DSE X5 */
+			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05be
+			/* HYS | PU | FSEL_3 | DSE X4 */
+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x139e
+			/* HYS | PU | FSEL_3 | DSE X3 */
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x138e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x138e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x138e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x138e
+			/* FSEL_2 | DSE X3 */
+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e
 		>;
 	};
 
 	pinctrl_usdhc2_uhs: usdhc2uhsgrp {
 		fsl,pins = <
-			/* HYS | PD | PU | FSEL_3 | DSE X6 */
-			MX93_PAD_SD2_CLK__USDHC2_CLK		0x17fe
-			/* HYS | PD | PU | FSEL_3 | DSE X4 */
-			MX93_PAD_SD2_CMD__USDHC2_CMD		0x139e
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x139e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x139e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x139e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x139e
-			/* PD | PU | FSEL_2 | DSE X3 */
-			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x50e
+			/* PD | FSEL_3 | DSE X6 */
+			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05fe
+			/* HYS | PU | FSEL_3 | DSE X4 */
+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x139e
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x139e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x139e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x139e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x139e
+			/* FSEL_2 | DSE X3 */
+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e
 		>;
 	};
 };
-- 
2.34.1

[PATCH 11/14] arm64: dts: freescale: imx93-tqma9352-mba93xxca: add RTC / temp sensor IRQ

[Alexander Stein]

From: Markus Niebel <Markus.Niebel@ew.tq-group.com>

The IRQ lines from devices on SoM are connected to CPU GPIO on
this mainboard.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 .../dts/freescale/imx93-tqma9352-mba93xxca.dts   | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
index 99a0b6b9e304..2d979ab085ee 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
@@ -500,6 +500,22 @@ &lpuart8 {
 	status = "okay";
 };
 
+&pcf85063 {
+	/* RTC_EVENT# from SoM is connected on mainboard */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcf85063>;
+	interrupt-parent = <&gpio1>;
+	interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
+};
+
+&se97_som {
+	/* TEMP_EVENT# from SoM is connected on mainboard */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_temp_sensor_som>;
+	interrupt-parent = <&gpio1>;
+	interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+};
+
 &tpm5 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_tpm5>;
-- 
2.34.1

[PATCH 12/14] arm64: dts: freescale: imx93-tqma9352-mba91xxca: Add ethernet aliases

[Alexander Stein]

They are used by systemd to rename network interfaces to predictable
interface names, e.g. end0 & end1.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
index 2d979ab085ee..8a64959e92cb 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
@@ -26,6 +26,8 @@ chosen {
 
 	aliases {
 		eeprom0 = &eeprom0;
+		ethernet0 = &fec;
+		ethernet1 = &eqos;
 		rtc0 = &pcf85063;
 		rtc1 = &bbnsm_rtc;
 	};
-- 
2.34.1

[PATCH 13/14] arm64: dts: freescale: imx93-tqma9352-mba93xxca: add GPIO line names

[Alexander Stein]

From: Markus Niebel <Markus.Niebel@ew.tq-group.com>

Provide GPIO line names for userspace usage, e.g. libgpiod.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 .../freescale/imx93-tqma9352-mba93xxca.dts    | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
index 8a64959e92cb..9a21fbf986fe 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
@@ -276,6 +276,16 @@ &flexcan2 {
 };
 
 &gpio1 {
+	gpio-line-names =
+		/* 00 */ "", "", "USB_C_ALERT#", "PMIC_IRQ#",
+		/* 04 */ "", "", "", "",
+		/* 08 */ "", "", "", "BM2_TEMP_EVENT_MOD#",
+		/* 12 */ "PEX_INT#", "", "RTC_EVENT#", "",
+		/* 16 */ "", "", "", "",
+		/* 20 */ "", "", "", "",
+		/* 24 */ "", "", "", "",
+		/* 28 */ "", "", "", "";
+
 	expander-irq-hog {
 		gpio-hog;
 		gpios = <12 GPIO_ACTIVE_LOW>;
@@ -294,6 +304,40 @@ tcpc-irq-hog {
 &gpio2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpio2>;
+
+	gpio-line-names =
+		/* 00 */ "SPI6_PCS0#", "", "", "",
+		/* 04 */ "", "", "", "",
+		/* 08 */ "", "FAN_RPM", "MIPI_CSI_TRIGGER", "MIPI_CSI_SYNC",
+		/* 12 */ "", "", "", "",
+		/* 16 */ "X1_11", "X1_21", "X1_17", "X1_13",
+		/* 20 */ "X1_15", "X1_9", "", "",
+		/* 24 */ "", "", "X1_7", "",
+		/* 28 */ "", "", "", "";
+};
+
+&gpio3 {
+	gpio-line-names =
+		/* 00 */ "SD2_CD#", "", "", "",
+		/* 04 */ "", "", "", "SD2_RST#",
+		/* 08 */ "", "", "", "",
+		/* 12 */ "", "", "", "",
+		/* 16 */ "", "", "", "",
+		/* 20 */ "", "", "", "",
+		/* 24 */ "", "", "ENET1_INT#", "ENET2_INT#",
+		/* 28 */ "", "", "", "";
+};
+
+&gpio4 {
+	gpio-line-names =
+		/* 00 */ "", "", "", "",
+		/* 04 */ "", "", "", "",
+		/* 08 */ "", "", "", "",
+		/* 12 */ "", "", "", "",
+		/* 16 */ "", "", "", "",
+		/* 20 */ "", "", "", "",
+		/* 24 */ "", "", "", "",
+		/* 28 */ "", "DP_INT", "", "";
 };
 
 &lpi2c3 {
-- 
2.34.1

[PATCH 14/14] arm64: dts: freescale: imx93-tqma9352: set SION for cmd and data pad of USDHC

[Alexander Stein]

From: Markus Niebel <Markus.Niebel@ew.tq-group.com>

imx93 pad integrate has one issue, refer to ERR052021:

ERR052021 uSDHC: Sometimes uSDHC does not work under VDD_SOC low
		 drive mode and nominal mode
Description:
uSDHC PADs have one integration issue.
When CMD/DATA lines direction change from output to input, uSDHC
controller begin sampling, the integration issue will make input
enable signal from uSDHC propagated to the PAD with a long delay,
thus the new input value on the pad comes to uSDHC lately. The
uSDHC sampled the old input value and the sampling result is wrong.

Workaround:
Set uSDHC CMD/DATA PADs iomux register SION bit to 1, then PADs will
propagate input to uSDHC with no delay, so correct value is sampled.

This issue will wrongly trigger the start bit when sample the USDHC
command response, cause the USDHC trigger command CRC/index/endbit
error, which will finally impact the tuning pass window, espically
will impact the standard tuning logic, and can't find a correct delay
cell to get the best timing.

This follows changes made for i.MX93 EVK with commit
bb89601282fc ("arm64: dts: imx93-11x11-evk: set SION for cmd and data pad of USDHC")

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 .../freescale/imx93-tqma9352-mba93xxca.dts    | 22 ++++++++++---------
 .../freescale/imx93-tqma9352-mba93xxla.dts    | 22 ++++++++++---------
 .../boot/dts/freescale/imx93-tqma9352.dtsi    | 19 ++++++++--------
 3 files changed, 34 insertions(+), 29 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
index 9a21fbf986fe..d7c067450503 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
@@ -870,32 +870,34 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00			0x1000
 		>;
 	};
 
+	/* enable SION for data and cmd pad due to ERR052021 */
 	pinctrl_usdhc2_hs: usdhc2hsgrp {
 		fsl,pins = <
 			/* PD | FSEL_3 | DSE X5 */
 			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05be
 			/* HYS | PU | FSEL_3 | DSE X4 */
-			MX93_PAD_SD2_CMD__USDHC2_CMD			0x139e
+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x4000139e
 			/* HYS | PU | FSEL_3 | DSE X3 */
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x138e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x138e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x138e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x138e
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000138e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000138e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000138e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000138e
 			/* FSEL_2 | DSE X3 */
 			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e
 		>;
 	};
 
+	/* enable SION for data and cmd pad due to ERR052021 */
 	pinctrl_usdhc2_uhs: usdhc2uhsgrp {
 		fsl,pins = <
 			/* PD | FSEL_3 | DSE X6 */
 			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05fe
 			/* HYS | PU | FSEL_3 | DSE X4 */
-			MX93_PAD_SD2_CMD__USDHC2_CMD			0x139e
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x139e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x139e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x139e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x139e
+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x4000139e
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000139e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000139e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000139e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000139e
 			/* FSEL_2 | DSE X3 */
 			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e
 		>;
diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
index b9a22d6c1de2..0409dffe844c 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
@@ -820,32 +820,34 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00			0x1000
 		>;
 	};
 
+	/* enable SION for data and cmd pad due to ERR052021 */
 	pinctrl_usdhc2_hs: usdhc2hsgrp {
 		fsl,pins = <
 			/* PD | FSEL_3 | DSE X5 */
 			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05be
 			/* HYS | PU | FSEL_3 | DSE X4 */
-			MX93_PAD_SD2_CMD__USDHC2_CMD			0x139e
+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x4000139e
 			/* HYS | PU | FSEL_3 | DSE X3 */
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x138e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x138e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x138e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x138e
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000138e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000138e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000138e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000138e
 			/* FSEL_2 | DSE X3 */
 			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e
 		>;
 	};
 
+	/* enable SION for data and cmd pad due to ERR052021 */
 	pinctrl_usdhc2_uhs: usdhc2uhsgrp {
 		fsl,pins = <
 			/* PD | FSEL_3 | DSE X6 */
 			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05fe
 			/* HYS | PU | FSEL_3 | DSE X4 */
-			MX93_PAD_SD2_CMD__USDHC2_CMD			0x139e
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x139e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x139e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x139e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x139e
+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x4000139e
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000139e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000139e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000139e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000139e
 			/* FSEL_2 | DSE X3 */
 			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e
 		>;
diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
index 63b02552c55d..ac9f94baf4cd 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
@@ -269,6 +269,7 @@ MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x106
 		>;
 	};
 
+	/* enable SION for data and cmd pad due to ERR052021 */
 	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <
 			/* PD | FSEL 3 | DSE X5 */
@@ -276,16 +277,16 @@ MX93_PAD_SD1_CLK__USDHC1_CLK		0x5be
 			/* HYS | FSEL 0 | no drive */
 			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x1000
 			/* HYS | FSEL 3 | X5 */
-			MX93_PAD_SD1_CMD__USDHC1_CMD		0x11be
+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x400011be
 			/* HYS | FSEL 3 | X4 */
-			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x119e
-			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x119e
-			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x119e
-			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x119e
-			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x119e
-			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x119e
-			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x119e
-			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x119e
+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000119e
+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000119e
+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000119e
+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000119e
+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000119e
+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000119e
+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000119e
+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000119e
 		>;
 	};
 
-- 
2.34.1

RE: [PATCH 01/14] arm64: dts: freescale: imx93-tqma9352: fix CMA alloc-ranges

[Peng Fan]

> Subject: [PATCH 01/14] arm64: dts: freescale: imx93-tqma9352: fix
> CMA alloc-ranges
> 
> From: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> 
> DRAM starts at 0x80000000.
> 
> Fixes: c982ecfa7992 ("arm64: dts: freescale: add initial device tree for
> MBa93xxLA SBC board")
> Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

RE: [PATCH 03/14] arm64: dts: freescale: imx93-tqma9352: Add PMIC node

[Peng Fan]

> Subject: [PATCH 03/14] arm64: dts: freescale: imx93-tqma9352: Add
> PMIC node
> 
> With driver support in place add the PMIC node and remove the fixed-
> regulators for rails provided by PMIC.
> 
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---

Reviewed-by: Peng Fan <peng.fan@nxp.com>

RE: [PATCH 04/14] arm64: dts: freescale: imx93-tqma9352: add eMMC regulators

[Peng Fan]

> Subject: [PATCH 04/14] arm64: dts: freescale: imx93-tqma9352: add
> eMMC regulators
> 
> With PMIC node in place, add the correct regulators for eMMC.
> 
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>


Reviewed-by: Peng Fan <peng.fan@nxp.com>

RE: [PATCH 06/14] arm64: dts: freescale: imx93-tqma9352-mba93xxla: improve pad configuration

[Peng Fan]

> Subject: [PATCH 06/14] arm64: dts: freescale: imx93-tqma9352-
> mba93xxla: improve pad configuration
> 
> From: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> 
> - disable PU/PD if already done with external resistors
> - do not configure Schmitt Trigger for outputs
> - do not configure DSE / FSEL for inputs
> - add missing pad groups
> - assign muxed GPIO pads for X1 to gpio2 node
> 
> Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  .../freescale/imx93-tqma9352-mba93xxla.dts    | 237 ++++++++++++----
> --
>  1 file changed, 164 insertions(+), 73 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-
> mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-
> mba93xxla.dts
> index e2ee9f5a042c..c663b6585c3a 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
> @@ -222,6 +222,11 @@ rtc-irq-hog {
>  	};
>  };
> 
> +&gpio2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_gpio2>;

I am not sure this is correct,  what are this used for?

And this is new, not pad improvement.

I would prefer the other improvement part merged
with patch 2. 

> +};
> +
>  &gpio3 {
>  	ethphy-eqos-irq-hog {
>  		gpio-hog;
> @@ -509,25 +514,39 @@ &usdhc2 {
>  };
> 
>  &iomuxc {
> +	pinctrl_afe: afegrp {

no users?

Regards,
Peng.

RE: [PATCH 07/14] arm64: dts: freescale: imx93-tqma9352-mba93xxla: add irq for temp sensor

[Peng Fan]

> Subject: [PATCH 07/14] arm64: dts: freescale: imx93-tqma9352-
> mba93xxla: add irq for temp sensor
> 
> From: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> 
> This adds muxing and configuration of the irq output of the temp
> sensor on TQMa93xx that is connected to a GPIO line on MBa93xxLA
> 
> While at it, add comment for RTC_EVENT for pcf85063 since the IRQ
> line of both devices on SoM are routed to CPU GPIO on MBa93xxLA.
> 
> Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  .../boot/dts/freescale/imx93-tqma9352-mba93xxla.dts    | 10
> +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-
> mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-
> mba93xxla.dts
> index c663b6585c3a..3038c94a1184 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
> @@ -452,13 +452,21 @@ &lpuart8 {
>  };
> 
>  &pcf85063 {
> -	/* RTC_EVENT# is connected on MBa93xxLA */
> +	/* RTC_EVENT# from SoM is connected on mainboard */
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcf85063>;
>  	interrupt-parent = <&gpio1>;
>  	interrupts = <14 IRQ_TYPE_EDGE_FALLING>;  };
> 
> +&se97_som {
> +	/* TEMP_EVENT# from SoM is connected on mainboard */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_temp_sensor_som>;

pinctrl_temp_sensor_som node node added?

Regards,
Peng.

RE: [PATCH 08/14] arm64: dts: freescale: imx93-tqma9352-mba91xxla: Add ethernet aliases

[Peng Fan]

> Subject: [PATCH 08/14] arm64: dts: freescale: imx93-tqma9352-
> mba91xxla: Add ethernet aliases
> 
> They are used by systemd to rename network interfaces to predictable
> interface names, e.g. end0 & end1.
> 
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---

Reviewed-by: Peng Fan <peng.fan@nxp.com>

RE: [PATCH 09/14] arm64: dts: freescale: imx93-tqma9352-mba93xxla: add GPIO line names

[Peng Fan]

> Subject: [PATCH 09/14] arm64: dts: freescale: imx93-tqma9352-
> mba93xxla: add GPIO line names
> 
> From: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> 
> Provide GPIO line names for userspace usage, e.g. libgpiod.
> 
> While at it, correct the line-name property for ENET[1,2]_INT# gpio hog
> and LCD_BLT_EN.
> 
> Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

RE: [PATCH 10/14] arm64: dts: freescale: imx93-tqma9352-mba93xxca: improve pad configuration

[Peng Fan]

> Subject: [PATCH 10/14] arm64: dts: freescale: imx93-tqma9352-
> mba93xxca: improve pad configuration
> 
> From: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> 
> - disable PU/PD if already done with external resistors
> - do not configure Schmitt Trigger for outputs
> - do not configure DSE / FSEL for inputs
> - add missing pad groups
> - assign muxed GPIO pads for X1 to gpio2 node
> 
> Pad config changes suggested by hardware team.
> 
> Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  .../freescale/imx93-tqma9352-mba93xxca.dts    | 235 ++++++++++++---
> ---
>  1 file changed, 159 insertions(+), 76 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-
> mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-
> mba93xxca.dts
> index 852dd3d2eac7..99a0b6b9e304 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-
> mba93xxca.dts
> @@ -289,6 +289,11 @@ tcpc-irq-hog {
>  	};
>  };
> 
> +&gpio2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_gpio2>;

New change.

I would prefer merge the pad improve into one. But see if
Shawn is ok to separate or merge to one.

Regards,
Peng.

> +};
> +
>  &lpi2c3 {
>  	#address-cells = <1>;
>  	#size-cells = <0>;
> @@ -559,22 +564,23 @@ &iomuxc {
>  	pinctrl_eqos: eqosgrp {
>  		fsl,pins = <
>  			/* PD | FSEL_2 | DSE X4 */
> -			MX93_PAD_ENET1_MDC__ENET_QOS_MDC
> 		0x51e
> -
> 	MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO
> 	0x4000051e
> -			/* PD | FSEL_2 | DSE X6 */
> -
> 	MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0
> 	0x57e
> -
> 	MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1
> 	0x57e
> -
> 	MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2
> 	0x57e
> -
> 	MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3
> 	0x57e
> -			/* PD | FSEL_3 | DSE X6 */
> -
> 	MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE
> _RX_CLK	0x5fe
> -
> 	MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL
> 	0x57e
> +			MX93_PAD_ENET1_MDC__ENET_QOS_MDC
> 			0x51e
> +			/* SION | HYS | FSEL_2 | DSE X4 */
> +
> 	MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO
> 	0x4000111e
> +			/* HYS | FSEL_0 | DSE no drive */
> +
> 	MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0
> 	0x1000
> +
> 	MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1
> 	0x1000
> +
> 	MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2
> 	0x1000
> +
> 	MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3
> 	0x1000
> +
> 	MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL
> 	0x1000
> +			/* HYS | PD | FSEL_0 | DSE no drive */
> +
> 	MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE
> _RX_CLK	0x1400
>  			/* PD | FSEL_2 | DSE X4 */
> -
> 	MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0
> 	0x51e
> -
> 	MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1
> 	0x51e
> -
> 	MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2
> 	0x51e
> -
> 	MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3
> 	0x51e
> -
> 	MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL
> 	0x51e
> +
> 	MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0
> 	0x51e
> +
> 	MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1
> 	0x51e
> +
> 	MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2
> 	0x51e
> +
> 	MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3
> 	0x51e
> +
> 	MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL
> 	0x51e
>  			/* PD | FSEL_3 | DSE X3 */
> 
> 	MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE
> _TX_CLK	0x58e
>  		>;
> @@ -582,7 +588,8 @@
> MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK
> 	0x58e
> 
>  	pinctrl_eqos_phy: eqosphygrp {
>  		fsl,pins = <
> -			MX93_PAD_CCM_CLKO1__GPIO3_IO26
> 	0x1306
> +			/* HYS | FSEL_0 | DSE no drive */
> +			MX93_PAD_CCM_CLKO1__GPIO3_IO26
> 		0x1000
>  		>;
>  	};
> 
> @@ -590,15 +597,16 @@ pinctrl_fec: fecgrp {
>  		fsl,pins = <
>  			/* PD | FSEL_2 | DSE X4 */
>  			MX93_PAD_ENET2_MDC__ENET1_MDC
> 		0x51e
> -			MX93_PAD_ENET2_MDIO__ENET1_MDIO
> 		0x4000051e
> -			/* PD | FSEL_2 | DSE X6 */
> -			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0
> 		0x57e
> -			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1
> 		0x57e
> -			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2
> 		0x57e
> -			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3
> 		0x57e
> -			/* PD | FSEL_3 | DSE X6 */
> -			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC
> 		0x5fe
> -
> 	MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL
> 	0x57e
> +			/* SION | HYS | FSEL_2 | DSE X4 */
> +			MX93_PAD_ENET2_MDIO__ENET1_MDIO
> 		0x4000111e
> +			/* HYS | FSEL_0 | DSE no drive */
> +			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0
> 		0x1000
> +			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1
> 		0x1000
> +			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2
> 		0x1000
> +			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3
> 		0x1000
> +
> 	MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL
> 	0x1000
> +			/* HYS | PD | FSEL_0 | DSE no drive */
> +			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC
> 		0x1400
>  			/* PD | FSEL_2 | DSE X4 */
>  			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0
> 		0x51e
>  			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1
> 		0x51e
> @@ -612,147 +620,222 @@
> MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x58e
> 
>  	pinctrl_fec_phy: fecphygrp {
>  		fsl,pins = <
> -			MX93_PAD_CCM_CLKO2__GPIO3_IO27
> 	0x1306
> +			/* HYS | FSEL_0 | DSE no drive */
> +			MX93_PAD_CCM_CLKO2__GPIO3_IO27
> 		0x1000
>  		>;
>  	};
> 
>  	pinctrl_flexcan1: flexcan1grp {
>  		fsl,pins = <
> -			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX
> 	0x139e
> -			MX93_PAD_PDM_CLK__CAN1_TX
> 	0x139e
> +			/* HYS | PU | FSEL_0 | DSE no drive */
> +			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX
> 		0x1200
> +			/* PU | FSEL_3 | DSE X4 */
> +			MX93_PAD_PDM_CLK__CAN1_TX
> 		0x039e
>  		>;
>  	};
> 
>  	pinctrl_flexcan2: flexcan2grp {
>  		fsl,pins = <
> -			MX93_PAD_GPIO_IO25__CAN2_TX
> 	0x139e
> -			MX93_PAD_GPIO_IO27__CAN2_RX
> 	0x139e
> +			/* HYS | PU | FSEL_0 | DSE no drive */
> +			MX93_PAD_GPIO_IO27__CAN2_RX
> 		0x1200
> +			/* PU | FSEL_3 | DSE X4 */
> +			MX93_PAD_GPIO_IO25__CAN2_TX
> 		0x039e
> +		>;
> +	};
> +
> +	pinctrl_gpio2: gpio2grp {
> +		fsl,pins = <
> +			/* HYS | PD | FSEL_2 | DSE X4 */
> +			MX93_PAD_GPIO_IO16__GPIO2_IO16
> 		0x151e
> +			MX93_PAD_GPIO_IO17__GPIO2_IO17
> 		0x151e
> +			MX93_PAD_GPIO_IO18__GPIO2_IO18
> 		0x151e
> +			MX93_PAD_GPIO_IO19__GPIO2_IO19
> 		0x151e
> +			MX93_PAD_GPIO_IO20__GPIO2_IO20
> 		0x151e
> +			MX93_PAD_GPIO_IO21__GPIO2_IO21
> 		0x151e
> +			MX93_PAD_GPIO_IO26__GPIO2_IO26
> 		0x151e
> +		>;
> +	};
> +
> +	pinctrl_jtag: jtaggrp {
> +		fsl,pins = <
> +
> 	MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK
> 	0x051e
> +			MX93_PAD_DAP_TDI__JTAG_MUX_TDI
> 		0x1200
> +
> 	MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO
> 	0x031e
> +
> 	MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS
> 	0x1200
>  		>;
>  	};
> 
>  	pinctrl_lpi2c3: lpi2c3grp {
>  		fsl,pins = <
> -			MX93_PAD_GPIO_IO28__LPI2C3_SDA
> 	0x40000b9e
> -			MX93_PAD_GPIO_IO29__LPI2C3_SCL
> 	0x40000b9e
> +			/* SION | HYS | OD | FSEL_3 | DSE X4 */
> +			MX93_PAD_GPIO_IO28__LPI2C3_SDA
> 		0x4000199e
> +			MX93_PAD_GPIO_IO29__LPI2C3_SCL
> 		0x4000199e
>  		>;
>  	};
> 
>  	pinctrl_lpi2c5: lpi2c5grp {
>  		fsl,pins = <
> -			MX93_PAD_GPIO_IO22__LPI2C5_SDA
> 	0x40000b9e
> -			MX93_PAD_GPIO_IO23__LPI2C5_SCL
> 	0x40000b9e
> +			/* SION | HYS | OD | FSEL_3 | DSE X4 */
> +			MX93_PAD_GPIO_IO22__LPI2C5_SDA
> 		0x4000199e
> +			MX93_PAD_GPIO_IO23__LPI2C5_SCL
> 		0x4000199e
>  		>;
>  	};
> 
>  	pinctrl_lpspi6: lpspi6grp {
>  		fsl,pins = <
> -			MX93_PAD_GPIO_IO00__LPSPI6_PCS0
> 	0x3fe
> -			MX93_PAD_GPIO_IO01__LPSPI6_SIN
> 	0x3fe
> -			MX93_PAD_GPIO_IO02__LPSPI6_SOUT
> 	0x3fe
> -			MX93_PAD_GPIO_IO03__LPSPI6_SCK
> 	0x3fe
> +			/* FSEL_2 | DSE X4 */
> +			MX93_PAD_GPIO_IO00__LPSPI6_PCS0
> 		0x011e
> +			/* HYS | PD | FSEL_0 | DSE no drive */
> +			MX93_PAD_GPIO_IO01__LPSPI6_SIN
> 		0x1400
> +			/* PD | FSEL_2 | DSE X4 */
> +			MX93_PAD_GPIO_IO02__LPSPI6_SOUT
> 		0x051e
> +			MX93_PAD_GPIO_IO03__LPSPI6_SCK
> 		0x051e
> +		>;
> +	};
> +
> +	pinctrl_mipi_csi: mipicsigrp {
> +		fsl,pins = <
> +
> 	MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3
> 	0x051e /* MCLK */
> +			MX93_PAD_GPIO_IO10__GPIO2_IO10
> 		0x051e /* TRIGGER */
> +			MX93_PAD_GPIO_IO11__GPIO2_IO11
> 		0x1400 /* SYNC */
> +		>;
> +	};
> +
> +	pinctrl_pcf85063: pcf85063grp {
> +		fsl,pins = <
> +			MX93_PAD_SAI1_RXD0__GPIO1_IO14
> 		0x1000
>  		>;
>  	};
> 
>  	pinctrl_pexp_irq: pexpirqgrp {
>  		fsl,pins = <
> -			MX93_PAD_SAI1_TXC__GPIO1_IO12
> 	0x1306
> +			/* HYS | FSEL_0 | No DSE */
> +			MX93_PAD_SAI1_TXC__GPIO1_IO12
> 		0x1000
>  		>;
>  	};
> 
>  	pinctrl_pwmfan: pwmfangrp {
>  		fsl,pins = <
> -			MX93_PAD_GPIO_IO09__GPIO2_IO09
> 	0x1306
> +			/* HYS | PU | FSEL_0 | no DSE */
> +			MX93_PAD_GPIO_IO09__GPIO2_IO09
> 		0x1200
> +		>;
> +	};
> +
> +	pinctrl_tc9595: tc9595-grp {
> +		fsl,pins = <
> +			/* HYS | PD | FSEL_0 | no DSE */
> +			MX93_PAD_CCM_CLKO4__GPIO4_IO29
> 		0x1400
> +		>;
> +	};
> +
> +	pinctrl_temp_sensor_som: tempsensorsomgrp {
> +		fsl,pins = <
> +			/* HYS | FSEL_0 | no DSE */
> +			MX93_PAD_SAI1_TXFS__GPIO1_IO11
> 		0x1000
>  		>;
>  	};
> 
>  	pinctrl_tpm5: tpm5grp {
>  		fsl,pins = <
> -			MX93_PAD_GPIO_IO06__TPM5_CH0
> 	0x57e
> +			MX93_PAD_GPIO_IO06__TPM5_CH0
> 		0x57e
>  		>;
>  	};
> 
>  	pinctrl_tpm6: tpm6grp {
>  		fsl,pins = <
> -			MX93_PAD_GPIO_IO08__TPM6_CH0
> 	0x57e
> +			MX93_PAD_GPIO_IO08__TPM6_CH0
> 		0x57e
>  		>;
>  	};
> 
>  	pinctrl_typec: typecgrp {
>  		fsl,pins = <
> -			MX93_PAD_I2C2_SCL__GPIO1_IO02
> 	0x1306
> +			/* HYS | FSEL_0 | No DSE */
> +			MX93_PAD_I2C2_SCL__GPIO1_IO02
> 		0x1000
>  		>;
>  	};
> 
>  	pinctrl_uart1: uart1grp {
>  		fsl,pins = <
> -			MX93_PAD_UART1_RXD__LPUART1_RX
> 	0x31e
> -			MX93_PAD_UART1_TXD__LPUART1_TX
> 	0x31e
> +			/* HYS | FSEL_0 | No DSE */
> +			MX93_PAD_UART1_RXD__LPUART1_RX
> 		0x1000
> +			/* FSEL_2 | DSE X4 */
> +			MX93_PAD_UART1_TXD__LPUART1_TX
> 		0x011e
>  		>;
>  	};
> 
>  	pinctrl_uart2: uart2grp {
>  		fsl,pins = <
> -			MX93_PAD_UART2_TXD__LPUART2_TX
> 	0x31e
> -			MX93_PAD_UART2_RXD__LPUART2_RX
> 	0x31e
> -			MX93_PAD_SAI1_TXD0__LPUART2_RTS_B
> 0x51e
> +			/* HYS | FSEL_0 | No DSE */
> +			MX93_PAD_UART2_RXD__LPUART2_RX
> 		0x1000
> +			/* FSEL_2 | DSE X4 */
> +			MX93_PAD_UART2_TXD__LPUART2_TX
> 		0x011e
> +			/* FSEL_2 | DSE X4 */
> +			MX93_PAD_SAI1_TXD0__LPUART2_RTS_B
> 		0x011e
>  		>;
>  	};
> 
>  	pinctrl_uart3: uart3grp {
>  		fsl,pins = <
> -			MX93_PAD_GPIO_IO14__LPUART3_TX
> 	0x31e
> -			MX93_PAD_GPIO_IO15__LPUART3_RX
> 	0x31e
> +			/* HYS | FSEL_0 | No DSE */
> +			MX93_PAD_GPIO_IO15__LPUART3_RX
> 		0x1000
> +			/* FSEL_2 | DSE X4 */
> +			MX93_PAD_GPIO_IO14__LPUART3_TX
> 		0x011e
>  		>;
>  	};
> 
>  	pinctrl_uart6: uart6grp {
>  		fsl,pins = <
> -			MX93_PAD_GPIO_IO04__LPUART6_TX
> 	0x31e
> -			MX93_PAD_GPIO_IO05__LPUART6_RX
> 	0x31e
> +			/* HYS | FSEL_0 | No DSE */
> +			MX93_PAD_GPIO_IO05__LPUART6_RX
> 		0x1000
> +			/* FSEL_2 | DSE X4 */
> +			MX93_PAD_GPIO_IO04__LPUART6_TX
> 		0x011e
>  		>;
>  	};
> 
>  	pinctrl_uart8: uart8grp {
>  		fsl,pins = <
> -			MX93_PAD_GPIO_IO12__LPUART8_TX
> 	0x31e
> -			MX93_PAD_GPIO_IO13__LPUART8_RX
> 	0x31e
> +			/* HYS | FSEL_0 | No DSE */
> +			MX93_PAD_GPIO_IO13__LPUART8_RX
> 		0x1000
> +			/* FSEL_2 | DSE X4 */
> +			MX93_PAD_GPIO_IO12__LPUART8_TX
> 		0x011e
>  		>;
>  	};
> 
>  	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
>  		fsl,pins = <
> -			MX93_PAD_SD2_CD_B__GPIO3_IO00
> 	0x31e
> +			/* HYS | FSEL_0 | No DSE */
> +			MX93_PAD_SD2_CD_B__GPIO3_IO00
> 		0x1000
>  		>;
>  	};
> 
>  	pinctrl_usdhc2_hs: usdhc2hsgrp {
>  		fsl,pins = <
> -			/* HYS | PD | PU | FSEL_3 | DSE X5 */
> -			MX93_PAD_SD2_CLK__USDHC2_CLK
> 	0x17be
> -			/* HYS | PD | PU | FSEL_3 | DSE X4 */
> -			MX93_PAD_SD2_CMD__USDHC2_CMD
> 	0x139e
> -			/* HYS | PD | PU | FSEL_3 | DSE X3 */
> -			MX93_PAD_SD2_DATA0__USDHC2_DATA0
> 	0x138e
> -			MX93_PAD_SD2_DATA1__USDHC2_DATA1
> 	0x138e
> -			MX93_PAD_SD2_DATA2__USDHC2_DATA2
> 	0x138e
> -			MX93_PAD_SD2_DATA3__USDHC2_DATA3
> 	0x138e
> -			/* PD | PU | FSEL_2 | DSE X3 */
> -
> 	MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x50e
> +			/* PD | FSEL_3 | DSE X5 */
> +			MX93_PAD_SD2_CLK__USDHC2_CLK
> 		0x05be
> +			/* HYS | PU | FSEL_3 | DSE X4 */
> +			MX93_PAD_SD2_CMD__USDHC2_CMD
> 		0x139e
> +			/* HYS | PU | FSEL_3 | DSE X3 */
> +			MX93_PAD_SD2_DATA0__USDHC2_DATA0
> 		0x138e
> +			MX93_PAD_SD2_DATA1__USDHC2_DATA1
> 		0x138e
> +			MX93_PAD_SD2_DATA2__USDHC2_DATA2
> 		0x138e
> +			MX93_PAD_SD2_DATA3__USDHC2_DATA3
> 		0x138e
> +			/* FSEL_2 | DSE X3 */
> +
> 	MX93_PAD_SD2_VSELECT__USDHC2_VSELECT
> 	0x010e
>  		>;
>  	};
> 
>  	pinctrl_usdhc2_uhs: usdhc2uhsgrp {
>  		fsl,pins = <
> -			/* HYS | PD | PU | FSEL_3 | DSE X6 */
> -			MX93_PAD_SD2_CLK__USDHC2_CLK
> 	0x17fe
> -			/* HYS | PD | PU | FSEL_3 | DSE X4 */
> -			MX93_PAD_SD2_CMD__USDHC2_CMD
> 	0x139e
> -			MX93_PAD_SD2_DATA0__USDHC2_DATA0
> 	0x139e
> -			MX93_PAD_SD2_DATA1__USDHC2_DATA1
> 	0x139e
> -			MX93_PAD_SD2_DATA2__USDHC2_DATA2
> 	0x139e
> -			MX93_PAD_SD2_DATA3__USDHC2_DATA3
> 	0x139e
> -			/* PD | PU | FSEL_2 | DSE X3 */
> -
> 	MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x50e
> +			/* PD | FSEL_3 | DSE X6 */
> +			MX93_PAD_SD2_CLK__USDHC2_CLK
> 		0x05fe
> +			/* HYS | PU | FSEL_3 | DSE X4 */
> +			MX93_PAD_SD2_CMD__USDHC2_CMD
> 		0x139e
> +			MX93_PAD_SD2_DATA0__USDHC2_DATA0
> 		0x139e
> +			MX93_PAD_SD2_DATA1__USDHC2_DATA1
> 		0x139e
> +			MX93_PAD_SD2_DATA2__USDHC2_DATA2
> 		0x139e
> +			MX93_PAD_SD2_DATA3__USDHC2_DATA3
> 		0x139e
> +			/* FSEL_2 | DSE X3 */
> +
> 	MX93_PAD_SD2_VSELECT__USDHC2_VSELECT
> 	0x010e
>  		>;
>  	};
>  };
> --
> 2.34.1
> 

Re: [PATCH 01/14] arm64: dts: freescale: imx93-tqma9352: fix CMA alloc-ranges

[Shawn Guo]

On Wed, Jul 24, 2024 at 02:58:48PM +0200, Alexander Stein wrote:
> From: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> 
> DRAM starts at 0x80000000.
> 
> Fixes: c982ecfa7992 ("arm64: dts: freescale: add initial device tree for MBa93xxLA SBC board")
> Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Applied, thanks!

Re: [PATCH 02/14] arm64: dts: freescale: imx93-tqma9352: improve pad configuration

[Shawn Guo]

On Wed, Jul 24, 2024 at 02:58:49PM +0200, Alexander Stein wrote:
> From: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> 
> - disable PU/PD if already done with external resistors
> - do not configure Schmitt Trigger for outputs
> - do not configure DSE / FSEL for inputs
> 
> Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Applied, thanks!

Re: [PATCH 03/14] arm64: dts: freescale: imx93-tqma9352: Add PMIC node

[Shawn Guo]

On Wed, Jul 24, 2024 at 02:58:50PM +0200, Alexander Stein wrote:
> With driver support in place add the PMIC node and remove the
> fixed-regulators for rails provided by PMIC.
> 
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  .../boot/dts/freescale/imx93-tqma9352.dtsi    | 113 ++++++++++++++----
>  1 file changed, 92 insertions(+), 21 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
> index d07eca6526db..ddb4f452ba2d 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
> @@ -25,20 +25,6 @@ linux,cma {
>  		};
>  	};
>  
> -	reg_v1v8: regulator-v1v8 {
> -		compatible = "regulator-fixed";
> -		regulator-name = "V_1V8";
> -		regulator-min-microvolt = <1800000>;
> -		regulator-max-microvolt = <1800000>;
> -	};
> -
> -	reg_v3v3: regulator-v3v3 {
> -		compatible = "regulator-fixed";
> -		regulator-name = "V_3V3";
> -		regulator-min-microvolt = <3300000>;
> -		regulator-max-microvolt = <3300000>;
> -	};
> -
>  	/* SD2 RST# via PMIC SW_EN */
>  	reg_usdhc2_vmmc: regulator-usdhc2 {
>  		compatible = "regulator-fixed";
> @@ -47,14 +33,14 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
>  		regulator-name = "VSD_3V3";
>  		regulator-min-microvolt = <3300000>;
>  		regulator-max-microvolt = <3300000>;
> -		vin-supply = <&reg_v3v3>;
> +		vin-supply = <&buck4>;
>  		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
>  		enable-active-high;
>  	};
>  };
>  
>  &adc1 {
> -	vref-supply = <&reg_v1v8>;
> +	vref-supply = <&buck5>;
>  };
>  
>  &flexspi1 {
> @@ -105,6 +91,91 @@ se97_som: temperature-sensor@1b {
>  		reg = <0x1b>;
>  	};
>  
> +	pca9451a: pmic@25 {
> +		compatible = "nxp,pca9451a";
> +		reg = <0x25>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_pca9451>;
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> +
> +		regulators {
> +			/* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */
> +			buck1: BUCK1 {
> +				regulator-name = "BUCK1";
> +				regulator-min-microvolt = <750000>;
> +				regulator-max-microvolt = <900000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <3125>;
> +			};
> +
> +			/* V_DDRQ - 1.1 LPDDR4 or 0.6 LPDDR4X */
> +			buck2: BUCK2 {
> +				regulator-name = "BUCK2";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <1100000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <3125>;
> +			};
> +
> +			/* V_3V3 - EEPROM, RTC, ... */
> +			buck4: BUCK4{

Missing space before braces.

> +				regulator-name = "BUCK4";
> +				regulator-min-microvolt = <3300000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			/* V_1V8 - SPI NOR, eMMC, RAM VDD1... */
> +			buck5: BUCK5{

Ditto

Shawn

> +				regulator-name = "BUCK5";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			/* V_1V1 - RAM VDD2*/
> +			buck6: BUCK6 {
> +				regulator-name = "BUCK6";
> +				regulator-min-microvolt = <1100000>;
> +				regulator-max-microvolt = <1100000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			/* V_1V8_BBSM, fix 1.8 */
> +			ldo1: LDO1 {
> +				regulator-name = "LDO1";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			/* V_0V8_ANA */
> +			ldo4: LDO4 {
> +				regulator-name = "LDO4";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <800000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			/* V_SD2 - 3.3/1.8V USDHC2 io Voltage */
> +			ldo5: LDO5 {
> +				regulator-name = "LDO5";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +		};
> +	};
> +
>  	pcf85063: rtc@51 {
>  		compatible = "nxp,pcf85063a";
>  		reg = <0x51>;
> @@ -116,28 +187,28 @@ eeprom0: eeprom@53 {
>  		reg = <0x53>;
>  		pagesize = <16>;
>  		read-only;
> -		vcc-supply = <&reg_v3v3>;
> +		vcc-supply = <&buck4>;
>  	};
>  
>  	eeprom1: eeprom@57 {
>  		compatible = "atmel,24c64";
>  		reg = <0x57>;
>  		pagesize = <32>;
> -		vcc-supply = <&reg_v3v3>;
> +		vcc-supply = <&buck4>;
>  	};
>  
>  	/* protectable identification memory (part of M24C64-D @57) */
>  	eeprom@5f {
>  		compatible = "atmel,24c64d-wl";
>  		reg = <0x5f>;
> -		vcc-supply = <&reg_v3v3>;
> +		vcc-supply = <&buck4>;
>  	};
>  
>  	imu@6a {
>  		compatible = "st,ism330dhcx";
>  		reg = <0x6a>;
> -		vdd-supply = <&reg_v3v3>;
> -		vddio-supply = <&reg_v3v3>;
> +		vdd-supply = <&buck4>;
> +		vddio-supply = <&buck4>;
>  	};
>  };
>  
> -- 
> 2.34.1
> 

Re: [PATCH 05/14] arm64: dts: freescale: imx93-tqma9352-mba93xxla: fix typo

[Shawn Guo]

On Wed, Jul 24, 2024 at 02:58:52PM +0200, Alexander Stein wrote:
> From: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> 
> Fix typo in assignment of SD-Card cd-gpios.
> 
> Fixes: c982ecfa7992 ("arm64: dts: freescale: add initial
> device tree for MBa93xxLA SBC board")
> 
> Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Applied, thanks!

Re: [PATCH 06/14] arm64: dts: freescale: imx93-tqma9352-mba93xxla: improve pad configuration

[Alexander Stein]

Hi Peng,

thanks for the review.

Am Donnerstag, 1. August 2024, 05:04:49 CEST schrieb Peng Fan:
> > Subject: [PATCH 06/14] arm64: dts: freescale: imx93-tqma9352-
> > mba93xxla: improve pad configuration
> > 
> > From: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> > 
> > - disable PU/PD if already done with external resistors
> > - do not configure Schmitt Trigger for outputs
> > - do not configure DSE / FSEL for inputs
> > - add missing pad groups
> > - assign muxed GPIO pads for X1 to gpio2 node
> > 
> > Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
> > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > ---
> >  .../freescale/imx93-tqma9352-mba93xxla.dts    | 237 ++++++++++++----
> > --
> >  1 file changed, 164 insertions(+), 73 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-
> > mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-
> > mba93xxla.dts
> > index e2ee9f5a042c..c663b6585c3a 100644
> > --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
> > @@ -222,6 +222,11 @@ rtc-irq-hog {
> >  	};
> >  };
> > 
> > +&gpio2 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_gpio2>;
> 
> I am not sure this is correct,  what are this used for?

This is for general GPIOs usable from userspace. I'll add a new patch for
adding gpio-line-names, so it should be clear.

> And this is new, not pad improvement.

Okay, I'll separate the changes from adding new/missing ones.

> I would prefer the other improvement part merged
> with patch 2. 

Patch 2 already got merged, but despite that this patch is for the mainboard
while patch is addressing the module only.

> > +};
> > +
> >  &gpio3 {
> >  	ethphy-eqos-irq-hog {
> >  		gpio-hog;
> > @@ -509,25 +514,39 @@ &usdhc2 {
> >  };
> > 
> >  &iomuxc {
> > +	pinctrl_afe: afegrp {
> 
> no users?

There is no driver yet, but the pinctrl settings can still be created
meanwhile.

Thanks and best regards,
Alexander
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