From: JieGan <quic_jiegan@quicinc.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Jinlong Mao <quic_jinlmao@quicinc.com>,
<coresight@lists.linaro.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
Tingwei Zhang <quic_tingweiz@quicinc.com>,
Yuanfang Zhang <quic_yuanfang@quicinc.com>,
Tao Zhang <quic_taozha@quicinc.com>,
Song Chai <quic_songchai@quicinc.com>,
<linux-arm-msm@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>
Subject: Re: [PATCH v3 3/5] dt-bindings: arm: Add Coresight TMC Control Unit hardware
Date: Mon, 19 Aug 2024 17:06:41 +0800 [thread overview]
Message-ID: <ZsMLIRoDMmbH7vM0@jiegan-gv.ap.qualcomm.com> (raw)
In-Reply-To: <e087b788-4002-4d12-bd8f-a40fc814856a@kernel.org>
On Mon, Aug 19, 2024 at 08:26:19AM +0200, Krzysztof Kozlowski wrote:
> On 12/08/2024 04:41, Jie Gan wrote:
> > +
> > +maintainers:
> > + - Yuanfang Zhang <quic_yuanfang@quicinc.com>
> > + - Mao Jinlong <quic_jinlmao@quicinc.com>
> > + - Jie Gan <quic_jiegan@quicinc.com>
> > +
> > +description:
> > + The Coresight TMC Control unit controls various Coresight behaviors.
> > + It works as a helper device when connected to TMC ETR device.
> > + It is responsible for controlling the data filter function based on
> > + the source device's Trace ID for TMC ETR device. The trace data with
> > + that Trace id can get into ETR's buffer while other trace data gets
> > + ignored.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - qcom,sa8775p-ctcu
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + clock-names:
> > + items:
> > + - const: apb
> > +
> > + in-ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
> > + patternProperties:
> > + '^port(@[0-7])?$':
>
> I see only two ports in the example. How many are there in reality?
Existing projects can have a maximum of two ports. I used the range 0-7 as I consider
it unlikely to have more than 8 ports. Maybe it's intended as a large buffer for
futher design needs.
>
> Best regards,
> Krzysztof
>
Thanks,
Jie
next prev parent reply other threads:[~2024-08-19 9:07 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-12 2:41 [PATCH v3 0/5] Coresight: Add Coresight TMC Control Unit driver Jie Gan
2024-08-12 2:41 ` [PATCH v3 1/5] Coresight: Add support for new APB clock name Jie Gan
2024-08-12 2:41 ` [PATCH v3 2/5] Coresight: Add trace_id function to retrieving the trace ID Jie Gan
2024-08-12 2:41 ` [PATCH v3 3/5] dt-bindings: arm: Add Coresight TMC Control Unit hardware Jie Gan
2024-08-18 14:28 ` Rob Herring
2024-08-19 1:49 ` JieGan
2024-08-19 6:25 ` Krzysztof Kozlowski
2024-08-19 8:51 ` JieGan
2024-08-19 9:51 ` Krzysztof Kozlowski
2024-08-20 6:36 ` JieGan
2024-08-22 9:55 ` Krzysztof Kozlowski
2024-08-22 11:43 ` Suzuki K Poulose
2024-08-19 6:26 ` Krzysztof Kozlowski
2024-08-19 9:06 ` JieGan [this message]
2024-08-19 9:41 ` Krzysztof Kozlowski
2024-08-19 9:50 ` JieGan
2024-08-12 2:41 ` [PATCH v3 4/5] Coresight: Add Coresight TMC Control Unit driver Jie Gan
2024-08-12 2:41 ` [PATCH v3 5/5] arm64: dts: qcom: Add CTCU and ETR nodes for SA8775p Jie Gan
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