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Shutemov" Subject: Re: [PATCH v4 02/10] riscv: Add ISA extension parsing for pointer masking Message-ID: References: <20240829010151.2813377-1-samuel.holland@sifive.com> <20240829010151.2813377-3-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240829010151.2813377-3-samuel.holland@sifive.com> On Wed, Aug 28, 2024 at 06:01:24PM -0700, Samuel Holland wrote: > The RISC-V Pointer Masking specification defines three extensions: > Smmpm, Smnpm, and Ssnpm. Add support for parsing each of them. The > specific extension which provides pointer masking support to userspace > (Supm) depends on the kernel's privilege mode, so provide a macro to > abstract this selection. > > Smmpm implies the existence of the mseccfg CSR. As it is the only user > of this CSR so far, there is no need for an Xlinuxmseccfg extension. > > Signed-off-by: Samuel Holland Reviewed-by: Charlie Jenkins > --- > > (no changes since v3) > > Changes in v3: > - Rebase on riscv/for-next (ISA extension list conflicts) > - Remove RISCV_ISA_EXT_SxPM, which was not used anywhere > > Changes in v2: > - Provide macros for the extension affecting the kernel and userspace > > arch/riscv/include/asm/hwcap.h | 5 +++++ > arch/riscv/kernel/cpufeature.c | 3 +++ > 2 files changed, 8 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 5a0bd27fd11a..aff21c6fc9b6 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -92,6 +92,9 @@ > #define RISCV_ISA_EXT_ZCF 83 > #define RISCV_ISA_EXT_ZCMOP 84 > #define RISCV_ISA_EXT_ZAWRS 85 > +#define RISCV_ISA_EXT_SMMPM 86 > +#define RISCV_ISA_EXT_SMNPM 87 > +#define RISCV_ISA_EXT_SSNPM 88 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > @@ -100,8 +103,10 @@ > > #ifdef CONFIG_RISCV_M_MODE > #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA > +#define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SMNPM > #else > #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA > +#define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SSNPM > #endif > > #endif /* _ASM_RISCV_HWCAP_H */ > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index b3b9735cb19a..ba3dc16e14dc 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -377,9 +377,12 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), > __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > + __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), > + __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts), > __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > + __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts), > __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > -- > 2.45.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv