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[71.34.69.82]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20b37e357e8sm4132645ad.187.2024.09.26.18.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2024 18:25:20 -0700 (PDT) Date: Thu, 26 Sep 2024 18:25:18 -0700 From: Drew Fustini To: Andrew Lunn Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Jisheng Zhang , Maxime Coquelin , Emil Renner Berthing , Drew Fustini , Guo Ren , Fu Wei , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v2 3/3] riscv: dts: thead: Add TH1520 ethernet nodes Message-ID: References: <20240926-th1520-dwmac-v2-0-f34f28ad1dc9@tenstorrent.com> <20240926-th1520-dwmac-v2-3-f34f28ad1dc9@tenstorrent.com> <3e26f580-bc5d-448e-b5bd-9b607c33702b@lunn.ch> <0b49b681-2289-412a-8969-d134ffcfb7fc@lunn.ch> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0b49b681-2289-412a-8969-d134ffcfb7fc@lunn.ch> On Thu, Sep 26, 2024 at 09:30:32PM +0200, Andrew Lunn wrote: > On Thu, Sep 26, 2024 at 12:13:06PM -0700, Drew Fustini wrote: > > On Thu, Sep 26, 2024 at 08:39:29PM +0200, Andrew Lunn wrote: > > > > +&mdio0 { > > > > + phy0: ethernet-phy@1 { > > > > + reg = <1>; > > > > + }; > > > > + > > > > + phy1: ethernet-phy@2 { > > > > + reg = <2>; > > > > + }; > > > > +}; > > > > > > Two PHYs on one bus... > > > > Thanks for pointing this out. I will move phy1 to mdio1. > > ??? > > Are you saying the two PHYs are not on the same bus? Sorry, this is my first time working on an Ethernet driver and I misunderstood. Sipeed only shares the schematic of the baseboard for the LPi4a [1]. There are pages for GMAC Ethernet0 and GMAC Ethernet1. Each shows 4 MDIO differential pairs going into a SG4301G transformer. I believe that RTL8211F-CG phy chips are on the LM4A SoM board which contains the TH1520 SoC. Unfortunately, Sipeed does not provide a schematic of the SoM so its hard for me to inspect how the phy chips are wired up. Vendor kernel [2] that Sipeed uses has: mdio0 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; phy_88E1111_0: ethernet-phy@0 { reg = <0x1>; }; phy_88E1111_1: ethernet-phy@1 { reg = <0x2>; }; }; so I think that does mean they are on the same MDIO bus. > > > > > + gmac1: ethernet@ffe7060000 { > > > > + compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; > > > > + reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; > > > > + reg-names = "dwmac", "apb"; > > > > + interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; > > > > + interrupt-names = "macirq"; > > > > + clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC_AXI>; > > > > + clock-names = "stmmaceth", "pclk"; > > > > + snps,pbl = <32>; > > > > + snps,fixed-burst; > > > > + snps,multicast-filter-bins = <64>; > > > > + snps,perfect-filter-entries = <32>; > > > > + snps,axi-config = <&stmmac_axi_config>; > > > > + status = "disabled"; > > > > + > > > > + mdio1: mdio { > > > > + compatible = "snps,dwmac-mdio"; > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + }; > > > > + }; > > > > + > > > > + gmac0: ethernet@ffe7070000 { > > > > + compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; > > > > + reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; > > > > + reg-names = "dwmac", "apb"; > > > > + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; > > > > + interrupt-names = "macirq"; > > > > + clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC_AXI>; > > > > > > And the MACs are listed in opposite order. Does gmac1 probe first, > > > find the PHY does not exist, and return -EPROBE_DEFER. Then gmac0 > > > probes successfully, and then sometime later gmac1 then reprobes? > > > > > > I know it is normal to list nodes in address order, but you might be > > > able to avoid the EPROBE_DEFER if you reverse the order. > > > > The probe order seems to always be the ethernet@ffe7060000 (gmac1) first > > and then ethernet@ffe7070000 (gmac0). I do not see any probe deferral > > in the boot log [1]. > > > [1] https://gist.github.com/pdp7/02a44b024bdb6be5fe61ac21303ab29a > > So two PHYs are found, so they must be on the same bus. > > It could well be that this MAC driver does not connect to the PHY > until the interface is opened. That is a good 30 seconds after the > driver probes in this log message. So there has been plenty of time > for the PHYs to be found. > > What would be interesting is if you used NFS root. Then the interface > would be opened much faster, and you might see an EPROBE_DEFER. But > i'm just speculating. If it works for you, there is no need to do > more. > > Andrew I tried to setup an nfs server with a rootfs on my local network. I can mount it okay from my laptop so I think it is working okay. However, it does not seem to work on the lpi4a [3]. It appears the rgmii-id validation fails and the dwmac driver can not open the phy: thead-dwmac ffe7060000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0 thead-dwmac ffe7060000.ethernet eth0: validation of rgmii-id with support \ 00,00000000,00000000,00006280 and advertisementa \ 00,00000000,00000000,00006280 failed: -EINVAL thead-dwmac ffe7060000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -22) I suppose that this is what you were talking about that NFS will cause the interface to be opened much faster. Thanks, Drew [1] https://dl.sipeed.com/shareURL/LICHEE/licheepi4a/02_Schematic [2] https://github.com/revyos/thead-kernel/blob/lpi4a/arch/riscv/boot/dts/thead/th1520-b-product.dts#L758 [3] https://gist.github.com/pdp7/458eb93509548383beabeb21c8ffc43a