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From: Johan Hovold <johan@kernel.org>
To: Abel Vesa <abel.vesa@linaro.org>
Cc: Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Trilok Soni <quic_tsoni@quicinc.com>,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] arm64: dts: qcom: x1e80100-crd: Enable external DP support
Date: Wed, 16 Oct 2024 10:06:30 +0200	[thread overview]
Message-ID: <Zw90BlPCopp-Tp49@hovoldconsulting.com> (raw)
In-Reply-To: <20240902-x1e80100-crd-dts-add-external-dp-support-v1-1-899c264c0eb7@linaro.org>

On Mon, Sep 02, 2024 at 06:01:35PM +0300, Abel Vesa wrote:
> The Qualcomm Snapdragon X Elite CRD board has 3 USB Type-C ports,
> all of them supporting external DP altmode. Between each QMP
> combo PHY and the corresponding Type-C port, sits one Parade PS8830
> retimer which handles both orientation and SBU muxing. Add nodes for
> each retimer, fix the graphs between connectors and the PHYs accordingly,
> add the voltage regulators needed by each retimer and then enable all
> 3 remaining DPUs.
> 
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
 
> +	vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
> +		compatible = "regulator-fixed";
> +
> +		regulator-name = "VREG_RTMR0_1P15";
> +		regulator-min-microvolt = <1150000>;
> +		regulator-max-microvolt = <1150000>;
> +
> +		gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>;

When reviewing the schematics yesterday, I noticed that this is wrong
and that this enable GPIO comes from pmc8380_5_gpios.

Fortunately the above gpio is unused, but please double check the other
as well (I think the rest are correct).

You need to fix the pincfg as well.

> +		enable-active-high;
> +
> +		pinctrl-0 = <&rtmr0_1p15_reg_en>;

Please rename the enable pins according to the schematics too (e.g.
"usb0_pwr_1p15_en").

> +		pinctrl-names = "default";
> +	};

> +&i2c1 {
> +	clock-frequency = <400000>;
> +
> +	status = "okay";
> +
> +	typec-mux@8 {
> +		compatible = "parade,ps8830";
> +		reg = <0x08>;
> +
> +		clocks = <&rpmhcc RPMH_RF_CLK5>;
> +		clock-names = "xo";
> +
> +		vdd15-supply = <&vreg_rtmr2_1p15>;
> +		vdd18-supply = <&vreg_rtmr2_1p8>;
> +		vdd33-supply = <&vreg_rtmr2_3p3>;
> +
> +		reset-gpios = <&tlmm 185 GPIO_ACTIVE_HIGH>;

As I mentioned elsewhere, the reset lines are active low.

> +&pm8550_gpios {
> +	rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state {
> +		pins = "gpio11";
> +		function = "func1";

And this should be "normal" for gpio function, right? Same below.

> +		input-disable;
> +		output-enable;

And I don't think you need to provide these.

> +	};
> +};

Johan

  parent reply	other threads:[~2024-10-16  8:06 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-02 15:01 [PATCH 0/2] arm64: dts: qcom: x1e80100: Add external DP support to CRD and T14s Abel Vesa
2024-09-02 15:01 ` [PATCH 1/2] arm64: dts: qcom: x1e80100-crd: Enable external DP support Abel Vesa
2024-09-02 18:54   ` Dmitry Baryshkov
2024-09-02 20:05     ` Konrad Dybcio
2024-09-24 11:08     ` Abel Vesa
2024-09-24 12:03       ` Dmitry Baryshkov
2024-09-03  7:09   ` Johan Hovold
2024-09-24 10:58     ` Abel Vesa
2024-10-16  8:06   ` Johan Hovold [this message]
2024-10-16  8:18   ` Johan Hovold
2024-09-02 15:01 ` [PATCH 2/2] arm64: dts: qcom: x1e80100-t14s: Add " Abel Vesa
2024-09-03  7:05   ` Johan Hovold
2024-09-24 11:13     ` Abel Vesa

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