Re: [PATCH v3] arm64: dts: qcom: x1e80100: Fix PCIe 6a lanes description

[Johan Hovold <johan@kernel.org>]

On Wed, Oct 09, 2024 at 02:07:23PM +0300, Abel Vesa wrote:
> Fix the description and compatible for PCIe 6a, as it is in fact a
> 4-lanes controller and PHY, but it can also be used in 2-lanes mode. For
> 4-lanes mode, it uses the lanes provided by PCIe 6b. For 2-lanes mode,
> PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. The number
> of lanes in which the PHY should be configured depends on a TCSR register
> value on each individual board.
> 
> Cc: stable+noautosel@kernel.org # Depends on pcie-qcom 16.0 GT/s support
> Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes")
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> Changes in v3:
> - Re-worded the commit message once more to suggest a fix w.r.t
>   lanes.
> - Added back fixes tag and CC stable but with noautosel reason
> - Picked up Konrad's R-b tag.
> - Link to v2: https://lore.kernel.org/r/20241004-x1e80100-dts-fixes-pcie6a-v2-1-3af9ff7a5a71@linaro.org
> 
> Changes in v2:
> - Re-worded the commit message according to Johan's suggestions
> - Dropped the clocks changes.
> - Dropped the fixes tag as this relies on the Gen4 4-lanes stability
>   patchset which has been only merged in 6.12, so backporting this patch
>   would break NVMe support for all platforms.
> - Link to v1: https://lore.kernel.org/r/20240531-x1e80100-dts-fixes-pcie6a-v1-2-1573ebcae1e8@linaro.org

Thanks for the update. I find the commit message much clearer now:

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>

Johan